Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
In article 41C67EA6@rice.edu, Michael Filippo <filippo@rice.edu> () writes: >Let me try it again... > >Does anyone know where (or if) I can get ECL or PECL (preferrable) gate arrays >or FPGAs? I'm trying to design a high-speed (100 MHz) crossbar switch and I need >some way to build multiple multi-bit 16-1 MUXs. I've looked at Lattice's CPLDs >(1K, 2K, and 3K families), but I have serious doubts about their performance. I'm >laess concerned with the propagation delay than I am about the output edge rates. I >assume I can skew the clock for the receiving latch to compensate for the prop. >delay (assuming I can fix it in a range), but I can't very well have a 10 ns period >if I have 5ns (or more) edge rates. Any suggestions? > >-- >Mike Filippo >filippo@rice.edu >http://www-ce.rice.edu/ce/members/filippo/htdocs/filippo.html Have you looked at Vitesse Semiconductor's GaAs gate arrays? I can't imagine these would be terribly thrifty solutions for limited production runs of thesis projects, but others in the commercial world may wish to consider them. http://www.hp.com/csocat/eda/asicpages/vitesse.htm Good Luck, Bob Elkind ************************************************************************** Bob Elkind email:eteam@aracnet.com CIS:72022,21 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ******** Video processing, R&D, ASIC, FPGA design consulting *************Article: 3226
In article <4lqme8$2iq@news.tiac.net>, Eric Ryherd <eric@vautomation.com> wrote: > Does anyone have a reference on the annual number of FPGAs shipped > (or even revenue) by the top 3 FPGA companies. > > I assume the order is > 1) Xilinx, > 2) Altera, > 3) Actel. > Here are the calendar 1995 revenue numbers for the biggest players in the Programmable Logic Market: Xilinx $ 520 M Altera $ 402 M AMD $ 285 M Lattice $ 185 M Actel $ 106 M Cypress $ 76 M. Xilinx sales are mainly SRAM-based FPGAs, plus some CPLDs and some Antifuse-based FPGAs. Altera does not call any of its devices "FPGA", and most of their sales are CPLDs in EPROM and EEPROM technology. AMD is 100% CPLDs and PALs. Lattice is CPLDs and GALs. Actel is 100% antifuse-based FPGAs. Cypress is mostly CPLDs. I hope nobody is confused or offended by this explanation of the alphabet-soup. FPGA stands for Field-Programmable Gate Array, CPLD stands for Complex Programmable Logic Device PAL stands for Programmable Array Logic, trademarked by AMD GAL stands for Generic Array logic, trademarked by Lattice. EPROM stands for Erasable Programmable Read-Only Memory, and EEPROM stands for Electrically Erasable Programmable Read-Only Memory. Wow! Peter Alfke, Xilinx ApplicationsArticle: 3227
Dear Friends, when I synthesized my VHDL design, I notice from the report that the number of C-module exceeds the max C-module number of the target device. However, there are a lot left for the S-module resource. So I wonder if it is possible that those unused S-modules could possibly used as C-modules in the place and route stage. I think the utilization of Actel FPGA should be on the basis of (S-module + C-module) alltogether rather than C-module or S-module individually, right?! Regards, Felix K.C. CHEN -- --------------------------------- Felix, Kuan-chih CHEN (³¯ «a §Ó) Associate Project Manager System Product Division D-Link Co., Hsin-chu, Taiwan Email: flxchen@diig.dlink.com.tw Machines and tools are only as good as the people who use it. ---------------------------------Article: 3228
In article <mbuttsDqMt7C.JpD@netcom.com>, Mike Butts <mbutts@netcom.com> wrote: >guccione@xilinx.com (Steve Guccione) writes: > >>(...Stuff about FPGAs and CPUs working together deleted...) > >>I agree that a 400 MHz Alpha is able to get a lot of work done in a >>short time. But the problem is the memory interface. When you start >>getting cache misses, performance drops dramatically. > >Precisely. The most fundamental, and potentially the most important >difference between CPUs and FCCMs is the processor-memory model. > >The sequential Von Neumann CPU model has a single unified memory >space with only a single sequence of memory accesses permitted. >Implementations of CPUs, memory systems and compilers infer some >parallelism beyond that, but the model that programmers >must code to is still limited to that sequential, one reference at >a time model. > >FCCMs need not share that limitation. > > --Mike I have to disagree a bit. I think that FCCMs with multiple memories are inherently more difficult to program. As are multiprocessors. The problem is that the data is never where you want it, when you want it. And moving it can get expensive. Also, while multiple memories increase the bandwidth to the processor, accessing the data in these memories from the host computer becomes the bottleneck. I favor single memory FCCMs that exploit pipelining and customization of basic operations. I believe this will give a more balanced system and make program easier. BTW, a peeve of mine is memory interfacing on existing hardware. The justification for most of the designs seems to be along the lines of "I had these extra pins, so I hooked up some SRAM" (1/2 :^) -- Steve -- 4/30/96Article: 3229
venus@sunnyboy.ws.ba.dlr.de wrote: > I am looking for FPGA (5000 .. 20000 gates) for a apace application. > I know the Actel/Loral 1280. > Are there any other FPGA available for such kind of application. The needed > total dose is about 10 to 20 Krad(Si). Are there any radiation test data > available? What oubout SEU and latch up? Probably not. Once upon a time, Harris was making a Xilinx 3000 compatible device, but they dropped it. I got a note from an engineer at Vitesse saying that they are considering a GaAs SRAM-based FPGA. Their goal is speed, not rad-hardening, but GaAs is inherently more rad hard than silicon, so it might work. You can contact him at: Wayland Jeong Principal Engineer Vitesse Semiconductor Phone: 1-805-445-2212 Email: wayland@vitsemi.com It's not likely that an SRAM or EEPROM based device will be as rad-hard as a fuse-based device.Article: 3230
In article <4m555j$nlc@fnnews.fnal.gov>, husby@fnal.gov (Don Husby) wrote:
~venus@sunnyboy.ws.ba.dlr.de wrote:
~> I am looking for FPGA (5000 .. 20000 gates) for a apace application.
~> I know the Actel/Loral 1280.
~> Are there any other FPGA available for such kind of application. The needed
~> total dose is about 10 to 20 Krad(Si). Are there any radiation test data
~> available? What oubout SEU and latch up?
~
~Probably not. Once upon a time, Harris was making a Xilinx 3000 compatible
~device, but they dropped it.
We are in the process of designing a RAD-HARD FPGA which will exceed the
specifications you had mentioned (ie. SEU << 1e-9 err/bit-day). It will be
based on look-up table programming and will be re-programmable. What is your
time frame? Contact me if you would like more information. We would like to
know your future requirements as far as size, radiation, speed, etc.
Richard Greene EMAIL r.greene@ieee.org
--------------------------------------------------------------------
_______ _______ ?
/ _____ \ / _____ \ AEROSPACE DESIGN CONCEPTS ^
/ / \ \ / / \ \ MEMORIES INTO SPACE ^
__/ /__ | |__| | __\ \__ PLVS VLTRA . . . . ^
/__| |_ \ / \ / _| |__\
| | | | | _ _ | | | | | THE RAMMAN
| |_| | | \\ // | | |_| | Richard Greene
\___/ \ " " / \___/ E-MAIL:R.GREENE@IEEE.ORG
| | HUMAN:(609) 859-8833
| oo | FAX: (609) 859-3671
\__/ VINCENTOWN, NJ 08088
Article: 3231In article <DqoF63.48q@news.dlr.de>, venus@sunnyboy.ws.ba.dlr.de says... > > >Hello, > >Does anybody know the address of the packaging firm RAD-PACK ? US 4031 Sorrento Valley Boulevard San Diego California Phone : (619) 452-4167 Fax: (619) 452-5499 UK Mainstay Phone: (635) 210786 Standard FPGA's they pack are Actel 1020/1280 and the Xilinx 3090. Radpacks technology will only increase the total dose threshold, they will not prevent SEL/SEU. It will be interesting to see what happens to a SRAM based FPGA when it gets a SEU :-) We use Actel 1020/1280 for our micro/minisatellites. For circular LEO 800KM type of orbits we get a total dose of about 1Rad/Day. Thus even "low total dose" components (<5K) will still survive for a long time. Regards, Hans Tiggeler Surrey Satellite Technology.Article: 3232
We are designing a simple lowcost prot-typing board that takes 4 84 pin Xilinx FPGAs and provides a wirewrap area and some leds and switches. We want to daisychain these in such a way that the standard Xilinix software will download into them. we want to use a simple parallel cable, no expensive Xchecker. I recall that the pinouts were in the very old Xilinx manuals, and maybe the circuit of their old prototype boards. Can anyone help supply me with the pinouts? I suppose the daisychain programming uses slave serial mode, as listed in the current manuals. I do realise that using the parallel cable is not as powerful as an Xcehcker but there is a hint in the modern docs that it is possible. Anyone else wish to contribute their hardware scematics if they have done anything similiar? I'll post all data on my web... within a few months Thanks in anticiaption -- Regards from Ian McCrum, Lecturer in Digital Systems and ECAD Email: <IJ.MCCRUM@ulst.ac.uk> WEB: http://www.eej.ulst.ac.uk/index.html POST-MAIL: School of Electrical & Mechanical Engineering University of Ulster at Jordanstown, Northern Ireland, BT37 0QB Tel: +44 1232 366364 or at home +44 1247 882889 Fax: +44 1232 362804 or preferably +44 1247 882894 ------------------------------ ends ------------------------------------ 8-}Article: 3233
guccione@xilinx.com wrote: > I favor single memory FCCMs that exploit pipelining and customization > of basic operations. I believe this will give a more balanced system > and make program easier. I vote for multi memory FCCMs consisting of chunks of FPGA stuff separated by moderate sized (256x32) FIFO or Dual-port RAM (all on one chip if possible). This would be fairly easy to program for data flow type operations, load balancing, data sorting, data merging, short list processing, matrix operations, etc. Something with larger RAMs would be useful for linked-list processing, data-base operations, and pattern matching, but would probably not be a significant improvement over CPUs. The Flex 1000 architecture (Altera? Actel? they all look alike to me) seems to a step in this direction. The X4000E is too, but would be better with larger memories.Article: 3234
Hallo, I am looking for FPGA (5000 .. 20000 gates) for a apace application. I know the Actel/Loral 1280. Are there any other FPGA available for such kind of application. The needed total dose is about 10 to 20 Krad(Si). Are there any radiation test data available? What oubout SEU and latch up? Best regards, Holger Venus DLR Institute for Space Sensor Technology Rudower Chaussee 5 12489 Berlin Germany e-mail: venus@sunnyboy.ws.ba.dlr.deArticle: 3235
Hello, Does anybody know the address of the packaging firm RAD-PACK ? This firm packs dies in their radiation tolerant package. I am looking for radiation tolerant FPGA (10..20 Krad (SI)) beside the Actel/Loral FPGA . Thanks, Holger Venus e-mail: venus@sunnyboy.ws.ba.dlr.de DLR Institute for Space Sensor Technology Rudower Chaussee 5 12489 Berlin GermanyArticle: 3236
The S-module is a C-module with a programmable flip-flop. If you exceed the number of available C-Mods and have extra S-mods, the place and route software will automatically convert the S-mods to C-mods. JEFF WETCH wetch@actel.com Actel Field Application EngineerArticle: 3237
In article <kurt-2904961155480001@192.55.89.50>, Volker Kurt Kamp <kurt@emphasys.de> wrote: >we think about using the "Synario Universal FPGA Design System" from DATA/IO. Let me ask you this: do you want to use AMD Mach devices?Article: 3238
Discover the next-generation of digital design tools and test
technology!
Corelis Inc., a fast growing world leader in digital
design and test technology products, has the following
immediate openings for motivated and innovative
engineers at their Cerritos, California facility.
Join a company where your contribution will make a
difference to our high energy, dynamic team.
We offer a challenging professional environment,
unlimited growth opportunity, and attractive salaries.
Opportunities exist for:
1. Technical Marketing Engineer
You will perform strategic marketing activities
for Corelis' boundary-scan and emulation products
for the digital design and test market.
Responsibilities include new products definition
and proposals, product promotion, and business
partners development and maintenance.
You will also provide technical assistance to the
sales force, perfor market research, and train
field staff and sales personnel on new products.
Requires a BS/MSEE with 3-5 years of experience
in hardware and software development of embedded
applications and technical marketing. Concise
verbal and written communication skills are essential.
2. Sr. Application Engineer:
You will provide expert-level telephone/Internet-based
software/hardware design support for North American
Customers and field sales organization for boundary-scan
(JTAG) test and programming tools, and debug and
integration tools for designs that include leading RISC
processors. You will also author data sheets, technical
articles, application notes, and technical presentations.
Requires a BS/MSEE and 3-5 years' of hands-on experience
in design of embedded real-time systems, RISC microprocessors,
C, Unix, DOS, MS Windows.
Candidates must exhibit excellent verbal communications and
writing skills.
********************************************************************
Menachem Blasberg
Corelis Inc. Email: menachem@corelis.com
12607 Hidden Creek Way Tel: (310) 926-6727
Cerritos, CA 90703 Fax: (310) 404-6196
********************************************************************
Article: 3239If Mr. Holmes David is still reading this newsgroup, can you please reply because it seems your email address has changed. Thanks, ! -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 3240
In article <4m84i2$jc6@neutra.mv.us.adobe.com>, pngai@adobe.com (Phil Ngai) wrote: Hi, > Let me ask you this: do you want to use AMD Mach devices? No, not today. We want to use it for PCB designs, as we do it today with the old version of SCS for SUN. And we want to use it for Xilinx designs. In the Xilinx solution we need to have control over mapping and placing of clb's. Kurt. ------------------------------------------------------------------- **** * =========== = = = = Volker Kurt Kamp ** * = (kurt@bintec.de) **** * *** = == === BinTec Commmunications GmbH ** * * * * = ==== = Alt-Moabit 94 D-10559 Berlin ** * * * * = = = Voice: (+49)30 / 399 88-3 **** * * * = == === FAX: (+49)30 / 392 28 36 ------------------------------------------------------------------- C O M M U N I C A T I O N S -------------------------------------------------------------------Article: 3241
Hello, I have a place&routing problem in the Xilinx XC4010PG191. Our design flow is verilog HDL through synopsys optimization to xnf format. Then use Xilinx xmake to place&rout and makeprom to get the prom file. We use the parallel configuration mode with EPROM to download my design into Xilinx FPGA. There are some configuration pins, like "address and data pins to EPROM" can be used as I/O pins after configuration. But the vendor told us: don't set these pins as input pins of your design or the the input signal will disturb the configuration addresses in the download step and make the download fail. Then we try to use the contraint file to assign the I/O pins of our design to fixed pins of Xilinx FPGA in the ppr stage. But ppr can't success for these contraint (our design has 136 I/O). So we use the "notplace" instruction in the cst file to avoid place the input of our design in these configuration pins. Then ppr can success, but always has one input pin not under control. Can these constraints been assigned in sysnopsys optimization stage ? Or how can I write the constraint file to make the "notplace" right? Or anyway else to solve this problem? Thanx very much.... ps: the format of the constraint file is notplace instance input1* input2* : pins_name_in_4010pga; -- email-address: ccchen@ee.nctu.edu.tw ccchen 5/3 1996Article: 3242
In article <4m51ov$6pk@mailman.xilinx>, Steve Guccione <guccione@xilinx.com> wrote: >In article <mbuttsDqMt7C.JpD@netcom.com>, Mike Butts <mbutts@netcom.com> wrote: >>Precisely. The most fundamental, and potentially the most important >>difference between CPUs and FCCMs is the processor-memory model. >> >>The sequential Von Neumann CPU model has a single unified memory >>space with only a single sequence of memory accesses permitted. >>Implementations of CPUs, memory systems and compilers infer some >>parallelism beyond that, but the model that programmers >>must code to is still limited to that sequential, one reference at >>a time model. >> >>FCCMs need not share that limitation. >> >> --Mike > > >I have to disagree a bit. I think that FCCMs with multiple memories >are inherently more difficult to program. As are multiprocessors. >The problem is that the data is never where you want it, when you want >it. And moving it can get expensive. Also, while multiple memories >increase the bandwidth to the processor, accessing the data in these >memories from the host computer becomes the bottleneck. You're both right, and you're both wrong (how's that for equivocating? :). The biggest problem faced by most (existing) CCMs is achieving and exploiting reasonable bandwidth through the reconfigurable logic to keep the massive amounts of parallelism fed. What is on the other side of that bandwidth is of second order importance. From the point of view of the logic, data is data, regardless of where it's coming from. To the extent that the algorithms reuse data (or require random access) some of the bandwidth must be devoted to memory. But long pipelines spanning multiple processing elements require a great deal of bandwidth between the elements as well. And of course there is the issue of I/O with the outside world. All of these things must be balanced. Are multiple memories more difficult to program? I don't think so. On Splash 2 we often found it was necessary to multiplex several streams in and out of the single memory (per PE). Many signal and image processing applications naturally fit a FIFO type structure: reading from one stream while writing another. Having simultaneous access to two memories (or two ports to the same memory) would have significantly simplified the programming. As for host access to the memory, that's really the external I/O issue. It, too, must be balanced with the memory and interprocessor bandwidth. -jeff -- ----- Jeffrey M. Arnold jma@radix.netArticle: 3243
We are announcing two new products. Please visit our site http://www.vhdl.com for more details. New: Sledgehammer-4 source code editor for C, C++, ABEL, VHDL, Verilog New: Dragster VHDL model generation tool -- Sincerely, ------------------------------------------------------------- William Billowitch e-mail: wdb@vhdl.com The VHDL Technology Group Web: http://www.vhdl.com 100 Brodhead Road, Suite 140 Phone : 610-882-3130 Bethlehem, PA 18017 Fax : 610-882-3133Article: 3244
Hi
I posted this to sci.electronics, and was told that this group might be a
better place.
I work for a small electronics group. In the past we have produced some
large pieces of equipment with _lots_ of TTL logic. Much of this can now
be incorporated into a single FPGA.
We are interested in aquiring a basic programable logic capability,
and I have been charged with investigating the market and coming up
with some suggestions for about 2000 U.K. Pounds (about U.S.$3000) total cost.
Our development system will be P.C. based
However I have only a theoretical knowledge of the steps required to turn
a paper conceptual design based on 74 series TTL parts to a working single
device, eg GAL22V10, let alone the issues that need to be addressed when
attempting to implement larger designs.
Ideally we would be able to start with simple parts, such as generic 16V8,
and as we gain confidence move up to the much larger parts, eg Xylinx, without
having to learn a new set of design tools.
So my questions are :
1. What seperate bits do I need ? I have identified the following:
Schematic Capture Editor
Logic Compiler
Functional Simulator
Device Programmer
Is there anything else ?
2. Who supplies all this ? Is it possible to use third party software
and equipment, to avoid being locked in to a single manufacturer ?
3. What experience do people have of the major silicon vendors,
eg Altera, Lattice, Xylinx, and others ?
4. We expect to be required to be able to service equipment using this
technology in 10 years time. Which suppliers are most likely to be in
a position to supply spares over this timescale ?
I would really like to hear from users of this technology, because otherwise
I have to rely totally on what the salespeople have to say. In particular
I would like to hear from users of the Orcad PLD tool, or the MINC system.
Please post here or email me at Steve@s-dewey.demon.co.uk
--
Steve Dewey
Too boring to have a witty or interesting sig file.
Article: 3245husby@fnal.gov (Don Husby) wrote: > It's not likely that an SRAM or EEPROM based device will be as rad-hard as a > fuse-based device. .. but you can repair flipped configuration bits by reloading from a saver memory or even via the radio link. Are there known additional failure mechanisms inherent in SRAM/EEPROM FPGAs? GerhardArticle: 3246
> > If Mr. Holmes David is still reading this newsgroup, can you please reply > because it seems your email address has changed. > > Thanks, ! > > -- > > > ============================================================================== > > ************************************ > * Hofmans Kim * > * * > * tw38966@vub.ac.be * > * khofmans@info.vub.ac.be * > * * > * Brouwerijstraat 62 * > * 1630 Linkebeek * > * Belgium * > * * > * 32-2-3771012 * > * * > ************************************ > David Holmes, David@highgatedesiatedesign.comArticle: 3247
In article <4manj3$cqr@news.csie.nctu.edu.tw>, ccchen@athletes.EE.NCTU.edu.tw (Chih-Ching Chen) wrote: > We use the parallel configuration mode with EPROM to download my design into > Xilinx FPGA. There are some configuration pins, like "address and data pins > to EPROM" can be used as I/O pins after configuration. > > But the vendor told us: don't set these pins as input pins of your design > or the the input signal will disturb the configuration addresses in the > download step and make the download fail. > There is a hardware and a software aspect to this problem. Let me explain the hardware aspect and its solution: During configuration in Master Parallel mode, the FPGA must output 18 address lines and must receive 8 data inputs. Any other driver must be kept off these lines during the configuration process. So, if for one reason or the other, you must share any of the address or data pins with a signal that drives the FPGA during normal operation, you can use HDC or LDC to 3-state the offending driver during configuration. That's all there is to it. Peter Alfke, Xilinx ApplicationsArticle: 3248
Hi everybody, I have a short question: Does anybody know some good books regardig silage? I use a power estimation tool which is a free program available at Berkeley. It uses silage at the beginning of the optimization. Thanks a lot in advance. Best regards Markus Rettinger --------------------------------------------------------------------- - Lehrstuhl fuer Integrierte Schaltungen | - - Techn. Universitaet Muenchen | - - Dipl.-Ing Markus Rettinger | - - Arcisstr. 21 | - - 80290 Muenchen | - ------------------------------------------------| - - Tel: +49 89 289 225 15 | neue Telefonnr. - - Fax: +49 89 289 283 23 | seit 01.05.1996 - ------------------------------------------------| - - E-Mail: | - - M_Rettinger@lis.e-technik.tu-muenchen.de | - ---------------------------------------------------------------------Article: 3249
Markus Rettinger (markusr@tumlis.lis.e-technik.tu-muenchen.de) wrote:
|Does anybody know some good books regardig silage?
See agricultural textbook on farming cows; silage is fermented cow sh*t.
Sorry, couldn't resist. What idiot calls a product "silage" anyway?
--
===============================================================================
The above are my own views, not the views of HP
Tom Gardner Hewlett Packard Laboratories, Filton Rd,
tgg@hplb.hpl.hp.com Stoke Gifford, Bristol, Avon, BS12 6QZ, ENGLAND.
Fax: +44 117 9228920 Tel: +44 117 9799910 ext. 28192
===============================================================================
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z