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We are announcing two new products. Please visit our site http://www.vhdl.com for more details. New: Sledgehammer-4 source code editor for C, C++, ABEL, VHDL, Verilog New: Dragster VHDL model generation tool -- Sincerely, ------------------------------------------------------------- William Billowitch e-mail: wdb@vhdl.com The VHDL Technology Group Web: http://www.vhdl.com 100 Brodhead Road, Suite 140 Phone : 610-882-3130 Bethlehem, PA 18017 Fax : 610-882-3133Article: 3251
ian@PROBLEM_WITH_INEWS_DOMAIN_FILE (Ian McCrum STAFF) wrote: >We are designing a simple lowcost prot-typing board that takes 4 84 pin >Xilinx FPGAs and provides a wirewrap area and some leds and switches. We >want to daisychain these in such a way that the standard Xilinix software >will download into them. we want to use a simple parallel cable, no >expensive Xchecker. I recall that the pinouts were in the very old Xilinx >manuals, and maybe the circuit of their old prototype boards. > >Can anyone help supply me with the pinouts? I suppose the daisychain >programming uses slave serial mode, as listed in the current manuals. >I do realise that using the parallel cable is not as powerful as an Xcehcker >but there is a hint in the modern docs that it is possible. > >Anyone else wish to contribute their hardware scematics if they have done >anything similiar? > >I'll post all data on my web... within a few months Thanks in anticiaption > >-- >Regards from Ian McCrum, Lecturer in Digital Systems and ECAD >Email: <IJ.MCCRUM@ulst.ac.uk> WEB: http://www.eej.ulst.ac.uk/index.html >POST-MAIL: School of Electrical & Mechanical Engineering >University of Ulster at Jordanstown, Northern Ireland, BT37 0QB >Tel: +44 1232 366364 or at home +44 1247 882889 >Fax: +44 1232 362804 or preferably +44 1247 882894 >------------------------------ ends ------------------------------------ 8-} Hi . I'm afraid i cant give you any help at the moment but Im very interested in your project as I am about to do the same on my own in the autumn. I'm lecturing in digital systems and for the moment I'm doing the same kind of breadboard for an AMD-445 IC. My AMD breadboard is designed from the AMD-manuals and there has not been any problems yet( it hasn't been tested :-)). I'm having done a PCB'layout at the moment if you are interested . Maybe we can exchange design, PCB-layout etc at a later time .. Good luck Best regards KajArticle: 3252
ian@PROBLEM_WITH_INEWS_DOMAIN_FILE (Ian McCrum STAFF) wrote: >We are designing a simple lowcost prot-typing board that takes 4 84 pin >Xilinx FPGAs and provides a wirewrap area and some leds and switches. We >want to daisychain these in such a way that the standard Xilinix software >will download into them. we want to use a simple parallel cable, no >expensive Xchecker. I recall that the pinouts were in the very old Xilinx >manuals, and maybe the circuit of their old prototype boards. > >Can anyone help supply me with the pinouts? I suppose the daisychain >programming uses slave serial mode, as listed in the current manuals. >I do realise that using the parallel cable is not as powerful as an Xcehcker >but there is a hint in the modern docs that it is possible. > >Anyone else wish to contribute their hardware scematics if they have done >anything similiar? > >I'll post all data on my web... within a few months Thanks in anticiaption > >-- >Regards from Ian McCrum, Lecturer in Digital Systems and ECAD >Email: <IJ.MCCRUM@ulst.ac.uk> WEB: http://www.eej.ulst.ac.uk/index.html >POST-MAIL: School of Electrical & Mechanical Engineering >University of Ulster at Jordanstown, Northern Ireland, BT37 0QB >Tel: +44 1232 366364 or at home +44 1247 882889 >Fax: +44 1232 362804 or preferably +44 1247 882894 >------------------------------ ends ------------------------------------ 8-} Hi . I'm afraid i cant give you any help at the moment but Im very interested in your project as I am about to do the same on my own in the autumn. I'm lecturing in digital systems and for the moment I'm doing the same kind of breadboard for an AMD-445 IC. My AMD breadboard is designed from the AMD-manuals and there has not been any problems yet( it hasn't been tested :-)). I'm having done a PCB'layout at the moment if you are interested . Maybe we can exchange design, PCB-layout etc at a later time .. Good luck Best regards KajArticle: 3253
ian@PROBLEM_WITH_INEWS_DOMAIN_FILE (Ian McCrum STAFF) wrote: >We are designing a simple lowcost prot-typing board that takes 4 84 pin >Xilinx FPGAs and provides a wirewrap area and some leds and switches. We >want to daisychain these in such a way that the standard Xilinix software >will download into them. we want to use a simple parallel cable, no >expensive Xchecker. I recall that the pinouts were in the very old Xilinx >manuals, and maybe the circuit of their old prototype boards. > >Can anyone help supply me with the pinouts? I suppose the daisychain >programming uses slave serial mode, as listed in the current manuals. >I do realise that using the parallel cable is not as powerful as an Xcehcker >but there is a hint in the modern docs that it is possible. > >Anyone else wish to contribute their hardware scematics if they have done >anything similiar? > >I'll post all data on my web... within a few months Thanks in anticiaption > >-- >Regards from Ian McCrum, Lecturer in Digital Systems and ECAD >Email: <IJ.MCCRUM@ulst.ac.uk> WEB: http://www.eej.ulst.ac.uk/index.html >POST-MAIL: School of Electrical & Mechanical Engineering >University of Ulster at Jordanstown, Northern Ireland, BT37 0QB >Tel: +44 1232 366364 or at home +44 1247 882889 >Fax: +44 1232 362804 or preferably +44 1247 882894 >------------------------------ ends ------------------------------------ 8-} Hi . I'm afraid i cant give you any help at the moment but Im very interested in your project as I am about to do the same on my own in the autumn. I'm lecturing in digital systems and for the moment I'm doing the same kind of breadboard for an AMD-445 IC. My AMD breadboard is designed from the AMD-manuals and there has not been any problems yet( it hasn't been tested :-)). I'm having done a PCB'layout at the moment if you are interested . Maybe we can exchange design, PCB-layout etc at a later time .. Good luck Best regards KajArticle: 3254
ian@PROBLEM_WITH_INEWS_DOMAIN_FILE (Ian McCrum STAFF) wrote: >We are designing a simple lowcost prot-typing board that takes 4 84 pin >Xilinx FPGAs and provides a wirewrap area and some leds and switches. We >want to daisychain these in such a way that the standard Xilinix software >will download into them. we want to use a simple parallel cable, no >expensive Xchecker. I recall that the pinouts were in the very old Xilinx >manuals, and maybe the circuit of their old prototype boards. > >Can anyone help supply me with the pinouts? I suppose the daisychain >programming uses slave serial mode, as listed in the current manuals. >I do realise that using the parallel cable is not as powerful as an Xcehcker >but there is a hint in the modern docs that it is possible. > >Anyone else wish to contribute their hardware scematics if they have done >anything similiar? > >I'll post all data on my web... within a few months Thanks in anticiaption > >-- >Regards from Ian McCrum, Lecturer in Digital Systems and ECAD >Email: <IJ.MCCRUM@ulst.ac.uk> WEB: http://www.eej.ulst.ac.uk/index.html >POST-MAIL: School of Electrical & Mechanical Engineering >University of Ulster at Jordanstown, Northern Ireland, BT37 0QB >Tel: +44 1232 366364 or at home +44 1247 882889 >Fax: +44 1232 362804 or preferably +44 1247 882894 >------------------------------ ends ------------------------------------ 8-} Hi . I'm afraid i cant give you any help at the moment but Im very interested in your project as I am about to do the same on my own in the autumn. I'm lecturing in digital systems and for the moment I'm doing the same kind of breadboard for an AMD-445 IC. My AMD breadboard is designed from the AMD-manuals and there has not been any problems yet( it hasn't been tested :-)). I'm having done a PCB'layout at the moment if you are interested . Maybe we can exchange design, PCB-layout etc at a later time .. Good luck Best regards KajArticle: 3255
>We are designing a simple lowcost prot-typing board that takes 4 84 pin >Xilinx FPGAs and provides a wirewrap area and some leds and switches. We >want to daisychain these in such a way that the standard Xilinix software >will download into them. we want to use a simple parallel cable, no >expensive Xchecker. I recall that the pinouts were in the very old Xilinx >manuals, and maybe the circuit of their old prototype boards. The easiest way will be to load the first one in parallel, and load the other three from the first one's DOUT & CCLK signals. On the PC's parallel port, tie the BUSY line into a permanently ready state (on your board), and then when you output a byte to LPT1 it should get strobed into the first FPGA. You need to make sure you have a certain min gap between consecutive bytes, but that should be OK because of the time it takes to run through the LPT BIOS code etc. Then just use MAKEPROM to make a hex file, and you need a little program which converts this into a binary image which you can "COPY /b filename lpt1" to the board. This program needs to allocate a RAM block, fill it with FFs, then load the hex image into it according to the address in each hex record. These programs are sometimes used to drive EPROM programmers. A pity MAKEPROM cannot (I think) generate binary images directly. I cannot see why this should not work. In fact I remember seeing an article somewhere, with example code. Peter.Article: 3256
Peter Alfke <peter@xilinx.com> wrote:
>Here are the calendar 1995 revenue numbers for the biggest players in the
>Programmable Logic Market:
>
>Xilinx $ 520 M
>Altera $ 402 M
>AMD $ 285 M
>Lattice $ 185 M
>Actel $ 106 M
>Cypress $ 76 M.
Peter, do you know QuickLogic's sales numbers for this time period? Because
they get all their silicon from Cypress, I'd be tempted to lump the two
companies together for comparing market sizes. (A combined Cypress-QuickLogic
might even be bigger than Actel or possibly even Lattice -- don't know for
sure -- just guessing.)
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3713 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3257
You guys should think about using the serial port instead:
Use a MAX232 chip for converting rs-232 to ttl levels. This is a convenient
device because it has its own +/- 9V power supply (requiring four external
capacitors), and can work off of 5V only. These chips cost $2 plus $2 more
for the capacitors. It may be worth while to use the MAX233 instead- it has
built in capacitors, but costs about $5.
To make the PC's serial port software happy, you need to connect CTS to RTS
and DTR to DCD and DSR. You should receive DTR and send-data with the
MAX232, and you should transmit receive-data with the MAX232. Also some
serial port cards have a jumper so that you can get 5V on the
otherwise-useless ring-detect line (or you can cut and jumper your serial
port board to do this- 5V on the ring detect line when not harm modems).
You want to be able to reprogram the xilinx, so when DTR drops the PROG/DONE
line should be pulled down. The MAX-232 chip inverts the signals so you can
do this with an NPN transistor (like 2n3904) and a resistor. Connect the
collector to the PROG/DONE line. Connect the emitter to ground and connect
the base though a 1K resistor to DTR from the max232.
Send data will have the configuration data, so it should be connected to DIN
on the xilinx. To generate CCLK, use a 74LS221 dual one-shot (costs about
$0.60). Use one of the one-shots (triggered from a low going edge) to delay
to the middle of an asynchronous data frame (about 500uS for 9600 baud).
Feed this to the second one shot, which will make the actual low-going cclk
pulse (about 1uS). Thus the start bit of each serial frame will trigger the
one-shots so that a clock pulse appears when the data bits are stable on the
DIN line. For each bit to be sent to the xilinx you have to transmit a 0xFF
(for a 1) or a 0x00 (for a 0) (remember data on rs-232 is inverted, but the
max-232 fixes it).
You probably also want to connect the receive data line to one of the xilinx
pins- this way your xilinx 'program' can communicate bidirectionally with
the PC after configuration (if you implement a serial port in the xilinx,
which is easy to do). Also it's trivial to cascade several xilinx's
together.
I've made tiny little boards containing this circuit with a XC2064 (yes a
2064! $1 each surplus for these) and a DB9 serial port connector.
I use these to convert credit card machines (which also are used for
Medicaid verification and a bunch of other things) so that I can remotely
type on the keypad and read the vacuum flourescent screen (this hardware
solution is much much eaiser than hacking the protocol on the phone line
(which tends to change often anyway)). The xilinx is better suited for this
because a microcontroller may not be able to keep up with keypad's scanning
lines. Anyway, I sell them and a small program to automate methadone
treatment companys Medicaid verification process for $2500 each. Which is
well worth the money because it usually eliminates an employee- each patient
has to be verified every day, 100 patients can take 5 hours to do. Small
companies can not get an automated program from the state (or it costs too
much).
The same board can be easily reconfigured for other keypad/displays. I've
also used it to make a laser camera (an expensive device which prints MRI
films) remote controllable (for an image archiving system). You can get a
factory upgrade for the laser camera so that it can be remote controllable
(using their proprietary interface), but for this particular brand it costs
$25,000 (about the same as the entire archiving system).
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 3258
Ian McCrum STAFF wrote:
>
> We are designing a simple lowcost prot-typing board that takes 4 84 pin
> Xilinx FPGAs and provides a wirewrap area and some leds and switches. We
> want to daisychain these in such a way that the standard Xilinix software
> will download into them. we want to use a simple parallel cable, no
> expensive Xchecker. I recall that the pinouts were in the very old Xilinx
> manuals, and maybe the circuit of their old prototype boards.
>
> Can anyone help supply me with the pinouts? I suppose the daisychain
> programming uses slave serial mode, as listed in the current manuals.
> I do realise that using the parallel cable is not as powerful as an Xcehcker
> but there is a hint in the modern docs that it is possible.
>
> Anyone else wish to contribute their hardware scematics if they have done
> anything similiar?
>
> I'll post all data on my web... within a few months Thanks in anticiaption
Hello Ian,
I hacked the following program together years ago when I first started
playing with Xilinx parts and "C". It is compatible with the Xilinx
demo boards and accepts an intel hex bitfile. I just hacked in a crude
wiring diagram which I believe is correct. I didn't document it when I
wrote it (bad dog!) and had to reverse engineer it just now. The
program uses four PC parallel port pins to drive three signal lines
(DIn, CClk and *Prog/Done) to a Xilinx part in slave serial mode. You
can hack the -r switch code to generate a reset from another port pin
instead of prompting to push the demo board reset button. A single
Schottky diode (any kind will do) is required to isolate the parallel
port pin that drives *Prog when it goes high so that the state of Done
can be read by the PC on the SelectIn pin.
I have schematics for the demo board, but not in electronic form. They
may be copyrighted by Xilinx. Peter Alfke of Xilinx often drops in on
this newsgroup and may be able to help. If you have no luck, get back
to me and I'll see what I can do.
Have fun,
Scott
Program follows (originally compiled with QuickC):
/*
A simple program to download intel hex format Xilinx bitmap files to
Xilinx devices in slave serial mode from the PC parallel port (LPT1).
Scott Kroeger Copyright 1989
Wiring:
LPT Port Pin Port Name Xilinx Pin
2 D0----------DIn
3 D1----------CClk
6 D4----|<----*Prog/Done
13 SelectIn----*Prog/Done
Note: -|<- = Schottky diode.
*/
#include <stdio.h>
#include <ctype.h>
#include <fcntl.h>
#include <conio.h>
main(argc,argv)
char *argv[];
int argc;
{
FILE *in;
int doReset;
printf("Xilinx downloader version 1.0\n" );
if (argc < 2) {
printf("correct usage is: download infile\n");
exit(1);
}
in = fopen (argv[argc-1],"rt");
if(in == NULL){
printf("can't open input file: %s\n",argv[argc-1]);
exit (1);
}
doReset=1;
if( strstr(argv[1],"-r") ) doReset = 0;
download(in,doReset);
fclose(in);
return (0);
}
download(in,doReset)
FILE *in;
int doReset;
{
register int c,byteCount;
outp(0x378,0x03); /* assert prog */
if(doReset){
printf("Reset the device and press a key when ready.\n");
while (kbhit()==0);
}
outp(0x378,0x13); /* release prog */
if (inp(0x379) & 0x10) {
printf("Done did not stay low, loading stopped.\n");
}
getc(in); /* discard first record */
while ((c=getc(in)) != EOF){
if(c == ':') {
if(byteCount = GetByte(in)){
downloadRecord(byteCount,in);
}
}
}
if (inp(0x379) & 0x10)
printf("Load Done.\n");
else
printf("Done did not go high, bad load.\n");
}
downloadRecord(byteCount,in)
FILE *in;
int byteCount;
{
int a;
GetByte(in); /* discard load address and record type */
GetByte(in);
GetByte(in);
for(;byteCount>0;byteCount--){
SendByte(GetByte(in));
}
}
GetByte(in)
FILE *in;
{
int b,temp;
temp = getc(in);
b=toupper(temp)-'0';
if (b > 9) b-=7;
temp=b<<4;
b = getc(in);
b=toupper(b)-'0';
if (b > 9) b-=7;
b=b+temp;
return(b);
}
SendByte(byte)
int byte;
{
int bit;
for (bit=0;bit<=7;bit++) {
if(byte & 1) {
outp(0x378,0x11); /* Data = 1, CClk = 0 */
outp(0x378,0x11); /* waste time to avoid overruns */
outp(0x378,0x13); /* Data = 1, CClk = 1 */
outp(0x378,0x13);
}
else {
outp(0x378,0x10); /* Data = 0, CClk = 0 */
outp(0x378,0x10);
outp(0x378,0x12); /* Data = 0, CClk = 1 */
outp(0x378,0x12);
}
byte = byte >> 1;
}
}
Article: 3259Not sure if this is the appropriate place, but I have an Actel development system that I don't expect to be using soon and would like to sell it. Includes software and device programmer. Both for the IBM PC platform. As I seldom visit this group please email any interest. dwp@deltanet.com thanks, dennisArticle: 3260
ft63@dial.pipex.com (Peter) wrote:
>>We are designing a simple lowcost prot-typing board that takes 4 84 pin
>>Xilinx FPGAs and provides a wirewrap area and some leds and switches. We
>>want to daisychain these in such a way that the standard Xilinix software
>>will download into them. we want to use a simple parallel cable, no
>>expensive Xchecker. I recall that the pinouts were in the very old Xilinx
>>manuals, and maybe the circuit of their old prototype boards.
>The easiest way will be to load the first one in parallel, and load
>the other three from the first one's DOUT & CCLK signals.
>On the PC's parallel port, tie the BUSY line into a permanently ready
>state (on your board), and then when you output a byte to LPT1 it
>should get strobed into the first FPGA. You need to make sure you have
>a certain min gap between consecutive bytes, but that should be OK
>because of the time it takes to run through the LPT BIOS code etc.
>Then just use MAKEPROM to make a hex file, and you need a little
>program which converts this into a binary image which you can "COPY /b
>filename lpt1" to the board. This program needs to allocate a RAM
>block, fill it with FFs, then load the hex image into it according to
>the address in each hex record. These programs are sometimes used to
>drive EPROM programmers. A pity MAKEPROM cannot (I think) generate
>binary images directly.
>I cannot see why this should not work. In fact I remember seeing an
>article somewhere, with example code.
>Peter.
If you are using XC4000 parts (don't know about later ones), you can
do a neat remote configuration using the IEEE 1149 TAP port. This can
be connected to the PC's parallel port (just use a couple of data
lines), and generate a TAP protocol to configure it.
I have built a number of devices using this method, commonly
comprising an embedded CPU, memory and FPGA as a specialised
peripheral. With the software (and the real configuration) in a flash
ROM, this method allows the PC to "take over" the target hardware, and
turn it into an in-system flash ROM programmer. This is then used to
install the working software. The method will work with a factory-new
ROM in the system (ie no boot code is needed). The boards are arranged
so that on power-up, if the programming cable is connected, the CPU is
locked off the bus, and the FPGA awaits remote configuration. Else,
the FPGA self-configures (in master parallel mode, from the ROM), then
takes Reset off the CPU to run the system.
One tip: parallel port lines often have awful bounce on them.
Generate the TAP clock on-board, using a R-S latch controlled by TWO
parallel data lines, one to set and one to reset. Now the bounce is
eliminated, similar to debouncing a Form-C switch contact. This avoids
double-clocking the TAP logic, which is fatal.
-- Dave Brooks
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
Article: 3261Does anybody have information on the plpl2.3 (not plpl2.2) device definition file format (the files named "p<device>")? I was able to glean most of the format from the 2.2 source files, but it looks like the support for OR arrays was added in v2.3 (the lines in the files that begin with ">"), and I don't know if my interpretation of the format for these is correct. I'm trying to hack up a definition file for a GAL6002. Ithink I can do it, basing it on the p22v10, pls168 (for the or array) and the p29m16 (for the dual-feedback macrocells) files, but I'd like to verify a few points in the syntax. Maybe someone has already done the GAL6002? --Tim Stilson stilti@ccrma.stanford.eduArticle: 3262
My two cents worth:
"FPGA - The field-programmable gate array (FPGA)
was developed as a programmable alternative to
the masked gate array, another popular semicustom
ASIC device. An FPGA uses a channeled programmable
interconnect matrix to join blocks of configurable
logic. Unlike the CPLD, an FPGA's electrical
characteristics are not fixed, so qualities
such as line length and number of fuses are not
known until routing. Although this makes for some
unpredictability of timing, the trade-off is the
FPGA's increased logic complexity and flexibility."
So....segmenting the FPGA portion of the programmable
logic market by this definition yields:
"Company 95 Sales 94 Sales 95 MS 94 MS
---------------------------------------------------------
Xilinx $504.5 $315.1 70.4% 67.3%
Actel $108.4 $76.0 15.1% 16.2%
AT&T Micro $77.8 $44.9 10.9% 9.6%
QuickLogic $17.1 $7.5 2.4% 1.6%
Table 6-22: FPGA vendors' sales (in millions) and market shares,
1995, and comparision to 1994."
- definition and data from: "PLD Market Report 1995",
by Rhondalee Rohleder and
published by Pace Technologies
Altera, AMD, Lattice, and Cypress account for most of their revenue
from the sales of simple and complex PLDs. Lucent Technologies
(formerly AT&T Microelectronics) accounts for all of its revenue from
the sales of SRAM-based FPGAs (ATT3000 and ORCA-Series).
======================================================
Frederick Koons Strategic Marketing Manager, FPGAs
Lucent Technologies E-Mail: fjk@aloft.att.com
======================================================
> Peter Alfke wrote:
>
> In article <4lqme8$2iq@news.tiac.net>, Eric Ryherd <eric@vautomation.com> wrote:
>
> > Does anyone have a reference on the annual number of FPGAs shipped
> > (or even revenue) by the top 3 FPGA companies.
> >
> > I assume the order is
> > 1) Xilinx,
> > 2) Altera,
> > 3) Actel.
> >
> Here are the calendar 1995 revenue numbers for the biggest players in the
> Programmable Logic Market:
>
> Xilinx $ 520 M
> Altera $ 402 M
> AMD $ 285 M
> Lattice $ 185 M
> Actel $ 106 M
> Cypress $ 76 M.
>
> Xilinx sales are mainly SRAM-based FPGAs, plus some CPLDs and some
> Antifuse-based FPGAs.
>
> Altera does not call any of its devices "FPGA", and most of their sales
> are CPLDs in EPROM and EEPROM technology.
> AMD is 100% CPLDs and PALs.
> Lattice is CPLDs and GALs.
> Actel is 100% antifuse-based FPGAs.
> Cypress is mostly CPLDs.
>
> I hope nobody is confused or offended by this explanation of the alphabet-soup.
>
> FPGA stands for Field-Programmable Gate Array,
> CPLD stands for Complex Programmable Logic Device
> PAL stands for Programmable Array Logic, trademarked by AMD
> GAL stands for Generic Array logic, trademarked by Lattice.
> EPROM stands for Erasable Programmable Read-Only Memory, and
> EEPROM stands for Electrically Erasable Programmable Read-Only Memory. Wow!
>
> Peter Alfke, Xilinx Applications
Article: 3263[I've had many problems posting this message. Netcom corrupted several attempts, and two repostings from Microsoft's Usenet site never made it out the door. Apologies if you've already read this or are tired of the reposts, but I really wanted to get the message out in its entirety.] One of the "way out speculation" questions asked at FCCM 96 (IEEE Symposium on FPGAs for Custom Computing Machines) was "when, if ever, will an FPGA coprocessor ship on every PC motherboard?" Ignoring the daunting language and interface standards issues, and just looking at current hardware approaches to FPGA "coprocessors", the answer must be "not any time soon". Consider that today's power user's CPU (such as a 200 MHz Pentium Pro or a 400 MHz Alpha 21164A) *running out of L1 cache* issues peak three or four instructions per 2.5-5 ns clock. Also consider that the current "low latency high bandwidth" approach to FPGA coprocessor integration is to hang the FPGA on the PCI bus. In this scenario, the kinds of quasi-general purpose computing problems that an FPGA coprocessor can usefully assist with are quite limited. Issuing a write and then a read back operation to the FPGA could easily take 10 PCI bus cycles (300 ns), assuming no PCI bus contention. In that time (assuming hand crafted code (less effort than a FCCM)) a Pentium Pro could issue as many as 180 instructions; the Alpha, 480 64-bit instructions. Future versions of such processors will soon be doing VIS- or MMX-like limited bytewise 8+-way SIMD parallelism, and eventually superscalar versions of same. Such designs might issue between 500 (*) and 4000 (**) hand coded packed byte operations while that single 300 ns FPGA write/read is still in progress. ((At peak speeds like 400e6 clock/s * 4 issue/clock * 8 byte ops/issue, e.g. 12e9 byte ops/s, you have to agree that superscalar micros with bytewise SIMD are going to displace many FPGA applications on PC and workstation platforms.)) So as long as FPGAs are attached on relatively glacially slow I/O buses -- including 32-bit 33 MHz PCI -- it seems unlikely they will be of much use in general purpose PC processor acceleration. Sure, for applications such as cryptography, image and signal processing, they might be a win (***), given a semi-autonomous problem which either fits in the FPGA and local storage, or which can employ DMA to stream data into or through the FPGA without much CPU intervention or management. Of course, the PCI ASIC crowd has the same latency problems, but they don’t share FCCM aspirations of accelerating general purpose computing, rather they focus on the same aforementioned special purpose applications. Five times better latency and four times better bandwidth could be achieved if FPGA vendors invent a way to directly connect their parts to the Pentium Pro external bus, as a peer of the memory/bus controller. A custom, dedicated Pentium Pro interface would probably be required, since FPGA configurable logic would be too slow and electrically incompatible. This could be a good volume business, and not quite the moving target it might appear -- I expect the PPro external bus to be just as ubiquitous and as long lived as have been the 486 and Pentium buses. Someone could make a plug in card which sits in the PPro ZIF socket and which hosts a PPro and its FPGA(s). Alternately, the FPGA coprocessor could be attached on the new advanced graphics memory port, or whatever it is to be called, that will be available in future Intel memory/PCI controller chipsets. One might argue that Xilinx made a big mistake in not offering a version of the XC6200 with a dedicated 66 MHz Pentium external bus interface -- after all it is by far the most popular and most supported processor interface for the most lucrative general computing market. If any vendor does pursue this idea, I would appreciate a couple of sample parts. :-) -- (*) 500 op in 300 ns: forthcoming 200 MHz PPro with MMX: 60 clocks x 1 8-byte MMX insn/clock (**) 4000 op in 300 ns: hypothetical 400 MHz Alpha with each integer unit enhanced for bytewise SIMD: 120 clocks x 4 8-byte insns/clock (***) "win": much cheaper/faster than simply adding a second processor -- Acknowledgements: this posting is a spin-off of a discussion with Mark Shand, and the "way out speculative" question was suggested by Mike Butts. Jan Gray Redmond, WA -- The opinions expressed in this message, and any opinions I might express about FPGAs or the computer industry, are my own personal views and, of course, do not reflect the official views of Microsoft Corporation. Also, I acknowledge the trademarks of the various products named.Article: 3264
For Sale: 72 Altera EPX780QC132-15 devices.
In factory trays sealed in moisture barrier film, bag seal date
1/24/96, will sell 24 pieces, 48 pieces, or all 72. Asking $40/piece or
best offer, terms are COD. We are phasing our Nubus product into PCI which
uses a larger FPGA.
Thanks,
-----------------------------------------------------------------------
Scott D. Davilla Phone: 919 489-1757 (tel)
4pi Analysis, Inc. Fax: 919 489-1487 (fax)
3500 Westgate Drive, Suite 403 email: davilla@4pi.com
Durham, North Carolina 27707-2534 web: http://www.4pi.com
Article: 3265It is a tough thing to implement. Been there. Xilinx has a lengthly info packet on the subject. Quiet helpful. you can probably get it from your distributor. tw38966@vub.ac.be (Rafiki Kim Hofmans) wrote: >Anyone else busy with implementing PCI interfaces in FPGA's ? >Or am I the only newsreader busy with it at the moment ? :( >Regards, >Kim >-- >============================================================================== > ************************************ > * Hofmans Kim * > * * > * tw38966@vub.ac.be * > * khofmans@info.vub.ac.be * > * * > * Brouwerijstraat 62 * > * 1630 Linkebeek * > * Belgium * > * * > * 32-2-3771012 * > * * > ************************************Article: 3266
Hi, you can find a public domain simulator called S2C in ftp://ftp.imec.be/pub/vsdm/SW-distrib/s2c/s2c.4.13.tar.Z In that distribution, documentation on the Silage language is included. Hope this helps, Lode In article <DqtI8L.DKI@tumlis.lis.e-technik.tu-muenchen.de>, markusr@tumlis.lis.e-technik.tu-muenchen.de (Markus Rettinger) writes: |> Hi everybody, |> |> I have a short question: |> |> Does anybody know some good books regardig silage? |> |> I use a power estimation tool which is a free program available at Berkeley. |> It uses silage at the beginning of the optimization. |> |> Thanks a lot in advance. |> |> Best regards |> |> Markus Rettinger |> |> --------------------------------------------------------------------- |> - Lehrstuhl fuer Integrierte Schaltungen | - |> - Techn. Universitaet Muenchen | - |> - Dipl.-Ing Markus Rettinger | - |> - Arcisstr. 21 | - |> - 80290 Muenchen | - |> ------------------------------------------------| - |> - Tel: +49 89 289 225 15 | neue Telefonnr. - |> - Fax: +49 89 289 283 23 | seit 01.05.1996 - |> ------------------------------------------------| - |> - E-Mail: | - |> - M_Rettinger@lis.e-technik.tu-muenchen.de | - |> --------------------------------------------------------------------- |> |> -- ================================================================================ Lode Nachtergaele IMEC V.Z.W. Kapeldreef 75 Touch the ground 3001 Heverlee while carving ! Belgium E-mail: nachterg@imec.be WEB : http://www.imec.be/ Phone : +32 (0)16 28.15.12 Fax : +32 (0)16 28.15.15Article: 3267
ian@PROBLEM_WITH_INEWS_DOMAIN_FILE (Ian McCrum STAFF) writes: > we want to use a simple parallel cable, no expensive Xchecker. Xchecker comes with the software, so I don't follow. I think you get one per license, so unless people hoard them this should suffice. How much is an extra Xchecker cable? --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 3268
tw38966@vub.ac.be (Rafiki Kim Hofmans) wrote: >Anyone else busy with implementing PCI interfaces in FPGA's ? >Or am I the only newsreader busy with it at the moment ? :( I have just finished with a PCI master/slave interface in Lucent Orca. It supports full bandwidth 33MHz arbitrary length burst in both directions and as master or slave. It can be done, but you can't hope to do every operation using the minimum number of clock cycles. Careful pre-assignment of I/O signals to pads is critical, but unfortunately there is no easy to learn how to place them without first going over the process a few times yourself. This is the third circuit board I cut, and still there will be things I would like to change should there be another board made. You may not be able to place the signals in a way that is optimal for wiring out to the PCI edge connector. You need to watch out for places where you absolutely cannot pad with extra clock cycles to allow for internal operation. Architectural restrictions can make things impossible if signals were not placed carefully. If your design is meant only as a stop gap measure before you go to gate array in production boards, you can also cut a few corners as long as it do not affect the normal operation of the bus.Article: 3269
Andre Klindworth wrote: > > ... > This posting seeks feedback on the library of parametrized modules (LPM), > AHDL design style and logic synthesis options within MAX+plusII version 6.01. > ... > > Within a larger design project, I had to design a 16-bit binary up-/down > counter with synchronous and asynchronous reset for an Altera MAX-7000 CPLD. > ... > Since we just got our hands on MAX+plusII version 6.01, I decided to give > a try to the new LPM-modules and instantiated an 8-bit LPM_COUNTER with the > following source code: > ... > The results were disappointing: 17 LCs in a EPM7032 ! > > ... > Next, I tried the following straightforward source code: > ... > > The results, as reported in the .rpt file, where quite good: 8 LCs as expected, > but - what the heck? - 4 sharable expanders? What are those used for. So I took > a closer look to the report file and found the following equation for bit 5: > > ... > For the higher order bits (bits 6 and 7), DFFEs and sharable expanders > (for value0 & ... & value5 and !value0 & ... & !value5) were used. > ... > So I tried FAST, NORMAL, WYSIWYG, switching of this and that advanced option, > turning XOR synthesis on and off, but I didn't arrive at the optimal design. > I finally typed in the logic equation for each bit and compiled with WYSIWYG - > and got the optimum design at last. This hand-made counter is reported to run > at 62 MHz and uses 8 LCs (16 LCs for the 16-bit version). > > Finally I tried the old-style macrofunction 8COUNT and this also result > in an 8 LCs mapping with no expanders. > Hi Andre, nice to meet people, who are examining the SW behind a beautiful front-end. I can confirm your experience. The LPMs are not the best choice so far (except for multiply and add functions of course). I did not yet check Version 6.1, but expect improvements no earlier than in V. 6.2. It would be interesting to know, if the Altera people did the LPM-subdesigns themselves or outsourced them. I also wonder if anyone knows the approaches they take in synthesis, because their tool is so much faster than you would expect when you read research papers on that problems. Possibly they trade synthesis speed versus design speed (??). You did not mention parallel expanders; even if synthesis is not optimal, turning on this option should improve performance. And be aware that a "used" shareable expander can also be a product term that could alternatively be used as a sh. exp (in MAX 7k and 9k), but is actually used to feed the OR. Real sh. exp. have an equation named X... = ... in the equations section of the report file. With advanced synthesis options I typically turn OFF "subfactor extraction" and "reduce logic". Especially "reduce logic" is problematic: I found that it can increase design size, it can crash the logic synthesizer and in some earlier versions it simply led to wrong synthesis results in FLEX8k devices. With LPMs there are unexpected advantages too: You can assign a clique to a LPM_DFF, whereas you cannot do it with a DFF connected to a bus (the "primitive array"). By the way: There is a PLL-macro provided by Altera (in the LPM-directory) that is inherently unreliable, because it uses combinatorial feedback (My customer proved that it is unreliable !...) And you must be careful with a Gray-counter macro (I think it is named gray16.tdf) on their BBS, because it tends to give you a wrong MSB. Did you get feedback from Altera to your questions? AlfredArticle: 3270
Scott Kroeger wrote: > > The FPGA belongs on the CPU die. Once there it gets "free" use of much of the CPU's > facilities (registers, cache, memory interface etc). This should allow the FPGA to > achieve performance improvements over the CPU for operations too wierd to be > contemplated in the normal instruction set. For example, think how easy it would be to > rewire an ALU to perform CRC. > > I expect (hope) to see FPGAs on low end embedded chips as well. What else are we going > to use all that silicon for! > > Cheers, > Scott Three notes: a. FPGA vendors could increase the credibility of the reconfigurable coprocessor concept, if they tried to speed up their own SW with such a board. It need not be fully application independent. It is my impression that Xilinx intentionally delays the 6200 (targeted at such applications), because they do know, that there is no market for it. b. There was a project funded by the EC where a FPGA (CAM-based from Oxford?) was included on a processor from SGS-Thomson (I believe). As far as I know Thomson stopped the work after delivering first silicon (wasn't it in the EETimes?). I also was told that TI investigated FPGA in a DSP. Did they publish their experiences? c. The most promising way: Ask Intel to dug a third cave into the PPro package and specify an interface ... :-) AlfredArticle: 3271
Hi All, I am working on an ASIC, and I need a hardware implementation of the standard CCITT CRC algorithm: x^16+x^12+x^5+1 as used in floppy disk controllers. There are lots of software versions of this, mostly table-driven, but none are in the form comprising a 16-bit shift reg, with some XOR gates around it, which I know are all that is necessary. I have access only to 1 bit of the data at any time, whereas all the s/ware implementations load in at least 1 byte at a time. Attached is a zipfile containing a postscript file of my present circuit. (I hope no-one objects to this "binary" post; it is only 6k.) This very nearly works, but only if the input data is all zeroes! So there must be something wrong with the way I am feeding in the input data. Note that my init of 0xe295 (instead of 0xffff) is deliberate. Any help is appreciated. I have already done the usual web search, not to mention lots of books. PeteArticle: 3272
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`
end
Article: 3273
Hi,
Is XC7336 the cheapest CPLD one can find in the CPLD marcket?
What's the best price in quantity? Who should I order from?
Thanks in advance for any information in this regard.
-GF-
Article: 3274I am trying to implement a design consist of a 256*8 size ROM on a Xilinx FPGA. The rest of the circuit consists of a simple combinational and sequential logic. I use Synopsys FPGA compiler and the the design discription is in VHDL. I have used both "Memgen" program and the behavioural discription to generate the ROM. The behavioural discription almost always(with different contents for the ROM) gives a more optimum design in terms of resources used. Still when the content of the ROM is more random a large part of the resources are taken by the ROM and in many cases PPR tool can not succesfully place the circuit in one FPGA,(this very much depends on the content of the ROM). Can anybody give me some other solutions for the design for the ROM. Again ROM is 256*8 bits, and I am using Xilinx 4000series(4003, 4005).
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