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ben (breddall@atnf.csiro.au) wrote: : Does anyone know how to double the frequency of a clock inside a 4000. I : remember a circuit in some notes but I can't find it in my files. : Ben Its in the Xilinx "The Programmable Logic Data Book", page 9-7 in the 1994 edition. ErikArticle: 3826
Alexandr Solovkin wrote: > > Ray Andraka <randraka@ids.net> wrote: > >ft63@dial.pipex.com (Peter) wrote: > >> > >[stuff deleted] > > > >> But I have more often come across a nastier problem, common to all > >> FPGAs: say you have a 16-bit shift register. Obviously, for a SR to > >> work, the clock skew stage-to-stage has to be less than the clock-to-Q > >> propagation delay. IOW, you ideally want to clock all the stages > >> together. > > > >True. Use the global clock to minimize skew. > > You may manually route clock back to the data flow. > So, if data goes from 1 to 16 register, clock goes to clock16 !before! > then to clock15 and so on. This kills your problem. I'll second that. Dropping a longline constraint on the clock signal, presuming it drives a sufficiently small number of CLB's can also ensure that the clock runs on a single piece of metal with low skew. ScottArticle: 3827
ben wrote: > > Does anyone know how to double the frequency of a clock inside a 4000. I > remember a circuit in some notes but I can't find it in my files. > > Ben See the 1994 databook, page 9-7. It's a little ap-note from XCELL. Basically, you clock a FF from the XOR of your slow clock and the inverted output of the FF. Note that this simply creates a clock pulse on each edge of the input. Symettry is only as good as the duty cycle of the input clock. Regards, ScottArticle: 3828
In article 2181071@news.alt.net, ft63@dial.pipex.com (Peter) writes: > > >I already do this, but I still get flakey operation. Re-routing with tightened > >(or even loosened!) frequency constraints can result in a working design, but > >I'm hesitant to trust these "fixes". Sometimes one part of a circuit will start > >working after re-routing, but another area will develop a problem. > > Does it simulate OK, with a simulator? Which one? The synthesized schematic simulates OK with Cadence's Verilog XL. The back-annotated, post route netlist does not. Unfortunately, all the latter does is tell me it didn't work. There's not much I can do about it other than adjusting router constraints and trying again. ---------------------------------------------------------------------- Jeff Hunsinger jeffh@oakhill-csic.sps.mot.comArticle: 3829
Can anyone give me an AHDL example of exactly how to do a read and a write to an 8 bit BIDIR buffer? The examples in Altera's help file and documentation are (for me, anyway) lacking. They show how to set one up but not how to use it. Forgive me if this is a obvious question but I just started learning FPGA design on Monday! Thanks, FredArticle: 3830
In article <4u87rc$kce@gibelet.nexen.com>, markc@gibelet.nexen.com (Mark
Christensen) wrote:
> Xilinx 8100 series users may want to check out the August 5th
> EE Times cover page. Not surprising given all the problems with
> the part.
Here is the newsrelease issued by Xilinx one week ago, announcing our
withdrawal from the antifuse market.
Although I seem to be, by default, the Xilinx voice in this newsgroup, I
am not in marketing. I just assumed that everybody who needed to know had
already read this release. That does not seem to be the case, so here is
the one-week-old news.
The EETimes cover-page article also quotes Quicklogic and Actel marketing,
and not surprisingly, they take exception to the Xilinx assessment about
the problems with this technology. What else would you expect ?
Wednesday July 31 4:32 PM EDT
Xilinx Discontinues Antifuse Product Development
Mainstream SRAM- and FLASH-based technologies to serve market
SAN JOSE, Calif.--(BUSINESS WIRE)--July 31, 1996--Citing the strong
market acceptance of SRAM and FLASH technologies, Xilinx Inc today
announced it will discontinue the company's XC8100 family of one-time
programmable antifuse devices. The company said it will concentrate on its
core field programmable gate arrays (FPGAs) and complex programmable
logic devices (CPLDs).
The company anticipates taking a pretax charge against earnings in the
approximate amount of $5 million, primarly relating to the write-off of
inventories held by Xilinx, its distributors and its foundry partners.
"The XC8100 team successfully developed a number of patented,
industry-first innovations in antifuse architecture, design, programming
and processes, accomplishments no one else in the entire semiconductor
industry has been able to achieve so far with this difficult technology," said
Xilinx CEO Wim Roelandts. "But the market has chosen. Compared with
SRAM development, there are very few people working in antifuse. As a
result, antifuse will lag behind SRAM, entail disproportionately large
development costs, and be relegated to limited markets. For these reasons
we believe further investments in antifuse product development are too
large to be justified."
The company said employees involved with antifuse development will take
on new duties in other areas in the company. Resources and research and
development spending will be redirected to core areas of the business to
exploit new opportunities. Among others, those include the company's
LogiCore program of drop-in modules, new applications that exploit the
reconfigurable nature of Xilinx FPGAs, and in-system programmability, a
feature of the Xilinx FLASH-based XC9500 family of CPLDs.
Xilinx announced the one-time programmable XC8100 antifuse product
line in September 1995 and only recently began providing sample products
to customers. The company said a number of options are available to
support current XC8100 customers, including helping them move designs to
other Xilinx products and providing software upgrades for those devices.
Founded in 1984, Xilinx is the world's largest supplier of programmable
logic solutions comprising industry leading device architectures and world
class design software. Headquartered in San Jose, Calif., the company
pioneered the market for field programmable gate array (FPGA)
semiconductor devices that provide high integration and quick
time-to-market for electronic equipment manufacturers in the computer,
peripherals, telecommunications, networking, industrial control,
instrumentation and high reliability/military markets.
Note to editors: For more information on Xilinx, access our World Wide
Web site at http://www.xilinx.com. Xilinx is a registered trademark of
Xilinx, Inc. All XC-prefix product designations, LogiCore, and XACTstep
are trademarks of Xilinx, Inc. Other brands or product names are
trademarks or registered trademarks of their respective owners.
CONTACT: Xilinx, Inc.
Mike Seither, 408/879-6557
mike.seither@xilinx.com
Article: 3831Does anyone know how to double the frequency of a clock inside a 4000. I remember a circuit in some notes but I can't find it in my files. BenArticle: 3832
Hello Andreas, The latest Altera newsletter gives an example how to do this with a dc_shell script. You should be able to get this from Your local rep. The idea is to set properties like this: set_attribute find(port, ps2) "CHIP_PIN_LC" -type string "ministate@4" If You can't get hold of the document, drop an email to me and I'll fax the relevant page to You. Regards, Veli-Matti Karppinen Andreas Doering wrote: > > Hello, > I am designung for ALTERA devices (namely EPM9560, EPF10K50) > using SYNOPSYS-FPGA-compiler and Maxplus2. I want to put > my pin assignments into the VHDL-source. > I know that I can edit the .acf file, but Maxplus2-online help tells > that it can be done using EDIF-properties, too. > Now I do not know how to produce these property entries with > FPGA compiler. Attributes on the speciphic ports seem to be ignored. > Is there another way to get around (some kind of awk script, > that extracts the pin assignments and inserts them into the edif file. > I guess this is tedious to write this. > Thanks in advance. > Andreas > -- > --------------------------------------------------------------- > Andreas Doering > Medizinische Universitaet zu Luebeck > Institut fuer Technische Informatik > > Email: doering@iti.mu-luebeck.de > ---------------------------------------------------------------- -- *************************************************************************** ** ** Veli-Matti Karppinen Internet: ventti@fincitec.fi ** ** Fincitec Oy ** ** P.B. 11 tel. +358-698-21490 ** ** FIN-94601 KEMI,FINLAND fax. +358-698-21561 ** ** ** *************************************************************************Article: 3833
Hi, Does anyone knows if it's possible to generate a dual port ram with the memgen program of XACT 6.0.1 for Xilinx 4000E series? Thanks a lotArticle: 3834
Frederic GOFFIN <fg> wrote: >Hi, > >Does anyone knows if it's possible to generate a dual port ram >with the memgen program of XACT 6.0.1 for Xilinx 4000E series? > >Thanks a lot Hi Frederic, Yes, it is possible. You have to set the TYPE parameter to 'DP_RAM' in the memgen ascii input file (.mem). If you don't have a .mem file and start memgen, it asks you the depth, width and the type of the memory you want to implement and creates a memgen input file. YuceArticle: 3835
On the 6th of August, Bryan Harstad wrote:- "I am just starting to look into VHDL, and I am having a hard time locating any kind of evaluation board/software with a Xilinx FPGA, and some inputs/outputs. Does anyone know where I can buy one from? I don't really care what family of Xilinx, but I would prefer something in the 4000 line." In reply:- Parsys Ltd are developing an absolute animal. The card is designed to be fitted with two off Xilinx 4025E-2/3 devices, 8MB DRAM and 128 kB Flash ROM together with a T9000 embedded controller which provides access to a DS Link network. It is intended that the card may be deployed as a coprocessor in a PC bus, or as a node in our switched DS Link Parallel Computer systems. These switched systems are designed to support up to 2048 nodes and we already offer the Alpha AXP 21066 as a node. For the 4th QTR 96 we plan to be bring news of both the Xilinx engine and the 500MHz Alpha AXP 21164 node, available in a heterogeneous environment, up to 2048 of them, hence my reference to animal ! Please keep tuned to http://www.parsys.comArticle: 3836
Mark Christensen writes: >Xilinx 8100 series users may want to check out the August 5th >EE Times cover page. Not surprising given all the problems with >the part. The Xilinx Web Site has a July 31 press release on this subject, "Xilinx Discontinues Antifuse Product Development". http://www.xilinx.com/ http://www.xilinx.com/prs_rls.htm#CORP -- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 3837
Hi, I want detailed information on using carry logic in the XC4000 family of devices. Also, is the document "Using Carry Logic in XC4000s" available from any ftp/web site? A web search didn't yield anything. Thanks for any pointers. regards, Gurpreet.Article: 3838
Questions for XILINX members: For education purpose we use WorkView for design input an XACT (PPR) for fitting to the 4000 serie from XILINX. Both run on DOS or Win3.11. Now we change all plattform (Intel and Alpha) to Windows NT (3.51, later in the year 4.0). All tools from ViewLogic are avialable now. Whats happen by XILINX with PPR or XACTstep and WindowsNT ? Please give me hope and time schedules for our staff and students here in old germany. A not well informed Walter Lang -- Dipl.-Ing. Walter Lang University of Siegen Department of Electrical Engineering and Computer Science Hoelderlinstr. 3 D - 57068 Siegen Phone: +49 271 740 3210 FAX: +49 271 740 3344 E-Mail: lang@ti.et-inf.uni-siegen.de WWW: www.ti.et-inf.uni-siegen.deArticle: 3839
>There is no difference between creating an enable in the logic and using >the clock enable input (which just wraps the ff output back to the ff >input.) This incidentally is a really clever (well, I think so, anyway) way to use a GAL, which normally has only ONE global clock input, as a device with multiple effective clock inputs. Don't laugh! But I also knew someone who published an article in EDN (I think) showing how to use a XOR gate as a "programmable inverter". Peter.Article: 3840
Hi , I need to implement a mono-stable MVB inside an Altera PLD. Could anyone help ?? LEEArticle: 3841
HI, I WOULD LIKE TO KNOW HOW TO MODIFY THE MONISTABLE MULTIVIBRATOR 74HC123 WITH THE TTL CIRCUIT ESPECIALLY IN ALTERA DESIGN OR ORCAD. CAN SOME BODY HELP ME ? REGARDS -LEE, MALAYSIAArticle: 3842
HI, I WOULD LIKE TO KNOW HOW TO MODIFY THE MONOSTABLE VIBRATOR 74HC123 IN TO THE TTL CIRCUIT, ESPECIALLY IN ALTERA MAX 7000 ISP DESIGN OR ORCAD SOFTWARE. CAN ANYONE HELP ME ? REGARDS -LEE, MALAYSIA.Article: 3843
Hi, I am interested in pin layout for simms. I tried web sites of some vendors like motorola and ti, but was not usefull. Does any one know where I could find this info. Any pointers will be appreciated. Thank you Sid TakkellaArticle: 3844
Some people might be interested in the way we have tackled timing problems using Xilinx chips. We are not exactly a standard user of FPGAs as we are compiling directly from parallel programs into hardware without ever visiting the hardware level, so we had to do something different to escape the problems of timings which programmers would not be able to tolerate from their `hardware programs'. Typically we work with an FPGA co-processor (XILINX 3K) and a standard micro. The hardware program running in the FPGA does so synchronously, but with a clock unrelated to the microprocessor (necessarily in our case). Getting the clock frequency right for the FPGA is easy as we have a processor- controlled synthesiser, but the difficult issue is the interface hardware. This interface circuitry supports (CSP-style) channels between the software and hardware and has to be *very* carefully designed as it necessarily has to deal with metastability. We found that this part of the circuit had to be pre-placed as well as pre-routed in order to work reliably. We found that the xilinx tools were not sufficient to support designs where part was pre-routed and the rest (the hardware program) was handled by apr. So we built the `xmacros' software system which generates parametrised interfaces as pre-placed XNF and then generates the files which simulate an xact editor session to do the wiring up (since xnf couldn't carry routing information). The result is that we now have a fire-and-forget hardware compiler where we never normally have to worry about timing issues at all. The down-side is that it was really hard work to produce the xmacros software and it is very technology-specific; It might be possible for us to re-implement for 4k series chips, but we would obviously have to start again from scrath for any other FPGA. If anyone has any experience of, or good ideas about, *technology-independent* ways of building difficult (eg. metastable-capable interface) circuits in FPGAs, we would be very interested to correspond. We are expecting to have to tackle this problem again for both the 4k and 6k series parts in the near future. Ian Page. PS. Our web site is at http://www.comlab.ox.ac.uk/oucl/hwcomp.html and the xmacros document is at ftp://ftp.ox.ac.uk/pub/users/adrian/xmacros.ps.gzArticle: 3845
In article <32091BC2.3974@atnf.csiro.au>, ben <breddall@atnf.csiro.au> wrote: > Does anyone know how to double the frequency of a clock inside a 4000. I > remember a circuit in some notes but I can't find it in my files. > I should know, because I designed it. The description is on page 9-7 of the 1993 and1994 Data Books ( we are just now distributing the completely revamped 1996 data book, which doe not contain that circuit ) The circuit works pefectly, although digital purists frown on such analog dirty tricks, and I made that clear in the last paragraph of the description. Peter Alfke, Xilinx ApplicationsArticle: 3846
ben wrote: > > Does anyone know how to double the frequency of a clock inside a 4000. I > remember a circuit in some notes but I can't find it in my files. > > Ben From There Data book: F(in) goes to 1 input of XNOR gate. Output of XNOR is F(out) and is connected to clk of D FF. Q output of D FF goes to inverter. Output of inverter goes to 2nd input of XNOR and to D input of D FF. Note: They don't recommend this because it is asynchrounous.Article: 3847
Hi, I'm looking for extended optimised libraries for Xilinxs' XC4000 series chips. I am using the latest DOS version of OrCAD for schematic entry. Does anyone know if such extended libraries exist and if so where I can get a hold of them? I am specifically after such things as 2-bit and 5-bit adder/subtractors. Thanx in advance. Jason. ==================================================== Jason Crawford. B.E.(Hons 1) Experimental Scientist. Radio-Systems Program CSIRO Division of Radio-Physics phone: +61 2 9372 4163 fax: +61 2 9372 4490 e-mail: jcrawfor@rp.CSIRO.AU web: http://www.rp.csiro.au/staff/jcrawfor.html ====================================================Article: 3848
Fred Hamilton wrote: > > Can anyone give me an AHDL example of exactly how to do a read and > a write to an 8 bit BIDIR buffer? The examples in Altera's help > file and documentation are (for me, anyway) lacking. They show how > to set one up but not how to use it. Forgive me if this is a obvious > question but I just started learning FPGA design on Monday! > > Thanks, > > Fred No, I cannot give you an example, because I did my design in schematics, but I can add a warning (hope I do not confuse you more): In the current version (6.2) I found that you can get a wrong synthesis result in hierarchical designs, if you use tri-state busses (i.e. have several registers attached to the bus). If you connect inputs and outputs of registers to the bus in the same hierarchical level, you might not understand the equations of the result any more. You have to define two busses, connect inputs to one, outputs to the other and connect them in the hierarchical level above with a WIRE primitive between (in schematic entry at least). There are some strange things in their way to use tri-state busses and - unusual for Altera - they are indeed not documented well. Good luck FredArticle: 3849
Create a top level entity and architecture with the bus oriented signal eg counter(7 downto 0). Then instantiate the synthesised version as a component under this top level and manually join counter(x) => counter_x in your port map
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