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To All Site License Users Does anyone know where I can find a public-domain simulator that will give me functional simulations of the MAX7000 designs I want to do with my Site License? I don't need timing; I'm not doing FPGA designs. Bob LowellArticle: 3676
Ingo Cyliax wrote: > > we are building small robot controllers based on Xilinx > FPGAs (XC3030PC44). Since these robots are non-tethered, > we would like to download configurations to the FPGA over > a wireless channel. We do have a low-speed (300baud) IR > channel to the robot which used for control, but the > receiver (USART) is implemented on the FPGA. The required > range is limited (less than 10ft), i.e the same as for > the IR channel. > > Has anyone come up with simple schemes to download FPGAs > over wireless (or single wire) channels ? > > Thanks for any comments. It's pretty easy. Place a single pole RC lowpass on the DIN pin (say 2us RC). Now drive CCLK and the input of the DIN lowpass filter from a single signal. You clock a zero into the part with a low pulse of 6us (this is the longest you can hold CCLK low I think). You clock a one into the part with a low pulse of 500ns in length. You can probably drive PROG from a 1ms lowpass filter on the CCLK line, but you will have to violate the CCLK low period to drop PROG and I don't know if that will cause problems. Regards, ScottArticle: 3677
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Article: 3678we are building small robot controllers based on Xilinx FPGAs (XC3030PC44). Since these robots are non-tethered, we would like to download configurations to the FPGA over a wireless channel. We do have a low-speed (300baud) IR channel to the robot which used for control, but the receiver (USART) is implemented on the FPGA. The required range is limited (less than 10ft), i.e the same as for the IR channel. Has anyone come up with simple schemes to download FPGAs over wireless (or single wire) channels ? Thanks for any comments. See ya, -ingo -- /* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */Article: 3679
Robyn Cheyne wrote: > > Hi, > > I am looking for a simple emulation software system to help a > feasibility analysis of building a prototype board. > > I have limited CAD experience, so any assistance would be greatly > appreciated. > > Thanks, > > Robyn Cheyne > > email me at sci-rjc2@jcu.edu.au > -- > > ,\/~~~\_ _/~~~~\ > | ---, `\_ ___,-------~~\__ /~' ,,'' | > | `~`, ',,\`-~~--_____ --- - /, ,--/ '/' If you have some time check out MultiMedia Logic. What is it? It's an Interactive Logic Design and Simulator System. When you drop down a gate or switch you can instantly use it. You can not only interface your circuits to simple "Boolean" devices like an LED, but also things like, .BMPs, .WAVs, PC speaker. You can also interface it to work with real hardware through the COM/LPT ports. A picture is worth a thousand words. Which you can get when you visit http://www.ultranet.com/~mills Check it out, I'd love to get your feedback.Article: 3680
If you have some time check out MultiMedia Logic. What is it? It's an Interactive Logic Design and Simulator System. When you drop down a gate or switch you can instantly use it. You can not only interface your circuits to simple "Boolean" devices like an LED, but also things like, .BMPs, .WAVs, PC speaker. You can also interface it to work with real hardware through the COM/LPT ports. A picture is worth a thousand words. Which you can get when you visit http://www.ultranet.com/~mills Check it out, I'd love to get your feedback.Article: 3681
[was Re: What about the XC6200?] cgamrat@gaap.saclay.cea.fr (GAMRAT Christian) writes: >Is There anybody out there who knows anything new about the Xilinx XC6200 >partially reconfigurable fpga ? >The data available from Xilinx has not changed for months and it looks like if they >are not pushing the device ahead anymore. >I hope I'm wrong because this FPGA is a must in the field of reconfigurable >computing. It will be really Dommage ! William Roelandts (new Xilinx CEO) stated that developing recongifurable logic with "the ability to change the logic configuration of the FPGA during the operation of the device" is something that will be aggressively continued. Anyone from Xilinx care to expand on the details of this strategy? -- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 3682
> Hello. > I'm not quite suttisfied from the israeli EastRonics Altera vendor > services and availiability, and since they are the only one in israel, > i'm searching for a second source of altera's chips e.g AT&T for Xilinx. > > So please, if you know about it anything please remail me to: > mailto:gabby@isv.dec.com As far as I know is Philips manufacturing one or two devices which are pincompatible with ALTERAs small 7000 EPLDs. I think they even have a low cost compiler for it. Contact Philips for more details. I hope it helps .. TomArticle: 3683
>we are building small robot controllers based on Xilinx >FPGAs (XC3030PC44). Since these robots are non-tethered, >we would like to download configurations to the FPGA over >a wireless channel. We do have a low-speed (300baud) IR >channel to the robot which used for control, but the >receiver (USART) is implemented on the FPGA. The required >range is limited (less than 10ft), i.e the same as for >the IR channel. > >Has anyone come up with simple schemes to download FPGAs >over wireless (or single wire) channels ? My first reaction is the need for some error detection, unless your radio link is already 100%-solidly error corrected. If you are using the 3030 then it is easy to fill it with garbage, and end up with e.g. lots of TBUFs all shorting together. The device can get extremely hot. The 3030A do simple frame checking which helps a lot, but if your radio link is in any way error-prone then you should do some additional checking and, if the link is not duplex, you may need to package the data and send each packet several times. You may need a micro there to do this stuff. The 4k series do CRC checking but that will not solve the problem of data corruption on the way in. And please also remember that the devices (the 3k series, at least) need a good edge on CCLK. Anything slower than about 30ns causes problems. I would use a simple and as slow (i.e. noise-immune) as possible FSK or switched-carrier scheme, with some local logic to ensure that the 5us minimum low time for CCLK is never violated. Peter.Article: 3684
In article <4s2rgh$eba@news.cea.fr> cgamrat@gaap.saclay.cea.fr writes: > Is There anybody out there who knows anything new about the Xilinx XC6200 > partially reconfigurable fpga ? ... > I hope I'm wrong because this FPGA is a must in the field of reconfigurable > computing. It will be really Dommage ! Whilst it is an exciting offering, I don't see that it is that much more radical than the Atmel CacheLogic parts. Perhaps they don't feel that thay've got anything to bring to the party? I stand corrected if I am wrong. -- ----------------------------------------------------------------------------- | Andrew Morley, Design & Development, Trend Communications Ltd, High Wycombe.| | email: andrew.morley@trendcomms.com Phone +44 1628-524977 Bucks, UK.| -----------------------------------------------------------------------------Article: 3685
For Sale.. 3.5" disk by Advanced Management Systems Ltd. Contains PCI expansion board dimensions, pinouts, and PCI signal descriptions. Has a complete description of a basic PCI interface designed using cheap Lattice Field Programmable Gate Arrays (FPGAs), including circuit diagrams, chip equation files, info on cheap FPGA development kits, and C++/ASM Windows 32-bit source code to access PCI. 3.5 inch disk- Price 20 UK pounds Tel. 0181 689 3434 -- Austin O'HaraArticle: 3686
Hi all, today I got the AT17Cxxx upgrade for our programmer. The problem: I cannot program the RESET polarity of the EEPROM to active low. I like to know if this is a bug in the upgrade or in the 17C65. Is there anybody who can check this at a 17C65 with a Datecode of 9605 (last line on the PROM print) or earlier? E-regards --------------------------- Rainer Scharnow (amigo@bintec.de) BinTec Commmunications GmbH ---------------------------Article: 3687
On Mon, 15 Jul 1996, Rainer Scharnow wrote:
> ...
> who can check this at a 17C65 with a Datecode of 9605 (last line on the
> PROM print) or earlier?
^^^^^^^
Grmf, that was bullsh*t. :-(
E-regards
---------------------------
Rainer Scharnow
(amigo@bintec.de)
BinTec Commmunications GmbH
---------------------------
Article: 3688Hi I'm interested in Software to dissassemble the contents of the serial EEPROM connected to a XILINX XC3195. I'm writing a Linux-Device-driver for a PCI-Framegrabber, and I can't support Busmaster-DMA, because I have no documentation. The Xilinx Chip is loaded from a serial EEPROM, so I want to understand the contents. At Xilinx I found no Free Tools. -- Jochen Karrer http://cip.physik.uni-wuerzburg.de/~cip307 ---Article: 3689
Hi PLD cracks, if you are interested in the programmer I am using - forget it :-) It is a part of the company CELECTRONIC from Berlin, Germany (where I come from, too). I think that programmer named PROMICROM 1000 will be absolutly unknown in the US. But yesterday I contacted the programmer's programmer :-). We stated that he is using an ATMEL databook as reference for the EEPROMs but my source for the manuals about the algorithms were www.atmel.com. And now the surprise: we stated further that the algorithm for adjusting the reset polarity high or low had been swapped between the two documents. Are these differences known? E-regards --------------------------- Rainer Scharnow (amigo@bintec.de) BinTec Commmunications GmbH ---------------------------Article: 3690
Does anyone have data on the radiation tolerance (total dose and dose rate) of various vendors' FPGAs, CPLDs and PLDs. I've used rad-resistance Actel parts and would like to consider devices from other vendors as well. Thanks, Mike ------------------------------------------------------------------- | Michael A. Johnson | Laboratory for Extraterrestrial Physics | NASA/Goddard Space Flight Center | email: michael.a.johnson@gsfc.nasa.gov -------------------------------------------------------------------Article: 3691
The UNIVERSITY OF CALIFORNIA EXTENSION,
BERKELEY presents two short courses in IC
technology
1. "Electrostatic Discharge (ESD) in
Integrated Circuits---Protection Techniques
to Improve Reliability in Integrated
Circuits"
September 30-October 2, 1996
San Francisco Airport. Fee $995
Covers basics of ESD protection; CMOS ESD
input protection; failure modes and
characterization; testing for ESD; tester
models; transmission line pulsing; wafer
level monitor; issues in ESD; device physics;
CMOS output protection; process effects;
internal protection; bipolar/BiCMOS; CDM
phenomena and protection; failure analysis
tools; electrical overstress; device and
ciruit simulations; case studies; failure
examples; open session questions.
Lecturers:
Ajith Amerasekera, Ph.D., Senior Member of
the Technical Staff, Device Design
Laboratory, SEmiconductor Process and Device
Center, Texas Instruments
Charvaka Duvvury, Ph.D., Seniro Member of the
Technical Staff, Texas Instruments
Gadi Krieger, Ph.D., President of QualiTau,
Inc.
Timothy J. Maloney, Ph.D., Principal
Engineerin, Intel Corporation
Tom Polgreen, Ph.D., Staff Modeling
Engineer, Dallas Semiconductor
---------------------------------------------
2. "Gate Oxide Damage From Plasma
Processing---Understanding, Measuring and
Minimizing Gate Oxide Damage"
October 31-November 1, 1996
San Francisco Airport. Fee: $795
Covers effect of electrical stress on oxides;
plasma currents, voltages and charging;
factors affecting charging damage; topography
dependent charging in uniform plasmas;
charging damage results; charging
measurements; damage reduction and
protection.
Lecturers:
Calvin T. Gabriel, M.S.E.E., Manager of
Plasma Etch and CMP, Technology Development
Group, VLSI Technology, Inc.
James McVittie, Ph.D., Senior Research
Scientist, Stanford University Center for
Integrated Systems.
Krishna C. Saraswat, Ph.D., Professor of
Electrical Engineering, Stanford University
---------------------------------------------
For a brochure describing both courses in
detail, please send your POSTAL ADDRESS or
FAX number to course@garnet.berkeley.edu
Please reference "short courses in IC
technology"
Article: 3692> Message: 2 > From: Andrew Morley <andym@trend.demon.co.uk> > Date: Sat, 13 Jul 96 15:00:09 GMT > Subject: Re: What about the XC6200 ? > > In article <4s2rgh$eba@news.cea.fr> cgamrat@gaap.saclay.cea.fr writes: > > > Is There anybody out there who knows anything new about the Xilinx XC6200 > > partially reconfigurable fpga ? > ... > > I hope I'm wrong because this FPGA is a must in the field of reconfigurable > > computing. It will be really Dommage ! > > Whilst it is an exciting offering, I don't see that it is that much more > radical than the Atmel CacheLogic parts. Perhaps they don't feel that thay've > got anything to bring to the party? I stand corrected if I am wrong. > > - -- > ----------------------------------------------------------------------------- > | Andrew Morley, Design & Development, Trend Communications Ltd, High Wycombe.| > | email: andrew.morley@trendcomms.com Phone +44 1628-524977 Bucks, UK.| > ----------------------------------------------------------------------------- > Stand corrected:) The 6200 is a fine grain architecture but there is a big differance in both the hardware and the open system philosophy. First the hardware interface is structured in such a way as to provide direct access to both the configuration memory and the *data registers*. This means you can directly read data out of the 6200 without going through the user I/O pins, this is radicaly different than any other divice. The device is programmed like SRAM and is easy to understand. Another very different accpect of the 6200 is the fact that you can load a random bit stream into the device with blowing one up. So what you say? Well I just saw one of the most important (IMHO) designs ever downloaded into an FPGA at a little conferance at Cornell. Xilinx brought out a little robot (about 1x2x4 inches) that ziped back and forth on the table. Whats so important about this? The configuration was not designed by any human but by a genetic algorithm. Its cost function was to go forward as fast as possible. It took over 4000 generations to evolve. The little robot had 8 sensors (N,NE,E...) but in the end desided it only needed NW and NE. It did not need the sensors behind it (even though it backed up when you put your hand in front of it). I can imagine a day when engineers design cost functions and not hardware. The other thing I saw at this workshop was design tools for the 6200 developed by people other than Xilinx. Did they sign their life away? NO. The data sheets for the 6200 tell you how to explicitly program the 6200 down to the bit level. I saw a whole cad tool (obeoron) and tight little multipliers that completly by passed the Xactstep6200 tools (there is nothing wrong with the tools it is just to prove you don't have reverse engineer anything to program the 6200 they tell you up front). This open system approach is the best way for reconfigurable computing to take off (or any kind of computing for that matter). All in all I believe the 6200 brings a significant number of new and exciting features to FPGAs and really starts to take reconfigurable computing to new frontiers. Steve Casselman, President Virtual Computer CorporationArticle: 3693
Article: 3694
I'm just starting out as an independent. I have a little money for eqipment and software, but I need to spread it as thinly as possible. I'm aware of PLACE from ICT (free), and Warp2.0 ($99) from Cypress, which will let me program a very limited set of devices. Does anyone know of low-cost or free software for a wider range of devices from several manufacturers? Reply by e-mail to jperry@norfolk.infi.net, and I'll collect the responses and repost them if anyone is interested. John Perry Embedded ElectronicsArticle: 3695
>I'm interested in Software to dissassemble the contents of >the serial EEPROM connected to a XILINX XC3195. As Xilinx will tell you, the relationship between the bitmap data in the EEPROM and the netlist is a "closely guarded secret" known only to Xilinx and, presumably, to developers of 3rd party FPGA place/route tools. Peter.Article: 3696
Steve Casselman wrote: > ...<deleted> - my news reader enforces short quotes > ... > All in all I believe the 6200 brings a significant number of new and exciting > features to FPGAs and really starts to take reconfigurable computing to > new frontiers. > VERRY interesting - I HAD casually dismissed the 6200 as Yet Another Revolutionary Fine-grained FPGA Family (YARFFF), but as you point out, the open architecture makes a BIG difference. The prelim. data sheet, by the way, is available on Xilinx's web site. Sort of reminiscent of the Concurrent Logic 6000 parts. Did Xilinx buy them out? Thanks for the info - tomArticle: 3697
Hi, I just installed the Xilinx kit for mentor graphics and I discovered that there is no Autologic synthesis library for Xilinx, is this an error?? I there a public domain Xilinx synthesis library for autologic?? Thanks in advance, -- ------------------------------------------------------------------------------- Fernando Pardo (Profesor Ayte. Facultad) | e-mail: Fernando.Pardo@uv.es DECV (Dise~no Electronico y Circuitos VLSI) | pardo@glup.eleinf.uv.es Universidad de Valencia | Phone : +34 6 360 4484 C/ Hugo de Moncada 4-Entr. | Fax : +34 6 361 6198 46010 Valencia (SPAIN) | WWW: http://carpanta.eleinf.uv.es -------------------------------------------------------------------------------Article: 3698
> VERRY interesting - I HAD casually dismissed the 6200 as..... Sort > of reminiscent of the Concurrent Logic 6000 parts. Did Xilinx buy > them out? > No, the 6200 is very different animal than the CLI architecture. The Atmel AT6000 and the NSC CLAy series parts are the only ones licensed to use the CLI architecture. The 6200 differs in that it is LUT based, and it allows essentially random access to the array. Both parts allow partial reconfiguration while the rest of the device is being clocked. The CLI architecture holds flip-flop state on a cell when that cell is reconfigured, while the 6200 resets the flip-flop to zero. The holding of state can be useful for certain applications, but can also cause headaches if not handled properly. Generally speaking, the LUT architecture is easier to design with, but the small size of the cells in the CLI array can provide more complexity and higher speeds on certain types of designs if you are careful with the design. As far as which is the better part...it depends on the application. -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our homepage.Article: 3699
> VERRY interesting - I HAD casually dismissed the 6200 as..... Sort > of reminiscent of the Concurrent Logic 6000 parts. Did Xilinx buy > them out? > No, the 6200 is very different animal than the CLI architecture. The Atmel AT6000 and the NSC CLAy series parts are the only ones licensed to use the CLI architecture. The 6200 differs in that it is LUT based, and it allows essentially random access to the array. Both parts allow partial reconfiguration while the rest of the device is being clocked. The CLI architecture holds flip-flop state on a cell when that cell is reconfigured, while the 6200 resets the flip-flop to zero. The holding of state can be useful for certain applications, but can also cause headaches if not handled properly. Generally speaking, the LUT architecture is easier to design with, but the small size of the cells in the CLI array can provide more complexity and higher speeds on certain types of designs if you are careful with the design. As far as which is the better part...it depends on the application. -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our homepage.
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z