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I've got a customer who needs to sort a list of up to 100 80 bit words in hardware. The sort is on a 16 bit field within the 80 bit word. An address counter provides a count from 0 to 64k. Whenever an entry in the list has an address field that matches the address count, the 64 bits associated with the address field need to be output in parallel on the next 40M clock. I'm wondering if anyone has come up with a cute way of doing either a sort on the data going in or an associative read to get the data out? -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our homepage.Article: 3701
Mail*Link(r) SMTP request for inclusion Please sign me on to your listing: anne.greene@xilinx.com Thanks, AnneArticle: 3702
In article <4sji6m$50h@paperboy.ids.net> Ray Andraka <randraka@ids.net> writes: >I've got a customer who needs to sort a list of up to 100 80 >bit words in hardware. The sort is on a 16 bit field within the 80 >bit word. An address counter provides a count from 0 to 64k. >Whenever an entry in the list has an address field that matches the >address count, the 64 bits associated with the address field need to >be output in parallel on the next 40M clock. I'm wondering if anyone >has come up with a cute way of doing either a sort on the data going >in or an associative read to get the data out? Are the sort keys guarantied to be unique? If not, what are you supposed to do if 2 or more match? Do you have to accept the data on consecutive 40M clocks? How much time do you get between the acceptance of the data and the output of the data? Can you afford to use a 64K by 8 bit ram? -- dennis@netcom.com (Dennis Yelle) "You must do the thing you think you cannot do." -- Eleanor RooseveltArticle: 3703
Hi, We use XDE to move probes around, and to drive Xchecker. When we changed to the 6.0 release we had a lot of trouble getting XDE to work, and eventually found that it would only work in VGA4 mode (this VGA diamond stealth card running at 1164 x 852 / 256 color). Now that we have converted a 4005H design to 5210 XDE always crashes at exit, and takes over 5 minutes to load, accompanied by a lot a disk thrashing. The 4005H design took less than 30 seconds. "crash" in this context means black screen, Ctrl-Alt-Del doesn't work, hard re-boot needed. Has anyone found a way round this problem, or is it video card sensitive ? -- Gavin Melville, gavin@cypher.co.nzArticle: 3704
John Cooley (jcooley@world.std.com) wrote: : Felix K.C. CHEN <flxchen@diig.dlink.com.tw> wrote: : >** internal error: vhdlsim: : >Please Report (No attributes on signal /T_BENCH/TO_SW/ESWCLK) : >FAULT CONTEXT : > program: 'vhdlsim' : > release: '3.3b' : > Architecture: 'sparc' : > phase: 'Run-time' : > last UI Command: run 200 : > simulation time = 0ps : >FAULT ID: : >'2304524 374576 454228 323452 324296 79012 3049100 3046720 300676 8300' : > : >Have any of you encountered similar troubles before? I need help. Have you had a loook at the 'Simulation Release Information' in 'iview'. Might prove helpful ! -- AbhijeetArticle: 3705
MUG '96 Call for Papers
Mentor Graphics Users' Group
13th Annual International Conference
Shaping the Future with Technology
October 21-24, 1996
Janzten Beach Red Lion Hotel, Portland Oregon
------------------------------------------------------------------------
The International Mentor Graphics Users' Group (MUG) is seeking
technical papers for its annual users' conference to be held in
Portland, Oregon, October 21-24, 1996. The 1996 Conference provides MUG
members with a forum in a relaxed atmosphere for interaction with other
users and Mentor Graphics employees.
MUG invites submissions that will interest circuit and system design
engineers and engineering managers, layout professionals, CAE support
engineers and managers, and system administrators. PRACTICAL EXAMPLES,
CASE STUDIES, and USER EXPERIENCES are of particular interest. While
some introductory and overview papers will be selected, preference will
be given to papers with significant technical content. Paper topics
include but are not limited to:
* PCB/MCM Design, Layout, and Simulation
* IC Design, Layout, and Simulation
* ASIC/FPGA Design and Implementation
* Using Simulation to Improved Design Flow
* Process Improvement and Work Flow
* System Administration
* Hardware/Software Co-Design
* Embedded Software Development
* Customization/Userware
* Intellectual Property and Data Management Issues
* University Curriculum and Research Issues
Abstracts of 250 words or less must be submitted by August 12, 1996.
Participants will be notified of acceptance by August 19, 1996. Final
papers must be received by September 16,1996 in order to receive free
conference admission.
Prospective authors are invited to send an electronic copy of their
abstract, along with a one paragraph biography and the approximate
length (in minutes) of their presentation, to the MUG Program
Chairperson at Program_Chair@MentorUG.Org. Submissions should be made
as plain ASCII text. Be sure to include the title of your presentation,
topic area, author(s) name, job title, company name, complete mailing
address, phone number and e-mail address. In case of multiple authors,
one author should be identified as the contact person. The abstracts of
accepted papers will appear on the WWW before the conference. MUG
reserves the right to edit abstracts and biographies to meet length and
grammatical guidelines. An example abstract and bio can be found on
our web site at:
www.MentorUG.Org/Conferences/1996/info/example_abstract.html
Authors of accepted papers will be expected to make a 20 or 30 minute
presentation at the conference. The presenter of an accepted paper will
receive free admission to the conference, a $425 value. 30-minute time
slots are limited and will be reserved for topics that contain detailed
technical discussions requiring the extra time. Authors of accepted
papers will receive additional instructions with their acceptance
notice.
Visit http://www.MentorUG.Org for additional information about MUG and
the Conference. A sample abstract template as well as example papers
from MUG'95 are available there.
Important Dates
Abstracts Due: August 12, 1996
Notification of Acceptance: August 19, 1996
Final Papers Due: September 16, 1996
Conference Dates: October 21-24, 1996
Contact Information
Author Information: Program_Chair@MentorUG.Org
Conference or MUG Information: Info@MentorUG.Org
To join MUG: Join@MentorUG.Org
WWW Address: http://www.MentorUG.Org
--
------------------
Hardy J. Pottinger
URL: http://karnaugh.ee.umr.edu/~hjp
University of Mo - Rolla Dept of Elect. Engr (573) 341-4511
Article: 3706Can you implement a state-machine-driven ripple (or bubble?) sort? The one which just keeps exchanging consecutive pairs of items (until a pass has been made on which nothing had to be exchanged) should be quite simple to do. The quickest way, runtime-wise, would be to insert a new value into the right place right away, but that would require a lot of parallel logic. Peter.Article: 3707
Ray Andraka <randraka@ids.net> writes: > ... sort a list of up to 100 80 bit words in hardware. The sort is > on a 16 bit field within the 80 bit word. Can you afford 1600 XORs, plus probably another equal amount of other stuff? If so, you could build a shifting sorter that sorts your data into a list as it comes in (probably possible at the clock rate). To extract the data, reverse the shift direction and compare your address counter with the word at the head of the list. ~ JohnArticle: 3708
Marc Palmarini wrote: > > Hi, > > I'm currently working on a project wich involves very-high speed clock rate. Over the 100 MHz. > We're considering CPLD and/or FPGA. From what I can see, and have been informed by several compagnies. > CPLD offer less complexity, but more speed. Is this right ??? Also, I'd like to know if anybody > has had to work with different brand of CPLD/FPGA. We've been looking at two brands, first there is > the CYPRESS line, and then there's the the QuickLogic line (any comment/suggestion). Are there any other > lines that works at a higher than 100 MHz clock. Typically our project needs to access RAM (Burst Technique) > with acces to a peripheral (LCD Interface). Wich will need to be able to calculate an Adress/Data from an > (x,y) pixel position. That is about all the job for the PCLD/FPGA. I need at the very least 64 I/O line. > > Thanks in advance for any comments and/or suggestions. > > -- > ============================================================ > Tel:(418)-871-8977 Marc Palmarini > Fax:(418)-871-9021 ATI International > > E-Mail:amphi_t@acica.com Timing for CPLDs is deterministic and predictable however on FPGAs the timing depends on the place and route. Which will be faster depends on the size of the design. FYI there is no difference architecturally between Cypress and Quicklogic FPGAs. Another possibility is the FPGA line from Actel. If you need a reprogrammable FPGA you might want to look at the ORCA line from Lucent Technologies (formerly AT&T). ------------------------------------------------------------------------------------------ All opinions expressed is this message are my own and should not be interpreted as representing the views of DOE or WSRC. Bryan Bushart Net: bryan.bushart@srs.gov Phone: (803)725-3472Article: 3709
I'm interested in opinions of engineers that have transitioned (or are considering transitioning) from the traditional schematic-only design environment of FPGAs and CPLDs to the HDL synthesis environment. 1) How important is schematic capture to you - the ability to continue to design in technology-specific symbol libraries? Do you consider it critical to be able to mix HDL and schematic blocks within a design? Why or why not? 2) What is your opinion of graphical tools for hdl-based design? Do you or would you use them or would you prefer to strictly stick with text-only HDL design? What graphical tools do you or would you like to use (for example, state diagramming, block diagraming, ...)? 3) For HDL entry, do you have an editor that you prefer over others? If so, what features do you consider most essential? 4) How important is testbench generation to you? How much of your time is spent in verification? Do you currently use any tools for test bench generation? 5)Do you use any form of revision control (RCS,...)? How important is revision control to you? 6)What other tools/features would you like to see in your CPLD/FPGA synthesis environment? (A slightly open-ended question...) Thank-you! Mike Lottridge Technical Marketing, Antares Corporation 8905 SW Nimbus Ave. Suite 155 Beaverton, OR 97008 mike_lottridge@antaresco.com (503)526-1702 http://www.antaresco.comArticle: 3710
Hi Ray hows it going? > No, the 6200 is very different animal than the CLI architecture. The > Atmel AT6000 and the NSC CLAy series parts are the only ones licensed > to use the CLI architecture. The 6200 differs in that it is LUT based, > and it allows essentially random access to the array. The 6200 is multiplexer based and each cell has a register and can implement any function of two inputs. > Both parts > allow partial reconfiguration while the rest of the device is being > clocked. The CLI architecture holds flip-flop state on a cell when > that cell is reconfigured, while the 6200 resets the flip-flop to > zero. The holding of state can be useful for certain applications, > but can also cause headaches if not handled properly. I don't think this is true although I could not find it stated explicitly in the data sheet. All the configuration bits are random access and so when a cell's configuration is changed only those bits that need to change are changed. There is a mode call "protected" (RP) where the flip-flop can only be changed from the interface and can not be changed even by the global reset. Any of the registers can be read in at most two clocks without taking up any extra routing and with very little fore thought all the important user registers can be read in one clock. > Generally > speaking, the LUT architecture is easier to design with, but the > small size of the cells in the CLI array can provide more complexity > and higher speeds on certain types of designs if you are careful > with the design. As far as which is the better part...it depends on > the application. > The "size" of the cells is the same. Any function of two inputs (or a multiplexer). Also the logic can be placed in front of the register OR in back of the register and the data from the register can be routed from the back to the front internal to the cell. Some other nice features (as long as I have the data sheet out:) are a wild card register that allows you to configure more than one configuration location if you are doing some cellular array designs (bit slice stuff). Also there is a map register. Since there are 64 rows and 64 columns and a 32-bit microprocessor interface you can choose which of the 64 registers in the column space are mapped to the 32-bit microprocessor interface. Kind of like a hidden reconfigurable bus. One other feature which is really nice is a global signal that you can use that tells the internal logic that an access to the part through the interface has been made. This could be used to clock a counter to a memory address to allow the microprocessor to DMA data into a ram connected to the 6200 (or lots of other stuff). I think all of the above is correct if not let me know. Steve Casselman Virtual Computer Corp.Article: 3711
In article <Pine.SUN.3.91.960716092346.21224A-100000@Bundy>, amigo@bintec.de says... > >Hi PLD cracks, > .... >We stated that he is using an ATMEL databook as reference >for the EEPROMs but my source for the manuals about the algorithms >were www.atmel.com. And now the surprise: we stated further that >the algorithm for adjusting the reset polarity high or low had >been swapped between the two documents. Are these differences >known? Hello Rainer, until two days ago i also had difficulties programming the polarity fuse in an 17c128 ( same data sheet aand programming information). I tried to program the device in circuit via its I2C bus. I used information downloaded in march from www.atmel.com. After your last message i downloaded the information again. New File, larger than the old ( it now contains also information for in circuit programming), and as you stated the information regarding the polarity fuse is now inverse to the old. After trying it with the new information all went correct and i could also programm the polarity fuse and not only the data block. Somewhere in an older thread someone stated that Atmel changed the default polarity of its reset/oe fuse, maybe at this time they changed also the programming algorithm. Thanks for your unintended help. I hope this Information is also helpfull for you and others. Regards Klaus - Guenter LeissArticle: 3712
(my) experience tends to suggest that it depends on what you are trying to achieve:- an FPGA might well run a counter at an *internal* clock speed of 100MHz, for example, whilst it takes 100ns for an input signal to propagate through several levels of logic to an output pin. As an example, a few years ago I worked with Actel FPGAs. The quoted speed for a 1010 device was quite high for counters etc., but we had problems getting a zero wait-state DRAM controller working with a 16MHz 68302 - the problem being the timing requirement between a clock edge input and a signal output (e.g. /RAS and /CAS generation). This also changed at each design change/re-compilation as the actual delays in FPGAs are very dependent on logic block placement and routing. Had we simply needed a counter to run at high speed, with input-to-output delays unimportant, then we'd have been OK - as is the case in some applications. In short - it depends on your application, and always relate quoted figures to this or you could get caught out! -- Regards AndyGArticle: 3713
In article <31ED2CD4.4D39@drao.nrc.ca>, Tom Burgess <tburgess@drao.nrc.ca> writes: >Steve Casselman wrote: >> ...<deleted> - my news reader enforces short quotes >> ... >> All in all I believe the 6200 brings a significant number of new and exciting >> features to FPGAs and really starts to take reconfigurable computing to >> new frontiers. >> > >VERRY interesting - I HAD casually dismissed the 6200 as Yet Another >Revolutionary Fine-grained FPGA Family (YARFFF), but as you point out, >the open architecture makes a BIG difference. The prelim. data sheet, by >the way, is available on Xilinx's web site. Sort of reminiscent of the >Concurrent Logic 6000 parts. Did Xilinx buy them out? > > Thanks for the info - tom Not Concurrent, its the new and improved Algotronix you see before you. Xilinx bought them out in 92, and this is the first product from that group. rich -- ************************************************************************** Richard Wieler wieler@cmc.ca email Computer Engineer (VLSI) - TS (613)530-4673 phone Canadian Microelectronics Corporation (613)548-8104 fax Kingston, Ontario Canada ***************************************************************************Article: 3714
---------- Forwarded message ---------- Date: Fri, 19 Jul 1996 11:58:04 GMT From: Udi Finkelstein <fink@post.tau.ac.il> To: Rainer Scharnow <amigo@bintec.de> Subject: Re: Atmel EEPROMs 17C65: again On Mon, 15 Jul 1996 08:42:51 +0200, in comp.arch.fpga you wrote: >Hi all, > >today I got the AT17Cxxx upgrade for our programmer. The problem: I >cannot program the RESET polarity of the EEPROM to active low. I like to >know if this is a bug in the upgrade or in the 17C65. Is there anybody >who can check this at a 17C65 with a Datecode of 9605 (last line on the >PROM print) or earlier? I have programmed the RESET polarity of 17C65's with earlier date codes. I'm not sure I have newer chips (I have some 20-30 new SOIC 17C65's. I can check their date code). Also, please note that 17C65's cannot be cascaded, since their CEO pulse is generated after 132072 clcoks, and not 65536. I found out this when building a home made programmer for 17C65's, and this was verified by Atmel's FAE.Article: 3715
Warning to anyone using/considering Lattice ispLSI devices. Many good points, but the data book absolute max Vcc rating of 7.0V has to be taken very seriously. Overvolts of a few microseconds destroy the complete device. I know virtually all 5V logic ICs are rated 7V max, but many survive rail glitches without even glitching their outputs. Specific scenarios were prototype and development systems with plug-in wiring - bare-end Vcc/Gnd short in this situation has bounce which easily hits 8.5V, worse in some circumstances. Fix was to fit 1N5908. Note most "transient suppressors" have their knee around 6.8V, so they don't clamp hard until almost 10V. Large tantalum as bulk decoupler also helped. Note views expressed are personal. Tim Forcer Dept of Electronics & Computer Science University of Southampton email: tmf@ecs.soton.ac.ukArticle: 3716
I am using Xilinx XC4000 FPGAs for my design that has few increment and decrement by one and data bus is 8-bit integers. I was wondering whether there is any design that uses less resources of FPGA than 8-bit adder/subtractors to increment an 8-bit number by one. If there is such a method would anybody tell me what VHDL code infers this hardware? HamidArticle: 3717
Dear Friends, one thing has been confusing me for a long time. That is: based on what condition is the timing report from VHDL synthesizer generated? Every FPGA vendor has chips with different speed grades, but I have not seen a VHDL synthesizer, including Exemplar and Synopsys, offers user a synthesis option to specify the speed grade of the target device family. Also the reported delay can hardly predict the result of place/route tools, which introduce the net delay etc when we choose a particular package/member of the target family. So, could anyone of you tell me what exactly the timing report from VHDL synthesizer is for? Many thanks, Felix K.C. CHEN -- --------------------------------- Felix, Kuan-chih CHEN (³¯ «a §Ó) Associate Project Manager System Product Division D-Link Co., Hsin-chu, Taiwan Email: flxchen@diig.dlink.com.tw Machines and tools are only as good as the people who use it. ---------------------------------Article: 3718
S.J.B.Acock (sjba@ukc.ac.uk) wrote: : : I would be interested to hear from anyone who has interfaced a Xilinx 4000 : FPGA with a static RAM chip. My problem lies with creating bidirectional : tri-state buffers in the FPGA to access the RAM data bus. I am creating : designs using behavioural VHDL and the Synopsys Design Analyzer to create : a Xilinx netlist. : I have designed a bidirectional bus like this and it works in a XC4013. --------------------- | enable____ | | | OBUFT | inout Bus | out bus---|>----|--------<-> BPAD | | | | in bus----<|----| | | IBUF | | | --------------------- -RaghuArticle: 3719
Does anybody have any information on Actel? I am doing research on the company and was wondering what anybody thought about the company, its products, its service, anything. I would really appreciate it. Thanks. Nadeem SarwarArticle: 3720
In article <31edf313.36832759@news.dial.pipex.com> ft63@dial.pipex.com (Peter) writes: >Can you implement a state-machine-driven ripple (or bubble?) sort? The >one which just keeps exchanging consecutive pairs of items (until a >pass has been made on which nothing had to be exchanged) should be >quite simple to do... If you're seriously hardware-rich, there are sorting algorithms which use a sequence of compare/swap operations (compare two items, swap if in the wrong order) which is not data-dependent -- they always compare the same elements in the same order, so compare-and-swap devices could be hardwired to the wires/cells holding the items. Considerable parallelism would be available. See the section "Networks for Sorting" in Knuth volume 3. I'm not sure how relevant this is to the immediate problem, but it might be of help to others. (In case the hardware folks don't recognize that reference, it's to vol. 3, "Sorting and Searching", of Donald Knuth's "The Art of Computer Programming", a standard computer-science reference on algorithm design.) -- ...the truly fundamental discoveries seldom | Henry Spencer occur where we have decided to look. --B. Forman | henry@zoo.toronto.eduArticle: 3721
Let the log show that Felix K.C. CHEN wrote: >Every FPGA vendor has chips with different speed grades, >but I have not seen a VHDL synthesizer, including Exemplar >and Synopsys, offers user a synthesis option to specify >the speed grade of the target device family. That is what the set_operating_conditions command is for. You can specify a model for the physical conditions present in the chip. LSI's cell families come with several. >Also the reported delay can hardly predict the result of >place/route tools, which introduce the net delay etc when >we choose a particular package/member of the target family. Of course not. This is a model, remember. The wire load models make at least a beginning at predicting this, but you should expect more delays once the chip is actually laid out. I usually shave a few nanoseconds off the clock period to account for this. You can back-annotate layout data to Synopsys and improve these models. >So, could anyone of you tell me what exactly the >timing report from VHDL synthesizer is for? It gives you an idea of what your paths will look like using the *models* that you have provided. It will tell you whether you are close to the edge of your timing, or if you are sitting pretty. It can often alert you to timing problems you might not have seen while designing. (those sneaky asynchronous paths through a hierarchy level) It is a first approximation of the final timing, but I have found it to be a reasonably accutrate first approximation. --- cheebie@smart.net The Mighty Cheebie: loyal drone in the service of Da Queen Eater of Oreos, wearer of wing weaves, maker of pillows.Article: 3722
This is meant to clarify what I meant when I first posted a message here. I was wondering if anyone knew anything about Actel's products, how they functioned, how their service was, and anything about the company you generally liked or disliked. Thank you for your assistance. Nadeem SarwarArticle: 3723
On 11 Jul 1996, GAMRAT Christian wrote: > Is There anybody out there who knows anything new about the Xilinx XC6200 > partially reconfigurable fpga ? depends what you mean by new? i don't think there's any more information available yet, preliminary timing details that i'm probably not allowed to disclose even if i had the timing diagram where i could find it ;-) > The data available from Xilinx has not changed for months and it looks like if they > are not pushing the device ahead anymore. no. this device is definitely still going ahead. i'm not sure what the shipping info is. you might want to contact Raj Patel at xilinx (something like raj.patel@xilinx.com) if you're interested in using these parts. he's the head-6200-marketing-honcho. > I hope I'm wrong because this FPGA is a must in the field of reconfigurable > computing. It will be really Dommage ! i think it may make something of a splash in the reconfigurable world when it finally ships in quantity. xilinx seem to be getting behind the reconfigurable computing world of late. certainly their rather dominant presence at FCCM this year was an indication of this, along with the rather nice black "Xilinx reconfigurable computing" shirts they were giving out ;-) more later, :-j -- Jonathan AH Hogg, Computing Science, The University, Glasgow G12 8RZ, Scotland. jonathan@dcs.gla.ac.uk http://www.dcs.gla.ac.uk/~jonathan (+44)141 3398855x2069Article: 3724
Tim Forcer wrote: > > Warning to anyone using/considering Lattice ispLSI devices. > > Many good points, but the data book absolute max Vcc rating of 7.0V > has to be taken very seriously. [cut] ...which is why it's called an 'absolute max.'!! Some chips will be more tolerant than others, but by and large it's a good idea to beleive the data book :-) -- Regards AndyG
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