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How about trying a simple test. Keep adding 8 or 16-bit binary counters until the thing won't place or route. I realize this may be a little time-consuming, but it should give you accurate real-world numbers. If you don't like adding binary counters because they are very much unlike the logic you might want to add, use something else like LFSRs or decoders or whatever. Binary counters are convenient because they use both function generators and CLB flip flops, come in a variety of sizes, and can be placed and connected (and removed) quickly. Lance Gin <c43lyg@dso.hac.com> wrote in article <32A0FA6A.595@dso.hac.com>... > I've just finished a Xilinx 4025E design that PPR required 99% CLB's to > place/route. Utilization of CLB resources is a bit on the high side > (80%+ FG's, 50%+ DFF's). I've looked at the placed design with FPLAN > and PPR appears to have done an OK job given the speed requirements. > There are, however, many CLB's where only a few internal resources are > used. There are also many split nets (nets routed through CLB's) reported. > > I'd like to make an informed assessment of how much more logic I can > *ADD* to the design. So far, I've got the following to work with: <snip> > Does anyone have any suggestions on other data I can use ? > How would you go about making such an assessment ?Article: 4701
In article <slrn59oha5.8ns.dietrich@krusty.htc.honeywell.com>, dietrich@krusty.htc.honeywell.com (Paul Dietrich) writes: |> On 26 Nov 1996 23:49:57 GMT, Hari Vattikota <hari@syzygy.xilinx.com> |> wrote: |> > |> >In article <32998FFF.1466@martis.fi>, Mark Sandstrom |> ><Mark.Sandstrom@martis.fi> writes: |> >|> Has anyone managed to utilize Xilinx 4000e IOB FFs through |> Synopsys? |> > |> >Please avoid global reset on the I/O flip-flops you want to infer |> |> Why should global set/reset be avoided? The 4000e supports GSR in |> IOB |> flip-flops. I've used GSR in my designs and the flip-flops get |> merged into |> IOBs. It's true that the IOB flip-flops don't have another reset |> besides |> GSR. IOB flip-flops (in 4kE) don't have asynchronous reset. Synopsys will synthesize flip-flops with asynchronous reset which get placed in the CLBsArticle: 4702
Now that you have the answer to the MINIMUM number of pins to address
any amount of memory, maybe you can convince your boss that he
really wants something like a range of solutions for a range of
memory sizes and a range of numbers of pins. For example,
can use 8-pins to address 2**72 bytes by using 8-pins 9 times
can use 32 pins to address 2**96 bytes by using 32 pins 3 times
...
--
John Ahlstrom jahlstrom@cisco.com
408-526-6025 Using Java to Decrease Entropy
Any neural system sufficiently complex to generate the axioms
of arithmetic is too complex to be understood by itself.
Kaekel's Conjecture
Michael Quinlan (mikeq@primenet.com) wrote:
: TukryopKim <acsapark@public.bta.net.cn> wrote:
: >Hi,
: >I am having duty of to make a algorithm which is able to access the
: >abundant memory with minimum address pin lines. Perhaps that memory has
: >about several Tera bytes capacity. Ofcouse this is a hypothesis. But my
: >boss require me it.
: >Probably it could be carried out with only new mathematical approach.
: >With group theory?
: If you know in advance how much memory you can have, you should be able =
: to
: address it with a single pin by sending the address serially instead of =
: in
: parallel. If you don't know how much memory you have, you might have to =
: use
: something like a stop bit (a signal 1.5 or 2 times the length of your
: normal signal) to mark the end of the address.
: -------------------------------------
: Michael A. Quinlan
: mikeq@primenet.com
: http://www.primenet.com/~mikeq
: "If it doesn't fit, you must acquit!"
: -------------------------------------
Article: 4703Hi I'm using Xilinx 5.1 version with Viewlogic as my schematic editor. I am designing neural networks and implementing them on a XC4013 FPGA. However I am having trouble with memory requirements. When I go and run XMAKE on my schematic, I get an error during the X-BLOX routine stating that X-BLOX cannot process the design due to Error 20244: Out of memory I have about 600K of conventional memory available and 24M of RAM. Is this not enough??Article: 4704
This is a multi-part message in MIME format. ---------------------------------987992337016 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii Setanta ED runs under Windows 3.x/Windows 95 and Windows NT. It will run un WABI on Unix boxes. Regards, John ---------------------------------987992337016 Content-Transfer-Encoding: 7bit Content-Type: text/plainArticle: 4705
Call For Papers
3rd International Workshop on Applications of the
Reed-Muller Expansion in Circuit Design
(Reed-Muller 97)
In Cooperation with IFIP WG 10.5.
Place: Oxford University, Oxford, UK.
Date: September 19-20, 1997
just after ESSCIRC 97 (European Solid-State Circuits Conference)
Southampton, UK, September 16-18 .
just before EuroDAC 97 (European Design Automation Conference)
Dusseldorf, Germany, September 22-26 .
This workshop focuses on the application of new techniques in the
representation and realization of discrete functions. AND-EXOR based
representations are often simpler than AND-OR based representations,
and have other important properties. Decision diagrams are being
extensively studied, and have offered powerful new techniques for
verification and synthesis. The goal of the workshop is to bring
together researchers in these and related fields to discuss new
approaches and results. The first workshop was held in September 1993,
in Hamburg, and the second in August 1995, in Tokyo.
A non restrictive list of interest includes the following topics:
* Graph-based representation of logic functions
Binary decision diagrams, Functional decision diagrams etc.
* EXOR-based logic synthesis
Reed-Muller expressions, Kronecker expressions,
Exclusive-OR Sum-of-Products Expressions (ESOPs),
Multi-level circuits
* Spectral techniques
* New representations for discrete functions
* Complexity theory
AND-OR vs. AND-EXOR
* Easily testable circuits using EXORs
* Implementation in silicon (FPLDs, FPGAs,...)
* Applications, both inside and outside circuit design.
Chairman: Co-Chairman:
Jonathan Saul Udo Kebschull
Oxford University, FZI
UK. Germany.
Authors are invited to submit, by April 4, 1997, 10 copies of draft
papers not exceeding 20 pages, together with a signed statement that
if the paper is accepted the author will present it at the
workshop. Notifications of acceptance will be sent by June 20, 1997. A
workshop handout will be distributed to the workshop attendees, and it
is planned to publish selected papers in a more widely distributed
form. The camera-ready paper must be received by August 1, 1997.
Submissions should be sent to:
Jonathan Saul, Oxford University Computing Laboratory, Wolfson Building,
Parks Road, Oxford OX1 3QD, UK.
or
Udo Kebschull, Forschungszentrum Informatik (FZI),
Haid-und-Neu-str. 10-14, 76131 Karlsruhe, Germany
Enquiries :
Miss Frances Page
Oxford University Computing Laboratory
Wolfson Building
Parks Road
Oxford OX1 3QD, UK.
Tel: +44 1865 283505/273838
Fax: +44 1865 273839
Further details will become available on the website:
http://www.comlab.ox.ac.uk/oucl/users/jon.saul/ReedMuller97.html
Program Committee:
Bernd Becker University of Freiburg, Germany.
Jon T. Butler Naval Postgraduate School, USA.
Olivier Coudert Synopsys, USA.
Rolf Drechsler University of Freiburg, Germany.
Masahiro Fujita Fujitsu Laboratories of America, USA.
Kiyoshi Furuya Chuo University, Japan.
Udo Kebschull Forschungszentrum Informatik (FZI), Germany.
Tomasz Kozlowski University of Zielona Gora, Poland.
GueeSang Lee Chonnam National University, Korea.
Margaret Marek-Sadowska University of California, Santa Barbara, USA.
Christoph Meinel University Trier, Germany.
Michael Miller University of Victoria, Canada.
Shin-Ichi Minato NTT LSI Laboratories, Japan.
Marek A. Perkowski Portland State University, USA.
Tsutomu Sasao Kyushu Institute of Technology, Japan.
Jonathan Saul University of Oxford, UK.
Endric Schubert Exemplar Logic, USA.
Article: 4706Steve Wiseman wrote: > what synthesis tools are you using? I'm using ACTIVE CAD 2.2 and Xilinx Foundation Series Version 6.0.1 . Good luck ! Shelby CongArticle: 4707
Hans Tiggeler wrote: > > Can anybody tell me if there is a low-cost programmer for Cypress CPLD and > pASIC380 family? > > Their VHDL synthesis software is amazingly cheap (32 Pounds for Warp2 > Version4.0 + VHDL synthesis book). The Cypress databook describes the Impulse > 3 programmer which is based on an OEM version of the DATA I/O ChipLab > programmer. Those of you who know this programmer also know is far from > low-cost. > Even the software is cheap , but the device can be written only time . Maybe Lattice's device is better , because their software(not VHDL) is cheap and needn't a speical programmer . CongArticle: 4708
Joe Blake wrote: > > Hi > I'm using Xilinx 5.1 version with Viewlogic as my schematic editor. I am > Error 20244: Out of memory > > I have about 600K of conventional memory available and 24M of RAM. Is this > not enough?? I ran into problems with 32Meg on a full 4013 design as well as a 4025e. I upgraded to 64Meg and a lot of "interesting" problems just disappeared. Dave Thibault Speaking for myself (of course).Article: 4709
simonson@skopen.dseg.ti.com (Kevin M Simonson) writes:
> I'm feeling really ignorant right now. Is there anyone who can tell
>me what ASIC stands for? Thanks.
>
> ---Kevin Simonson
Aren't "ASICs" a brand of tennis shoe? :^)
(It could also stand for "Application Specific Integrated Circuit",
too, I think!)
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4599 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 4710
It appears that discussion on this thread has died out, but I'll add my two
cents worth. The problem here is another classic case of mononumerousis,
that dreaded disease most common to marketing and management. Device
capacity is a complex quantity of several dimensions and cannot possibly
be expected to be adequately described by a single number. This has been
true since PLDs were first invented, when device architectures were fairly
simple and regular, before the myriad of special functions and architectural
enhancements. This has only added additional dimensions to an already very
complex problem. The best one can hope for when taking a simplistic approach
to determining device capacity is to derive some statistical measures and
to determine reasonable practical limits. And vendors are beginning to do
this. At least one is even openly describing the assumptions and equations
used to obtain the "nominal" device capacity ratings and ranges for
practical applications. This is definitely a step in the right direction.
It is important for the designer to realize what these numbers mean and
how to use them. One way is consider them in a somewaht analogous fashion
to component power ratings. A good designer will de-rate them in order to
achive better reliability. The principle hold here as well, but the derating
factor isa bit larger....
************************************************************************
******* *********
******* ************* John Vincent
****** **************** Eastman Kodak Company
***** ******************* Equipment & Software Platform Center
**** ********************** Digital Technology Center
*** ************************ Elmgrove Plant Bldg. 1
**** ********************** Rochester New York 14653-5211
***** ******************* Phone: 716-726-4607
****** **************** Fax: 716-726-7131
******* ************* email: vincent@kodak.com
******* *********
************************************************************************
=======================================================================
Anything I say may or may not be my opinion, but certainly is not
the opinion of my kind and generous Internet-enabling employer.
(How's that sound, boss?)
=====================================================================
Article: 4711Volt Services Group currently has an contract opening to work in the Los Angeles area for a VHDL engineer. Tasks include FPGA Design, Verify Xilinx 4000, Board level debuf and verification Tools: Design architecture, Quicksim, X Delay. Rate to $75/hr DOE Position is in LA and must be done onsite! Length: Approx 2 months. Contact: Jason J. Tayles Volt Regional E-mail: voltj@ix.netcom.com www.volt-tech.com V:800.422.8777 V 602.955.8717 (outside US) F 602.955.8536Article: 4712
In article <E1y6pA.Bv6@nonexistent.com> kardos@mail.matav.hu writes: > Hi! > > Have anybody ever heard of a circuit named 74hc0324 or 74hco324 ? Or does anybody know, >where to search for it ? (AltaVista couldn't find it.) > Please answer in e-mail too ! Thanks for any hint. > >***************************** >Botond Kardos >kardos@mail.matav.hu Yes, I know what this chip is. It is the control chip inside a software security block (dongle), right next to a 93C46K ( a serial EEPROM), and an HC00 (quad CMOS nand gate). There are also 17 surface mount resistors, 7 capacitors, and 4 diodes near by. I hope you aren't trying to crack it.Article: 4713
The latest Xilinx XCELL Newsletter has an article on running
XACT under Windows NT. You can find the Acrobat file at
http://www.xilinx.com/xcell/xl23/xl23_20.pdf
The article references the following patch files available
from our BBS or FTP site:
ftp://ftp.xilinx.com/pub/swhelp/xact-pc/prep_nt.zip
ftp://ftp.xilinx.com/pub/swhelp/xact-pc/rainport.exe
The complete table of contents for the latest XCELL is at
http://www.xilinx.com/xcell/xcell23.htm
******************************************************
Marc Baker marc.baker@xilinx.com
Competitive Marketing and Applications
Phone: (408) 879-5375 Fax: (408) 879-4676
Xilinx, Inc.
2100 Logic Drive
http://www.xilinx.com
San Jose, CA 95124
******************************************************
Article: 4714
Dear colleague,
It is our pleasure to announce the public availability of POLIS-v0.2
co-design environment for control-dominated embedded systems.
POLIS offers an integrated interactive environment for specification,
co-simulation, formal verification, and synthesis of embedded systems
implemented as a mix of hardware and software components.
Version 0.2 offer many add features, including brand new microcontroller
resource library handling and ptolemy simulation debugging. Please see
REL_NOTES for more detail.
Most of the information about POLIS, including pointers to source and
object code (for various CPUs and OSes) is available at our WEB site
http://www-cad.eecs.berkeley.edu/Respep/Research/hsc/abstract.html
The software is available under the usual copyright rules of the
University of California
(see also http://www-cad.eecs.berkeley.edu:80/copyright.html).
If you are interested, but do not have WEB access, please contact us via
e-mail at polis-questions@ic.eecs.berkeley.edu.
Best regards,
the POLIS team
(currently including Felice Balarin, Massimiliano Chiodo, Alberto
Ferrari, Paolo Giusto, Harry Hsieh, Attila Jurecska, Marcello Lajolo,
Luciano Lavagno, Claudio Passerone, Claudio Sansoe', Ellen Sentovich,
Marco Sgroi, Kei Suzuki, Bassam Tabbara, Reinhard von Hanxleden, and
Alberto Sangiovanni-Vincentelli)
Article: 4715kardos@mail.matav.hu wrote: : Hi! : Have anybody ever heard of a circuit named 74hc0324 or 74hco324 ? Or does anybody know, : where to search for it ? (AltaVista couldn't find it.) : Please answer in e-mail too ! Thanks for any hint. Soooooo!! Trying to duplicate a hardware copyright protection key are we??? As I understand it the chip is a custom device (full name: 74HC032AM). Bob.Article: 4716
Hi! Have anybody ever heard of a circuit named 74hc0324 or 74hco324 ? Or does anybody know, where to search for it ? (AltaVista couldn't find it.) Please answer in e-mail too ! Thanks for any hint. ***************************** Botond Kardos kardos@mail.matav.huArticle: 4717
fliptron@netcom.com (Philip Freidin) wrote:
>In article <E1y6pA.Bv6@nonexistent.com> kardos@mail.matav.hu writes:
>> Hi!
>>
>> Have anybody ever heard of a circuit named 74hc0324 or 74hco324 ? Or does anybody know,
>>where to search for it ? (AltaVista couldn't find it.)
>> Please answer in e-mail too ! Thanks for any hint.
>
>Yes, I know what this chip is. It is the control chip inside a software
>security block (dongle), right next to a 93C46K ( a serial EEPROM), and an
>HC00 (quad CMOS nand gate). There are also 17 surface mount resistors, 7
>capacitors, and 4 diodes near by. I hope you aren't trying to crack it.
>
Hacking aside, is that chip a custom part for that specific dongle,
or a merchant part produced for general sale? If the latter, it might
have wider application than just security blocks.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or servers
"From" line rigged to foil spambots: daveb <at> iinet.net.au
Article: 4718joe@iscm.ulst.ac.uk (Joe Blake) wrote: >Hi >I'm using Xilinx 5.1 version with Viewlogic as my schematic editor. I am >designing neural networks and implementing them on a XC4013 FPGA. However I >am having trouble with memory requirements. When I go and run XMAKE on my >schematic, I get an error during the X-BLOX routine stating that X-BLOX >cannot process the design due to > Error 20244: Out of memory > >I have about 600K of conventional memory available and 24M of RAM. Is this >not enough?? Not if you are using any significant portion of the chip's resources. Even for the 4010, you should have 32 MBytes. (I used 24 MB for some designs, but some REQUIRED more memory--even with no XBLOX modules.) Jason T. WrightArticle: 4719
Dear Friends, I read the terminology "token chain" in an article, but I do not know waht it is? That article is about the FIFO control mechanism. Could anyone give me a reference or explanation? Best wishes, Felix K.C. CHENArticle: 4720
Hi.
I'm using FPGAs.
In a FPGA, I want to use OR gated clock to flipflop.
For And gated clock, I convert this to enable flip-flop to remove glitch.
But, I can not find Or gated clock conversion which is glitch free.
Is thee anybody knows glitch free OR gated clock usage?
Thanks.
============================================================
Jae-Ho Shin MJL Korea,Ltd
Section Chief/FAE 19th Fl. Korea Investment Trust
Bldg.
Field Application Engineering 27-1 Youido-Dong, Yungdeungpo-Ku
Section 2 Seoul, Korea 150-010
Electronic Component Tel: +82(2)767-2292, -2200, Fax-2221
Business Department Email: jhshin@mjl.co.kr
http://www.mjl.co.kr
============================================================
Article: 4721Hi everyone: Just wondering if anyone out there has first hand experience or cares to comment on the use of ASICs and FPGAs in safety critical applications such as in passanger airplanes. Are the FPGAs more prone to failure by their virtue of being "programmable" and because they have unused dangling gates on the silicon? Any one used any particular FPGAs on FAA certified equipment? Regards, Kayvon Irani Los Angeles, caArticle: 4722
Does anyone know what this chip is??? @M <-- Motorola Logo SC419510FU F66Y HLKH9518 This chip is inside a Sony Playstation memory cartridge next to a AT29LV010 eeprom. thanksArticle: 4723
Marc Baker wrote: > > The latest Xilinx XCELL Newsletter has an article on running > XACT under Windows NT. You can find the Acrobat file at > http://www.xilinx.com/xcell/xl23/xl23_20.pdf > > The article references the following patch files available > from our BBS or FTP site: > > ftp://ftp.xilinx.com/pub/swhelp/xact-pc/prep_nt.zip > ftp://ftp.xilinx.com/pub/swhelp/xact-pc/rainport.exe That's where I started and it doesn't work (under 3.51 or 4.0). The only solution that worked for me was to get a 2nd PC and load Win3.1 on it. The solution for my colleague was Actel :( Regards, ScottArticle: 4724
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If you have Netscape 3.0, and want to take the news group option, follow
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