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Last time I looked AMD and Lattice were making "zero power" 16V8s. But there will be more now. >Hi. >I'm looking for a small PLD (preferably with 16V8 fusemap) >which will operate over this supply range. Speed could >be anyhing. 35ns would be fine. > >Does anyone make such a device ? > >The power comes from a battery-backed (3.6VNiMh) supply, >which is 5V when the box is powered up, and 3.6-4.3V >when running off the battery. > >A 4.8V NiCad/NiMh battery would be rather inconvenient: >e.g. need to supply 6V for charging. >-- >John Vickers Tel: +44 1223 560129 >Hardware / Software Person Fax: +44 1223 563698 >The Magic Board Company john@rhizik.demon.co.ukArticle: 4326
Thomas Kobler wrote: > > Hello! > > I would like to ask if anybody had success in using the Xilinx > xchecker cable and xchecker.exe V5.1 od V5.2 under Windows > NT3.51 to download a LCA? > > To me it keeps crashing or it ignoring the download cable almost > every time. > > Any hints? I just read the XCELL Issue 22 page 32: Running XACTstep and Alternate Operating Systems. It's all about XACTstep 6.0.1 and 5.2.1 on Windows 95, NT and Solaris. See also: http://www.xilinx.com/xcell/xcell22.htm or http://www.xilinx.com/xcell/xl22/xl22_32.pdf Hope this helps. -- ------------------------------------------------------------------------ | Rene Bakker | FOM Institute for Atomic and Molecular Physics | | Digital engineer | Electronica & Informatica | | | Kruislaan 407 | | | 1098 SJ Amsterdam | | | The Netherlands | | | | | | Tel: +31-(0)20-6081234 | | | Fax: +31-(0)20-6684106 | | | E-mail: rbakker@amolf.nl | ------------------------------------------------------------------------Article: 4327
> Hello,
> I have designed a Reed-Solomon Decoder for a space tape recorder
that was implimented with FPGA's. Since we could only use radiation
hardened FPGA's, the decoder was placed into 3 Actel 1280's, 1 2k RAM,
and 1 2k ROM. I'm sure it would fit into a single chip Altera or
Xilinx
which contains RAM. The design is 2 years old and has been space
qualified. The Reed-Solomon encoder was on another board and easily
goes
into a Actel 1020.
I have also designed many other Reed-Solomon encoders all
targeted for FPGA's but of differenct number of checkbytes.
Joe Keith
(603) 885-5949
x0033$_AT_NCALAN1@MAILGW.SANDERS.LOCKHEED.Com
Article: 4328
The Plenary Session of the first fully online engineering conference is now open.
“Engineering Challenges: Just Around the Corner”
Join the WinEDA ‘96 Plenary session at www.wedasite.com. Read the presentations and join the online Q&A with three experts in
communications, workstations and platforms. WinEDA is sponsored by EE Times and a host of EDA tool vendors.
The presentations are:
“The Impact of Communications on Computing”
Mark Melliar-Smith
Executive Director, Integrated Circuits Div.,
Chief Technical Officer, Microelectronics,
Lucent Technologies
“Trends in Computer Systems Design”
Paul Bemis,
Marketing manager for technical servers,
Workstation Systems Div.,
Hewlett-Packard Co.
“Windows NT: The New Foundation for EDA Applications”
Daniel Small,
Technology Evangelist
Microsoft Corp.
The Plenary Session is now active, but will remain so only for another week.
best regards,
Stan Baker
Program Chairman,
WinEDA’96
*****************************************
SBAssociates
ph. 408-356-5119 fx. 408-356-9018
Stan Baker = sbaker@best.com
Debbie Peel = reconfig@best.com
Kathy Rogers = sba2@best.com
web sites:
www.pldsite.com - www.reconfig.com
****************************************
Article: 4329
Five sessions are now open and interactive in the WinEDA Online Engineering Conference And Exhibit. Join them at
www.wedasite.com.
Register (free) for the conference and you can post messages in the conference sessions.
You can lurk and read the presentations if you don’t register -- still free.
WinEDA is now open and will be active through the end of November, allowing you plenty of time to follow the presentations, Q&As
and get in your own comments.
The sessions are:
1. “Windows, Interoperability, Building the EDA Environment”
2. “Using HDLs for Programmable Logic -- for ASIC Designers (and others)”
3. “PCB and MCM Design -- Will PCB designers cease to exist?”
4. “Intellectual Property -- Reusing Cores and Macros”
5. Plenary Session, “Engineering Challenges: Just Around the Corner”,
with invited presentations, by Lucent Technologies, H-P and Microsoft.
best regards,
Stan Baker
Program Chairman,
WinEDA’96
*****************************************
SBAssociates
ph. 408-356-5119 fx. 408-356-9018
Stan Baker = sbaker@best.com
Debbie Peel = reconfig@best.com
Kathy Rogers = sba2@best.com
web sites:
www.pldsite.com - www.reconfig.com
****************************************
Article: 4330I want to use a FPGA to replace some PAL chips, and a PCI controller if I can. I heard that there are some PCI-compliant FPGAs. What does the "PCI-compliant" mean? Does it mean there are already some PCI controlling part integreted in it? Shawn Lee lxd@cpre1.ee.iastate.edu lxd@iastate.eduArticle: 4331
Hi, does someone has experience with XC4000 and 2 different clocks ? Both clocks are external. The first one runs at X Mhz and the other at X/2 MHZ. What would be the best way to synchronize them ? (There are also two external FIFO's running at the X/2 Mhz) Should I use a 2*X Mhz clock, dividing it by 2 and 4 and loading it through two BUFGP's ? Thanks in advance ! Kim -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 4332
There are three levels of PCI compliance. The first is electrical, ie. capacitance, second is timing, ie. setup and hold, and third is cycle to cycle protocol timing. For an FPGA, the chip determines the first and most of the second. The third is determined by the design. I have used the Xilinx 4xxxE series very successfully in both target only and target/master implementations. Xilinx has quite a lot of app notes on PCI. I developed my own PCI design, and did not use theirs, although theirs is not bad. Be aware that some vendors claim PCI compliance, but they do not have the internal resources to implement a decent size design, or do not really make the timing. 33mhz is really not all that easy in something as complicated as a PCI interface, but it can be done with carefull design and floorplanning. Austin Franklin darkroom@ix.netcom.com Durham 206 Mac 7200 <du206-7200@iastate.edu> wrote in article <32653DB7.6EA0@iastate.edu>... > I want to use a FPGA to replace some PAL chips, and a PCI controller > if I can. I heard that there are some PCI-compliant FPGAs. What does > the "PCI-compliant" mean? Does it mean there are already some PCI > controlling part integreted in it? > > Shawn Lee > lxd@cpre1.ee.iastate.edu > lxd@iastate.edu >Article: 4333
There are three levels of PCI compliance. The first is electrical, ie. capacitance, second is timing, ie. setup and hold, and third is cycle to cycle protocol timing. For an FPGA, the chip determines the first and most of the second. The third is determined by the design. I have used the Xilinx 4xxxE series very successfully in both target only and target/master implementations. Xilinx has quite a lot of app notes on PCI. I developed my own PCI design, and did not use theirs, although theirs is not bad. Be aware that some vendors claim PCI compliance, but they do not have the internal resources to implement a decent size design, or do not really make the timing. 33mhz is really not all that easy in something as complicated as a PCI interface, but it can be done with carefull design and floorplanning. Austin Franklin darkroom@ix.netcom.comArticle: 4334
Dan Bartram wrote: > I thought the AT17C128 serial proms were EEPROMS. At least the ones > I used were. The ones from AT&T are EEPROMs, like the ATT17128F (flash version). I don't know if the name has changed since a part of AT&T now calls itself Lucent Technologies. > > Perhaps I missed the original posts, but I would definitely use the EE > versions during development. > > **************************************************************************** > Dan Bartram, Jr. > Internet: dan.bartram@.gtri.gatech.edu > **************************************************************************** -- ------------------------------------------------------------------------ | Rene Bakker | FOM Institute for Atomic and Molecular Physics | | Digital engineer | Electronica & Informatica | | | Kruislaan 407 | | | 1098 SJ Amsterdam | | | The Netherlands | | | | | | Tel: +31-(0)20-6081234 | | | Fax: +31-(0)20-6684106 | | | E-mail: rbakker@amolf.nl | ------------------------------------------------------------------------Article: 4335
RAINPORT.EXE, mentioned in the XCELL article, is found at: ftp://ftp.xilinx.com/pub/swhelp/xact-pc/rainport.exeArticle: 4336
Rafiki Kim Hofmans wrote: > > Hi, > > does someone has experience with XC4000 and 2 different clocks ? > > Both clocks are external. The first one runs at X Mhz and the other at X/2 > MHZ. > > What would be the best way to synchronize them ? A Phase locked loop. > (There are also two external FIFO's running at the X/2 Mhz) Sounds like you try to synchronize a data signal to a system clock, but the data signal has its own clock (different than the system clock). > Should I use a 2*X Mhz clock, dividing it by 2 and 4 and loading it > through two BUFGP's ? > Depending on your requirements, dividing the clock by 2/4/... is trivial. However, I don't think you'll be able to use BUFGPs from inside the FPGA. You'll have to use the BUFGS. It's all written in the xilinx documentation. Martin.Article: 4337
As with most things, it depends :). The XC4000s have 4 primary and 4 secondary global buffers, all of which are good choices for internal clocks (secondaries have a few nSecs more skew). The secondary global buffers may be sourced by internal logic, and not just the I/O pin, so your devide by two could be generated inside the FPGA. The choice is going to depend on the frequency of the clock and your maximum allowable skew. It should also be noted that the secondary global buffers use global routing resources - I've had designs that would not route when I assigned a signal to a BUFGS because it (the clock) hogged the long lines. If you can provide some more information on frequency and timing requirements I might be able to give a better answer. > does someone has experience with XC4000 and 2 different clocks ? > > Both clocks are external. The first one runs at X Mhz and the other at X/2 > MHZ. > > What would be the best way to synchronize them ? > (There are also two external FIFO's running at the X/2 Mhz) > > Should I use a 2*X Mhz clock, dividing it by 2 and 4 and loading it > through two BUFGP's ?Article: 4338
Rene Bakker rbakker@amolf.nl wrote: > The ones from AT&T are EEPROMs, like the ATT17128F (flash version). > I don't know if the name has changed since a part of AT&T now calls > itself Lucent Technologies. Beware of these (AT&T/Lucent parts): these have a power-up problem that causes them to mis-behave if power comes on "too slowly". I would not buy any of these until Lucent fixes the bug. Note that this is NOT the same as the reset-polarity issue that affects Atmel parts. The Atmel parts are completely usable if you read the directions and have a programmer that will program them properly.Article: 4339
Martin d'Anjou <mdanjou@nortel.ca> wrote: >Rafiki Kim Hofmans wrote: >> >> Hi, >> >> does someone has experience with XC4000 and 2 different clocks ? >> >> Both clocks are external. The first one runs at X Mhz and the other at X/2 >> MHZ. >> >> What would be the best way to synchronize them ? >A Phase locked loop. Were they are already coherent? Are their relative phases fixed? >> (There are also two external FIFO's running at the X/2 Mhz) >Sounds like you try to synchronize a data signal to a system clock, >but the data signal has its own clock (different than the >system clock). > >> Should I use a 2*X Mhz clock, dividing it by 2 and 4 and loading it >> through two BUFGP's ? >> Depending on your requirements, dividing the clock by 2/4/... is >trivial. However, I don't think you'll be able to use BUFGPs from >inside the FPGA. You'll have to use the BUFGS. It's all written >in the xilinx documentation. >Martin. You can definitely use BUFGPs from inside; the cost is the pin (which you should then leave unassigned.) Actually, another cost is the routing to get to the BUFGP (but that is the same for the BUFGS; it's just located in a different spot.) JasonArticle: 4340
I used it with DOS and Windows 3.11 and found V5.1 to be more reliable than 5.2. 5.2 would report a failure to configure the FPGA quite often, while 5.1 has worked perfectly. > I would like to ask if anybody had success in using the Xilinx > xchecker cable and xchecker.exe V5.1 od V5.2 under Windows > NT3.51 to download a LCA? > > To me it keeps crashing or it ignoring the download cable almost > every time.Article: 4341
I've been thinking about using an SRAM based FPGA for bus interfaceing, among other tasks. But I am concerned about what happens on start up. The FPGA has to load it's configration seriallly from an external eprom. What happens to the I/O's durring this time? Are they in a defined state? Simple tri-state would probably do. Random signals would not. ---- "..very sad life. Probably have very sad death. But there's symetry" Remember the home hobbyist computer: Born 1975, died April 29, 1994Article: 4342
I want to use a FPGA to replace some PAL chips, and a PCI controller if I can. I heard that there are some PCI-compliant FPGAs. What does the "PCI-compliant" mean? Does it mean there are already some PCI controlling part integreted in it? Another question: Who knows the actual size of the XC3164A and XC4000E. I can not find them on the web. Shawn Lee lxd@cpre1.ee.iastate.edu lxd@iastate.eduArticle: 4343
I want to use a FPGA to replace some PAL chips, and a PCI controller if I can. I heard that there are some PCI-compliant FPGAs. What does the "PCI-compliant" mean? Does it mean there are already some PCI controlling part integreted in it? Another question: Who knows the actual size of the XC3164A and XC4000E. I can not find them on the web. Shawn Lee lxd@cpre1.ee.iastate.edu lxd@iastate.eduArticle: 4344
Shawn Lee wrote: > > I want to use a FPGA to replace some PAL chips, and a PCI controller > if I can. I heard that there are some PCI-compliant FPGAs. What does > the "PCI-compliant" mean? It means that the device supports PCI drive levels, output delays and input setup/hold requirements. > Does it mean there are already some PCI > controlling part integreted in it? No. > Another question: Who knows the actual size of the XC3164A and XC4000E. > I can not find them on the web. Not sure what you are asking. See: www.xilinx.com Regards, ScottArticle: 4345
Eric Edwards wrote: > > What happens to the I/O's durring this time? Are they in a defined state? Xilinx I/Os become inputs with weak pull-ups during configuration. Atmel I/Os are also inputs during the initial configuration. Subsequent reconfiguration in an Atmel part leaves I/Os in the current configuration if they are not being reconfigured, or changes them to the new configuration if they are (unless you do a reboot configuration, which reverts all I/O to input) -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our web site.Article: 4346
> > You can definitely use BUFGPs from inside; the cost is the pin (which > you should then leave unassigned.) Actually, another cost is the > routing to get to the BUFGP (but that is the same for the BUFGS; it's > just located in a different spot.) > Right. I forgot. Thanks. You loose the pin, not the BUFGP. Martin.Article: 4347
Eric Edwards wrote: > > I've been thinking about using an SRAM based FPGA for bus interfaceing, > among other tasks. But I am concerned about what happens on start up. > The FPGA has to load it's configration seriallly from an external eprom. > What happens to the I/O's durring this time? Are they in a defined state? > Simple tri-state would probably do. Random signals would not. Xilinx FPGAs place their I/O's in tri-state with a weak pullup (about 50Kohms or so) during configuration. I imagine other vendors do the same. Regards, ScottArticle: 4348
Looking for a rough coast estimate, to convert a 3020 fpga to an asic. Quantity would be 10,000. Need a piece price under $2.00, excluding all NRE and setup cost. JimCArticle: 4349
Not all the I/O pins are in tri-state during configuration. There are some special pins, like LDC (Low during configuration), HDC (high during configuration)...etc. You have to choose your pins carefully, either don't use these dual purpose pins for I/O pins, or make sure they are hooked to signals that are safe do that to take the state changes during configuration. Austin Franklin darkroom@ix.netcom.com
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Compare FPGA features and resources
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