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In article <4uth89$e23@lily.redrose.net>, Otto's CAD Auction <otto@ottocad.com> wrote: >Mr. Lewis, > >Otto's sorry that you object to seeing your associates get jobs. Otto >thinks everyone needs one; Otto can't sell them software if they don't >have money. Otto seems to have some sort of psychosis that causes him to speak in the third person about himself. Perhaps he should have this problem looked into... And in case Otto hadn't noticed, this is comp.cad.SYNTHESIS which has NOTHING to do with autoCAD!!! -- ----------------------------------------------------------------------------- --Celia Clause Celia's Verilog/EDA web page: celiac@teleport.com http://www.teleport.com/~celiac/ver_eda.htmlArticle: 3901
there is a product for SGI workstations called the atlightspeed. it has up to 345K programmable gates, and can be re programmed by an application running on the host in 5 mSec. i believe it uses a combination of LUCENT 2C40/2C15/2C10 FPGA's. they claim it can perform an 11x11 convolution of a 64bit RGBA at 720x486 resolution in 130 mSec. are there any cards like this for a PCI bus? do they supply necessary programming utilities? i am interested in using this as sort of replacement for a DSP. it sounds as if you can tune the 'array' to a specific algorithm. if anyone can send me any info on this subject, i would be very grateful. thanks, MTM. ********************************************************************* * Michael T. Mayers - MINDESIGN limited * ********************************************************************* * http://www.mindesign.com * *********************************************************************Article: 3902
I have a question regarding Xilinx bitstreams, specifically regarding
downloading a bitstream in Asynchronous Parallel Mode. Assume the
(serial) bitstream looks like:
11111111 00100000 00111100 10001001 01101111 ... 0111 1111
^ ^
^ first bit sent to device last bit sent to device ^
How do I divide this into bytes for parallel download?
Choice 1: Byte 0 Byte 1
D7 .. D0 D7 .. D0
11111111 00100000 ... (i.e. $FF $20...)
Choice 2: Byte 0 Byte 1
D0 .. D7 D0 .. D7
11111111 00100000 ... (i.e. $FF $04...)
Thanks in advance.
-Steve Gross gross@pa.msu.edu
Article: 3903August 19 -- EDA - An Application Opportunity for Parallel Processing PPC members frequently tell us that they want to hear about application opportunities for Parallel Processing. With that in mind, we invited a few speakers to help us explore EDA during the next several meetings; after that, we'll look at other application areas. EDA (ECAD) involves a number of compute intensive areas - synthesis, place and route, timing analysis, simulation, design rule verification, etc.; we understand that parallelism is not yet extensively used to break the bottlenecks. Dr. Samad Moini of IBM, Manager, RS-6000 EDA application development, will provide an expert's view of the availability of parallel EDA applications and the trends and market forces shaping demand for them. He'll examine what is needed to really deliver performance on machines such as the IBM SP-2 with 1,000 or more processors (message-passing). One of the start-ups nurtured by PPC notes that it sees Samad's presentation as a vehicle from which to abstract opportunities for the Distributed Shared Memory machine that it is developing. The main meeting starts promptly at 7:30PM at Sun Microsystems at 901 San Antonio Road in Palo Alto. This is just off the southbound San Antonio exit of 101. Northbound travelers also exit at San Antonio and take the overpass to the other side of 101. A discussion of member projects currently underway and other issues of interest to entrepreneurs follows immediately thereafter at 9PM. Please be prompt; as usual, we expect a large attendance; don't be left out or left standing. There is a $12 fee for non-members and members will be admitted free. Yearly membership fee is $65. -- B. Mitchell Loebel parallel@netcom.com Director - Strategic Alliances and Partnering 408 732-9869 PARALLEL Processing Connection Mktg. Director Minute-Tape International CorporationArticle: 3904
The PARALLEL Processing Connection is an entrepreneurial association; we mean to assist our members in spawning very successful new businesses involving parallel processing. Our meetings take place on the second Monday of each month at 7:30 PM at Sun Microsystems at 901 South San Antonio Road in Palo Alto, California. Southbound travelers exit 101 at San Antonio; northbound attendees also exit at San Antonio and take the overpass to the other side of 101. There is a $12 visitor fee for non- members and members ($65 per year) are admitted free. Our phone number is (408) 732-9869 for a recorded message about upcoming meetings; recordings are available for those who can't attend - please inquire. Since the PPC was formed in late 1989 many people have sampled it, found it to be very valuable, and even understand what we're up to. Nonetheless, certain questions persist. Now, in our seventh year of operation, perhaps we can and should clarify some of the issues. For example: Q. What is PPC's raison d'etre? A. The PARALLEL Processing Connection is an entrepreneurial organization intent on facilitating the emergence of new businesses. PPC does not become an active member of any such new entities, ie: is not itself a profit center. Q. The issue of 'why' is perhaps the most perplexing. After all, a $65 annual membership fee is essentially free and how can anything be free in 1996? What's the payoff? For whom? A. That's actually the easiest question of all. Those of us who are active members hope to be a part of new companies that get spun off; the payoff is for all of us -- this is an easy win-win! Since nothing else exists to facilitate hands-on entrepreneurship, we decided to put it together ourselves. Q. How can PPC assist its members? A. PPC is a large technically credible organization. We have close to 100 paid members and a large group of less regular visitors; we mail to approximately 400 engineers and scientists (primarily in Silicon Valley). Major companies need to maintain visibility in the community and connection with it; that makes us an important conduit. PPC's strategy is to trade on that value by collaborating with important companies for the benefit of its members. Thus, as an organization, we have been able to obtain donated hardware, software, and training and we've put together a small development lab for hands-on use of members at our Sunnyvale office. Further, we've been able to negotiate discounts on seminars and hardware/software purchases by members. Most important, alliances such as we described give us an inside opportunity to JOINT VENTURE SITUATIONS. Q. As an attendee, what should I do to enhance my opportunities? A. Participate, participate, participate. Many important industry principals and capital people are in our audience looking for the 'movers'! For further information contact: -- B. Mitchell Loebel parallel@netcom.com Director - Strategic Alliances and Partnering 408 732-9869 PARALLEL Processing Connection Mktg. Director Minute-Tape International CorporationArticle: 3905
In article <3214E9DF.59B0@pa.msu.edu> Steve Gross <gross@pa.msu.edu> writes: >I have a question regarding Xilinx bitstreams, specifically regarding >downloading a bitstream in Asynchronous Parallel Mode. Assume the I assume you mean Asynchronous peripheral mode. >(serial) bitstream looks like: > > 11111111 00100000 00111100 10001001 01101111 ... 0111 1111 > ^ ^ > ^ first bit sent to device last bit sent to device ^ > >How do I divide this into bytes for parallel download? > > Choice 1: Byte 0 Byte 1 > D7 .. D0 D7 .. D0 > 11111111 00100000 ... (i.e. $FF $20...) > > Choice 2: Byte 0 Byte 1 > D0 .. D7 D0 .. D7 > 11111111 00100000 ... (i.e. $FF $04...) > >Thanks in advance. > >-Steve Gross gross@pa.msu.edu The start of the program should arrive at the chip as a string of '1's followed by the start code 0,0,1,0 in that order. Just as you have described above. The header (including the start code) also comes out the dout pin. Looking at page 2-41 of the data book, it shows DOUT as transmitting bit 0 first, so the answer is 0xFF, 0x04, your choice #2. I looked real hard in the data book, and other than similar diagrams else where, there does not seem to be a more direct declaration of this. The makebits documentation in volume 2 of the SW reference docs gives no clue, nor the docs for makeprom. The "User Guide and Tutorials" book page 521 shows the answer, in great detail, and confims what I said above. By the way, when your last bit of config does not fall on a byte boundary, pad the byte with '1' bits (appended after the last data bit), follow with an 0xff byte, and make sure you load it. This can be needed, if the done goes high (early done on 3K), around bit 6 or 7 of the byte. You need the extra byte to generate the internal shift clocks to get the chip through the startup sequence. Good luck, PhilipArticle: 3906
Steve Gross wrote: > > I have a question regarding Xilinx bitstreams, specifically regarding > downloading a bitstream in Asynchronous Parallel Mode. Assume the > (serial) bitstream looks like: > > 11111111 00100000 00111100 10001001 01101111 ... 0111 1111 > ^ ^ > ^ first bit sent to device last bit sent to device ^ > > How do I divide this into bytes for parallel download? > > Choice 1: Byte 0 Byte 1 > D7 .. D0 D7 .. D0 > 11111111 00100000 ... (i.e. $FF $20...) > > Choice 2: Byte 0 Byte 1 > D0 .. D7 D0 .. D7 > 11111111 00100000 ... (i.e. $FF $04...) I think Choice 2 is correct, I've seen FF04 at the front of the intel hex files from makebits. You shouldn't have to worry about this as makebits takes care of it for you when it creates the output file (intel hex usually). Beware of a glitch in the makebits too. Xilinx is aware of the problem and claims it's insoluble (nonsense, it's easy for them to fix). Makebits apparently isn't aware of the internal clocking requirements of XC3000 family devices and can produce a bitfile that is one byte too short to correctly configure a device in perhipheral mode (I think this only happens for either done-early, or maybe it's done-late configurations... we'll it's one of those two!). Perhaps another Xilinx veteran out there recall the exact nature of the problem. To Peter Alfke of Xilinx: How about getting someone to add a command line switch (or radio button) to makebits, telling it just how the done bit is configured so it can add the extra "FF" pad byte when needed. If Xilinx had done this years ago there would probably have been hundreds of extra leisure hours available to Xilinx customers around the world (or at least I would have had a few more hours some years back). ;) Regards, ScottArticle: 3907
http://www.ozemail.com.au/~henrik/ I'll design for you on a contrat basis. Regards.Article: 3908
Rafiki Kim Hofmans wrote: > > Hi, > > 1) If I want to simulate my routed design, all the signals connected > immediately to an I/O pad are unknown. How can I assign values to the > 'unknown signals' ? > > 2) when I want to simulate my original design, it seems that the startup > symbol doesn't work properly. > If I assign an attribute "init=s" to a flip-flop, the start value > is always zero. >Kim, We've had the same startup problems. My solution uses FDP type flip flops which are set true when GSR is asserted. Xilinx was no help, they recommended the same thing you tried. I wonder what other "features" lurk in their software? Regards, Mark Garaway mgaraway@deltanet.comArticle: 3909
Rafiki Kim Hofmans (tw38966@vub.ac.be) wrote: : Hi, : 1) If I want to simulate my routed design, all the signals connected : immediately to an I/O pad are unknown. How can I assign values to the : 'unknown signals' ? Well, I finally found out what the problem was. I was always setting the routing effort to it's maximum (4). Somehow XACT wasn't able to route some pins (let's say almost none of them) Decreasing the routing and placement effort to 3, solved the problem. Regards, Rafiki Kim Hofmans -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 3910
I've noticed some interesting behaviour in the XIlinx XACT software I'd like to share with people. I have a design entered using Protel Schematic CAD software which outputs Xilinx .XNF netlists. These netlist files are then run through the XACT 5.1 tools. The design is targeted for an XC3164A-3 part, with about 60% of the CLBs used and a number of small parts of the design with 30ns timing requirements. At one point I had the design placed and routed with all timing requirements met. I then added net names to about 30 signals (all starting with the letter 'X') and placed and routed the design again. This time it routed, but failed to meet the timing specifications. It failed on the next attempt as well. After removing the net names I had previously added, it routed perfecting twice in a row. My suspicion is that the place and route tools work on nets in alphabetical order and changing the nets from the schematic editor net names such as N_____ to X____ changed things enough to throw out the routing. This was confirmed by changing the net names to EX____ which again routed perfectly. The conclusion seems to be that changing net names can positively and negatively affect routing. I'd be interested to hear from anybody who has similar experiences or who on the basis of my observations has experimented and noticed similar phenomena. Yours etc., Erik. PS: Please reply to the newsgroup as I don't have a valid return email address.Article: 3911
I have recently obtained a plug-in card for my PC which contains a XC4013 FPGA. This card was purchased from VCC (Virtual Computer Corporation). I was wondering if anyone out there has a similar card and how they were getting on with it. I am experiencing a few problems with mine, namely downloading a logic function to the FPGA from a software application program. VCC have sent me a demonstration program which was compiled in Microsoft Visual C++. However I only have Borland C and this compiles the demonstration program but does not link it. If anyone out there knows anything about this board or knows anything about the difference between compiling and linking programs in Microsoft Visual C++ and Borland C, would you please get in contact with me. I have a project due in 4 weeks time and I really need to use the XC4013 FPGA. Thanks in advance JoeArticle: 3912
Hallo does anyone know a ftp place for free VHDL models regarding the PCI bus? I like to implement these bus in a FPGA (Actel,Xilinx,..). I know the models from Actel and Xilinx. These are quit expensive. Did anyone design a Host (DSP) to PCI-bus bridge? How could be implemented the burst transfer for such a DSP based PCI system? Best regards, Holger e-mail : Holger.Venus@dlr.deArticle: 3913
Test - please ignoreArticle: 3914
> > To Peter Alfke of Xilinx: > > How about getting someone to add a command line switch (or radio button) > to makebits, telling it just how the done bit is configured so it can > add the extra "FF" pad byte when needed. If Xilinx had done this years > ago there would probably have been hundreds of extra leisure hours > available to Xilinx customers around the world (or at least I would have > had a few more hours some years back). ;) > > Regards, > Scott Well, it looks like I have to respond: In October 1994 ( almost 2 years ago ) I wrote, and Xilinx published, an eight-page application note called "FPGA Configuration Guidelines". It tries to cover all the known configuration issues with chapters like: Protection against data or format errors, Daisy-chain operation, Start-up procedure, Configuration modes, When configuration fails, General debugging hints, Special debugging hints for the different Xilinx families, Potential Length-count problem in parallel or peripheral modes. This app note is now incorporated into the brand-new 1996 data book ( pages 14-25 through 32.) You can, of course, also find it on the web. Here is the text of the next-to-last subject. I think it relates to your question: "Potential Length-Count Problem in Parallel or Peripheral Modes. It is highly desirable that the complete change from configuration to user operation occur as the result of one single byte-wide input. The activation of outputs and DONE, the de-activation of the global reset (set/reset in XC4000), and the progression to the ³finished² state F (see Figure 2) should all occur as a result of one common byte input. Under normal circumstances, the software achieves this by manipulating the length-count value appropriately, taking into account the additional bits between devices, and adjusting for the fact that byte-wide interfaces always leave the last bit sitting in the P-S converter, shifting it out at the beginning of the next byte. These complexities, combined with the many possible daisy-chain arrangements have occasionally led to problems, where the device outputs go active before the last required byte had been received. This can lead to contention on the address outputs or data inputs and might prevent the device from going DONE, or reaching the real end of its configuration sequence. Not reaching this ³finished² state limits the use of readback and boundary scan. A new Makebits option solves this problem: Since XACT 5.0, the default option is ³Length-Count aligned² which adjusts the length-count value such that length-count match occurs during the first bit in the last configuration byte. This assures sufficient CCLK pulses to complete any selected type of start-up sequence. The other option is ³DONE-aligned², which adjusts length count value to make DONE go active at the end of a configuration data byte, which can cause problems in Peripheral mode." End of quote. Peter Alfke, Xilinx ApplicationsArticle: 3915
Peter Alfke wrote: snip > In October 1994 ( almost 2 years ago ) I wrote, and Xilinx published, an > eight-page application note called "FPGA Configuration Guidelines".> snip A new Makebits option solves this problem: > Since XACT 5.0, the default option is 3Length-Count aligned2 which adjusts > the length-count value such that length-count match occurs during the > first bit in the last configuration byte. This assures sufficient CCLK > pulses to complete any selected type of start-up sequence. > The other option is 3DONE-aligned2, which adjusts length count value to > make DONE go active at the end of a configuration data byte, which can > cause problems in Peripheral mode." Peter, Well, I guess you did fix the problem (alas, it was after my struggles were over). Sorry I didn't notice it! Glad to see you are watching the newsgroup like a hawk! :) Cheers, Scott (a pretty darn happy Xilinx user).Article: 3916
Electronics Resource Internet Addresses Needed
for Publisher.
==============================================
To all Electronics Companies, Service Person-
nel, Webmasters & Hobbyists,
I am preparing a book tentatively titled "Sam's
Internet Guide to the Electronics Industry", to
be published by Howard W. Sams & Co. and PROMPT
Publications. The book will contain site add-
resses for electronics resources. Companies,
organizations and individual web creators are
encouraged to fill out a simple FORM at the ad-
dress below.
-----------------------------------------------
http://web.idirect.com/~ifx/book/
-----------------------------------------------
In addition, any electronics related addresses
or resources you run into while surfing please
let me know by filling out said form.
If you lack FORMS capability send an email with
the info below. I am especially interested in
sites offering simple electronics repair data,
service specs and hobbyist help-pages. Other
resources are more than welcome. Top Urls will
be printed in this directory and updated in
future issues.
-------------------------------------------------
Name:
Company Name:
Nature of Business:
Address http:
Other Addresses:
FTP Site:
E-mail Contact:
E-mail Main (info):
Webmaster:
Listserv:
How often is your website updated:
What type of information can be found on your
website or special features:
Has the WWW helped your business:
Comments:
-------------------------------------------------
Send to John Adams -- jadams@idirect.com
If you know of any other Electronics related
links please let me know in an email or a blank
form.
Thank you in advance. John Adams -- Author
John J. Adams | "Forever Learning" |
Author | "Forever Questioning" |
Web Designer | "Forever Creating" |
------------jadams@idirect.com------------
INFINET-FX @ http://web.idirect.com/~ifx/
Article: 3917In article <32116D0C.4504@club-internet.fr>, Jean-Michel Vuillamy <vuillamy@club-internet.fr> wrote: > What about the much-advertised 1995 reconfigurable FPGAs, > and particularly the XC6200 family? Is the latter going to follow the > same path as the antifuse XC8100 FPGA i.e. will it also be dropped? > Here I am again, playing marketeer because nobody else does it: There are no plans whatsoever to drop the XC6200. There is a lot of enthusiasm for the concept of reconfigurable computing in Xilinx. I guess that the only reason for not being mentioned as one of the areas of focus, is the presently tiny economic relevance of this technology and design style. I think that, in time, it will become very important. But it will take time until it becomes a significant business and until it makes it into the annual report. Just my $0.02 worth. Peter Alfke, Xilinx Applications EngineeringArticle: 3918
Advanced Management Systems Ltd. do a 3.5 inch disk containing full details of a simple PCI expansion board for a PC. The disk includes board dimensions and pinouts, how to use and program (cheaply) programmable logic, full equations for a simple PCI interface, and PCI driving windows source software in C++ and assembler. Suitable for students and hobbyists, priced at 20 UK pounds message me for more info. -- Austin O'Hara austin@ohara.demon.co.ukArticle: 3919
The UNIVERSITY OF CALIFORNIA EXTENSION,
BERKELEY presents two short courses in IC
technology
1. "Electrostatic Discharge (ESD) in
Integrated Circuits---Protection Techniques
to Improve Reliability in Integrated
Circuits"
September 30-October 2, 1996
San Francisco Airport. Fee $995
Covers basics of ESD protection; CMOS ESD
input protection; failure modes and
characterization; testing for ESD; tester
models; transmission line pulsing; wafer
level monitor; issues in ESD; device physics;
CMOS output protection; process effects;
internal protection; bipolar/BiCMOS; CDM
phenomena and protection; failure analysis
tools; electrical overstress; device and
ciruit simulations; case studies; failure
examples; open session questions.
Lecturers:
Ajith Amerasekera, Ph.D., Senior Member of
the Technical Staff, Device Design
Laboratory, Semiconductor Process and Device
Center, Texas Instruments
Charvaka Duvvury, Ph.D., Senior Member of the
Technical Staff, Texas Instruments
Gadi Krieger, Ph.D., President of QualiTau,
Inc.
Timothy J. Maloney, Ph.D., Principal
Engineerin, Intel Corporation
Tom Polgreen, Ph.D., Staff Modeling
Engineer, Dallas Semiconductor
---------------------------------------------
2. "Gate Oxide Damage From Plasma
Processing---Understanding, Measuring and
Minimizing Gate Oxide Damage"
October 31-November 1, 1996
San Francisco Airport. Fee: $795
Covers effect of electrical stress on oxides;
plasma currents, voltages and charging;
factors affecting charging damage; topography
dependent charging in uniform plasmas;
charging damage results; charging
measurements; damage reduction and
protection.
Lecturers:
Calvin T. Gabriel, M.S.E.E., Manager of
Plasma Etch and CMP, Technology Development
Group, VLSI Technology, Inc.
James McVittie, Ph.D., Senior Research
Scientist, Stanford University Center for
Integrated Systems.
Krishna C. Saraswat, Ph.D., Professor of
Electrical Engineering, Stanford University
---------------------------------------------
For a brochure describing both courses in
detail, please send your POSTAL ADDRESS or
FAX number to course@garnet.berkeley.edu
Please reference "short courses in IC
technology"
Article: 3920Holger wrote: HV>does anyone know a ftp place for free VHDL models regarding the PCI bus? HV>I like to implement these bus in a FPGA (Actel,Xilinx,..). HV>I know the models from Actel and Xilinx. These are quit expensive. HV>Did anyone design a Host (DSP) to PCI-bus bridge? HV>How could be implemented the burst transfer for such a DSP based PCI HV>system? Try Lucent Technologies - talk to them nicely and you may be surprised. ========================================= Stuart Clubb, Field Applications Engineer Eurodis Bytech Limited Direct Line: (+44) 1256 602578 Facsimile : (+44) 1256 707162 E-mail : STUART_CLUBB@bytech.win-uk.net ========================================= --- * PowerAccess 1.08 What is "Laptop" spelled backwards???Article: 3921
Questions for XILINX members: For education purpose we use WorkView for design input an XACT (PPR) for fitting to the 4000 serie from XILINX. Both run on DOS or Win3.11. Now we change all plattform (Intel and Alpha) to Windows NT (3.51, later in the year 4.0). All tools from ViewLogic are avialable now. Whats happen by XILINX with PPR or XACTstep and WindowsNT ? Please give me hope and time schedules for our staff and students here in old germany. A not well informed Walter Lang -- Dipl.-Ing. Walter Lang University of Siegen Department of Electrical Engineering and Computer Science Hoelderlinstr. 3 D - 57068 Siegen Phone: +49 271 740 3210 FAX: +49 271 740 3344 E-Mail: lang@ti.et-inf.uni-siegen.de WWW: www.ti.et-inf.uni-siegen.deArticle: 3922
Does anyone know where to find in the web the information about Rosmount and its patent? Thanks.Article: 3923
Using a plug in board containing a xc4013 FPGA, I am informed in the user's manual that you can convert a design into a "shx" file using the striphex utility in the Xilinx tool set. I am using Xilinx version 5.1.0 and can't find any striphex utility!!. I made contact with the manufacturer's that make the plug-in board and they told me that they also use Xilinx version 5.1.0. If so, then where is my striphex utility!! or am I missing something!!! Does anyone know about this.Article: 3924
[ Editor's Note: This poll and write-up were done *before* Cadence decided
to go after Cooper & Chyan. (I'm getting engineers writing me trying to
change their responses to my original survey questions *because* of
this new Cadence/CCT lawsuit.) Sorry, the polls are closed! :^) - John ]
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / INDUSTRY GADFLY: "EDA Goes OJ"
_] [_ (published in EE Times as "Trial By Media")
by John Cooley, EE Times Columnist
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
As anyone who followed the O.J. Simpson trial can tell you, we Americans
love "Trial by Media." And the EDA business is no different. Now that
EE Times has covered both sides of the Cadence-Avant! lawsuit in minute
detail, here's what engineers responding to a recent Internet survey said.
Overall, 311 engineers responded: 30 percent used P&R tools directly,
29 percent supported other engineers using P&R tools, and 56 percent
only used related EDA tools like synthesis. (Yup, that's a 115 percent
total -- some engineers wear multiple hats.)
To the question "TRUE or FALSE: As an engineer, I believe the American
legal system is generally capable of rendering justice in technically complex
lawsuits.", only 27 percent said TRUE. "I worked on the AMD/Intel suit with
Intel and the whole process was a joke. The judge was so technically
clueless the lawyers (also technically clueless) would spend 110 percent of
their time trying to dumb down the data and predict how the judge would
react." "TRUE -- but I would not want to have to stake my livelyhood on
this, though. I was once disqualified as a juror for a Speeding Ticket trial
because I knew how RADAR worked." 17 engineers referenced O.J. Simpson
and 5 mentioned the McDonald's scalding coffee lawsuit. "Can you spell OJ?
Can you spell DNA?"
To the question: "As an engineer, if I were the judge in the Cadence/Avant!
lawsuit, I (WOULD / WOULD NOT) grant Cadence's Sept. 11 request for an
injunction to prevent further sales of Avant! products that are alleged to
contain Cadence technology.", 13 percent of engineers said they WOULD, 66
percent said they WOULD NOT, and 21 percent said they didn't know. "WOULD
NOT -- once granted, the company's dead. There's no appeal after death."
"Cadence is a large mega-company bullying its way into marketshare. They
should be ashamed!" "Something smells fishy to me at Avant!" "I haven't
seen enough to prove guilt."
To the question "Because of this lawsuit, I am (MORE LIKELY / LESS LIKELY
/ UNCHANGED) to do business with Cadence.", 81 percent chose UNCHANGED,
16 percent LESS LIKELY, and 3 percent MORE LIKELY. "UNCHANGED -- But I feel
disgusted. It is not easy to switch CAD systems especially when you have
spent years building it up. I would if I could. Their tools are not
improving in terms of quality." "UNCH. I hate Joe Costello and Bill Gates,
but my company depends on products from both."
With the same question put in Avant! terms, 65 percent chose UNCHANGED,
29 percent LESS LIKELY, and 6 percent MORE LIKELY. "LESS LIKELY. I don't
want to be stuck with a future support issue." Only 12 percent of users
voiced interest in non-Avant!, non-Cadence P&R tools. "I think this lawsuit
will finish long before Compass Pathfinder finishes routing my 100k gate
design."
The biggest surprise came when I later compiled the 36 additional responses
from EDA employees. This group was three times as likely (42 percent versus
the EDA users' 13 percent) to grant Cadence's injunction. And EDA makers
were twice as likely (53 percent vs. 27 percent) to see the courts as
competent -- which helps explain why the EDA industry is so litigious!
----
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is past president
of the User Society for Electronic Design Automation (USE/DA) and works as a
contract ASIC/FPGA designer. He loves e-mail from fellow engineers at
"jcooley@world.std.com" or call (508) 429-4357. [ Copyright 1996 CMP ]
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