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>Why a schematic rather than an HDL? It should actually be much >simpler to hardwire in the HDL (XXX = constant), and the "generic >design" would be much more portable--i.e., not restricted to Xilinx, >ORCA, Altera, ... Assuming you like HDLs :) But that is another thread, much longer than this one ... But you are right. >With a schematic, you've got to match the schematic entry tool >and the vendor library--or else redraw it yourself! It takes only an hour or so to copy/draw the schematic of a UART, if you have say a hard copy in front of you. Not much to it. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 4551
>A Xilinx sales rep said something interesting to me once. "Software >prices are somewhat negotiable." They are, but only from say $5000 to say $3000. I tell you another little-known story: prior to about 1988, if you were a big potential user of Xilinx parts, they would give it away! They had a box with about 5000 dongles, and just picked one out of the box. >He called me back the next day, and informed me that they would throw in >the software package for free if I attended. Altera, Cypress et al have beeing giving away their s/w for years if you attend some of their seminars. A Xilinx sales rep told me at a very recent seminar that they would be quite happy to give it away, but they cannot ever do that with the 3rd party tools, e.g. Viewlogic. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 4552
You should find that an *analog* PLL is far less work. Just make a VCO, centre freq about (1024x50=51kHz) and divide its output by a 2^10 counter. You can do the whole lot with a 74HC4046 (or a 4046B) plus a counter; I think a 4060B has a 10th-tap output. Build it in a few hours, for less than the cost of a FPGA *socket*. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 4553
I'm currently working with an Altera 880 running at 100 MHz but this is not going to be fast enough. Does anyone know of an FPGA currently available or available soon that can handle clock speed in excess of 100 MHz?? Thanks in advance! Dean M. Dunnigan ddunnigan@ontrack.comArticle: 4554
Hi all,
I am wanting to do some powerline voltage and current data aquistions and then
to perform an FFT to extract the frequency information. I would like to change
the sampling frequency of the ADCs so that I get _exactly_ 1024 samples per
cycle of mains. The 50Hz (or 60Hz) does vary quite a bit during the day, so
making the blind assumption that it will be 50Hz is not valid.
A previous version of the meter used a CMOS PLL to lock onto zero crossings
and so the 1024X frequency. I am using a Xilinx FPGA for the glue between the
10 channel ADC and a TMS320C30 DSP. I would like to use this FPGA to provide
the conversion pulses for the ADCs rather than resorting to external
circuitry.
If you have some ideas on how to implement this or an comments, please let me
know, either by posting (for others to share) or in email.
Thanks in advance,
Dave Ingram
Masters student in Power Electronics
University of Canterbury
Christchurch, New Zealand
Article: 4555Comprehensive Verilog Training About the Verilog HDL Training Verilog HDL is enabling shorter design times and increased productivity. To tap this valuable resource, a designer needs to learn not just the language but how to apply the language to meet their design goals. The best courses and teachers offer the unique combination of design experience, HDL design and tools and teaching experience. No Substitute for Experience It's one thing to learn a hardware description language, it's another to understand how to apply the language to real world design issues. Each of our instructors has design and CAE experience and has worked with numerous design teams to help them fully realize the benefits of a hardware description language as well as has participated in language design itself. In addition, each instructor has teaching experience and experience as a design consultant helping customers solve their toughest design problems. Subject Matter . Our courses can be customized to meet your needs. From subject matter to delivery format we will be glad to discuss your specific requirements to maximize the effectiveness of the course. Current Classes (A detailed agenda is available for each class. All classes use labs to reinforce the concepts. More detailed information is available on each instructor.) Comprehensive Verilog HDL Training (3 days) An intensive course on the Verilog hardware description language. All aspects of behavioral, RTL, and gate level modeling are presented. The course enables the student to be productive with Verilog and Verilog software tools. A book "Digital Design with the Verilog Hardware Description Language - A comprehensive approach" written by Vivek Sagdeo is provided along with numerous examples and tool-usage guidelines. We begin with understanding of how and why the language was designed, go through each feature of the language, its syntax and semantics with examples of its usage, simulation and synthesis interpretations and any special considerations when used with other constructs. We also understand the 3 basic styles of modeling with Verilog - behavioral, rtl, and structural and where each construct fits in and when to use each style. We provide a detailed algorithmic and simulation-trace-based model of the language for deeper understanding of the concepts leading you to know them beyond the capabilities of the existing tools - into the future possibilities and new ways as well. After covering the entire language, including the system tasks, function, compiler directives and special interactive commands, we take several real life large designs like r4200 microprocessor, cache controllers, floppy disk controllers, memory models, Pentium model [you could choose from a range of designs] for to-down design with full simulation. A design cycle involving synthesis (behavioral and logic) is presented. A model for logic synthesis subset of Verilog is presented for a clear understanding of the following topic - Logic synthesis subset of Verilog. Each feature of synthesizable is discussed in detail with syntax, synthesis semantics and examples. Various useful synthesis directives and commands are discussed as well as modeling styles for quickly synthesizable and highly optimized designs. Advanced topics such as Programming Language Interface, Specify blocks (timing specifications) and switch-level modeling with strengths are discussed to provide the complete capabilities of Verilog to the designer. Hands on experience with the tools is also provided throughout the course and the students are ready to take real designs with accelerated schedules as they step out of the class with comfort and ease with the powerful design methodologies and techniques of today and tomorrow. When and where The next class is scheduled for Dec 3 to Dec 5 January class : Jan 7-9, 1997 in our Mountain View, CA Silicon VAlley Office at 444 Castro St. Fees : $595 for 3-day class Enrollment is limited. Please sign up today at WWW www.veri-log.com or by email training@veri-log.com Phone (408)973-7221/(415)961-4450 Fax (408)725-8885/(415)961-4450 -- Vivek SagdeoArticle: 4556
Comprehensive Verilog Training About the Verilog HDL Training Verilog HDL is enabling shorter design times and increased productivity. To tap this valuable resource, a designer needs to learn not just the language but how to apply the language to meet their design goals. The best courses and teachers offer the unique combination of design experience, HDL design and tools and teaching experience. No Substitute for Experience It's one thing to learn a hardware description language, it's another to understand how to apply the language to real world design issues. Each of our instructors has design and CAE experience and has worked with numerous design teams to help them fully realize the benefits of a hardware description language as well as has participated in language design itself. In addition, each instructor has teaching experience and experience as a design consultant helping customers solve their toughest design problems. Subject Matter . Our courses can be customized to meet your needs. From subject matter to delivery format we will be glad to discuss your specific requirements to maximize the effectiveness of the course. Current Classes (A detailed agenda is available for each class. All classes use labs to reinforce the concepts. More detailed information is available on each instructor.) Comprehensive Verilog HDL Training (3 days) An intensive course on the Verilog hardware description language. All aspects of behavioral, RTL, and gate level modeling are presented. The course enables the student to be productive with Verilog and Verilog software tools. A book "Digital Design with the Verilog Hardware Description Language - A comprehensive approach" written by Vivek Sagdeo is provided along with numerous examples and tool-usage guidelines. We begin with understanding of how and why the language was designed, go through each feature of the language, its syntax and semantics with examples of its usage, simulation and synthesis interpretations and any special considerations when used with other constructs. We also understand the 3 basic styles of modeling with Verilog - behavioral, rtl, and structural and where each construct fits in and when to use each style. We provide a detailed algorithmic and simulation-trace-based model of the language for deeper understanding of the concepts leading you to know them beyond the capabilities of the existing tools - into the future possibilities and new ways as well. After covering the entire language, including the system tasks, function, compiler directives and special interactive commands, we take several real life large designs like r4200 microprocessor, cache controllers, floppy disk controllers, memory models, Pentium model [you could choose from a range of designs] for to-down design with full simulation. A design cycle involving synthesis (behavioral and logic) is presented. A model for logic synthesis subset of Verilog is presented for a clear understanding of the following topic - Logic synthesis subset of Verilog. Each feature of synthesizable is discussed in detail with syntax, synthesis semantics and examples. Various useful synthesis directives and commands are discussed as well as modeling styles for quickly synthesizable and highly optimized designs. Advanced topics such as Programming Language Interface, Specify blocks (timing specifications) and switch-level modeling with strengths are discussed to provide the complete capabilities of Verilog to the designer. Hands on experience with the tools is also provided throughout the course and the students are ready to take real designs with accelerated schedules as they step out of the class with comfort and ease with the powerful design methodologies and techniques of today and tomorrow. When and where The next class is scheduled for Dec 3 to Dec 5 January class : Jan 7-9, 1997 in our Mountain View office at 444 Castro St. Fees : $595 for 3-day class Enrollment is limited. Please sign up today at WWW www.veri-log.com or by email training@veri-log.com Phone (408)973-7221/(415)961-4450 Fax (408)725-8885/(415)961-4450 -- Vivek SagdeoArticle: 4557
CALL FOR PAPERS AND PARTICIPATION
1997 IEEE INTERNATIONAL WORKSHOP
ON MEMORY TECHNOLOGY, DESIGN AND TESTING
August 11-12, 1997
Submission deadline: January 15, 1997
Send submissions to:
TECHNICAL PROGRAM CHAIR
Thomas Wik
LSI Logic, MS E-194
1501 McCarthy Blvd
Milpitas CA 95035, USA
408/954--4471; trw@lsil.com
Address general inquiries to:
GENERAL CHAIR
Fabrizio Lombardi
Computer Science MS 3112
Texas A&M University
College Station TX 77843, USA
409/845--5464; fax 847--8578
lombardi@cs.tamu.edu
The 1997 IEEE International Workshop on Memory Technology, Design and
Testing will be held at the Hilton Hotel and Towers, 300 Almaden Blvd,
San Jose, California, USA (408/287--2100), on August 11-12, 1997.
The workshop will include all aspects of memory design, process
technologies and testability related topics. Memory circuit designs,
cell structures, fabrication processes, design architectures as
related to testing, verification and test methods for SRAM, DRAM,
Flash and Non-Volatile memories, EPROM, EEPROM, embedded memories,
logic-enhanced and FIFO memories, 3-D memories and content addressable
memories. Some representative topics are:
- Memory fault modeling and test generation
- Built-in test and testable designs for memories
- Concurrent checking and memory fault diagnosis
- Quality and reliability issues
- Space applications and radiation hardening issues
- Memory failure and yield analysis
- High-speed, innovative designs
- Fault isolation, reconfiguration and repair
- Multiported, multibuffered memories
- Logic-enhanced and programmable memories
- Application-specific and embedded memories
- Multimegabit SRAMs and DRAMs
- CMOS, BiCMOS and bipolar designs for high yield and reliability
Authors please submit five (5) copies of an extended abstract of about
1000 words of original work on any aspect of memory technology, design
and testing to the Technical Program Chair. Submissions should
include full names and affiliations of authors, contact information
and should indicate the intended presenter.
Submissions are due January 15, 1997. Authors will be notified of
acceptance on March 31, 1997. Final papers will be due May 15, 1997.
Presentations will be 30 minutes, inclusive of discussion.
Sponsored by:
IEEE Computer Society
Technical Committee on Test Technology
Technical Committee on VLSI
In cooperation with:
IEEE Solid-State Circuit Council/Society
Article: 4558Hi all, I'm looking for a multiplier 16x16 (bit 15=sign, bit [14:10]=exp, bit [9..0]=mantisse) the mantisse should be normalised. If someone could give me a link to the FPGA file, I would be very happy Thank's samArticle: 4559
verilog library of gpl'd verilog yes Yes YES I would love this. I have part of an ethernet interface (target 1GBit) and the boss wouldn't mind, if there were a well-known site. LArticle: 4560
Michael Ismert wrote: > > On a related note: has anyone given any thought to (or does there > exist) a site where people could put up FPGA designs more or less as > freeware? We have a slightly crufty PCI bus master/slave design that > we wouldn't mind making available for people who wanted to poke around > without spending the big bucks on Xilinx's prepackaged modules. I > suppose this sort of thing would be primarily targetted at university > research, where people weren't so concerned about giving away their > advantage over their competition, and also weren't making devices in > very large quantities. Perhaps such designs could be copy-lefted > under the GPL or some such thing to keep them freely available. > I couldn't agree more. Perhaps MIT or another university would want to host such a site. We (GigaOps) might even be interested in hosting it. When you start to look at what you want in such a site however, it become clear that lot of labor and disk space could be involved. Perhaps there is a way to create a self maintaining site. I see it as a web site for ditections and info with an FTP site for uploading and downloading. Maybe it works like this: To contribute: - register at the site by filling out some forms and receive a password - log on to the FTP area with password - make a directory under your name and transfer the files - the site maintainer then periodically will inspect new uploads and link them into the web pages accordingly. All transfers must be accompanied by a readme file. All web page references must include a link to the author for credit and futher interaction. To recieve: - goto the web site in you browser - follow the links to the data you want or - search the site for the data you want - then download via FTP or your browser. - send a review of the data back to the site The following types of data might be appropriate: - source designs in schematics, HDLs ... - logic macros in EDIF, XNF, ... - .bit files with docmented functionallity - working host programs for commercial and research FPGA platforms. - shareware translators (xnf2edif etc) - new exerimental design tools such as C compilers, filter generators. - and most importantly, user reviews of above data Sounds easy eh? - BradArticle: 4561
Dean Dunnigan wrote: > > I'm currently working with an Altera 880 running at 100 MHz > but this is not going to be fast enough. Does anyone know > of an FPGA currently available or available soon that can > handle clock speed in excess of 100 MHz?? > Depending on what you are trying to do, both the Xilinx XC3100A FPGA family and the Xilinx XC9500 CPLD family support clock frequencies in excess of 100 MHz. Is there a specific critical path? --------------------------------------------------------------- Steven K. Knapp Xilinx, Inc. Vertical Applications Manager 2100 Logic Drive (408) 879-5172 (voice) San Jose, CA 95124 (408) 879-4442 (FAX) U.S.A. E-mail: stevek@xilinx.com Web: http://www.xilinx.comArticle: 4562
Jens Weigle wrote: > > Hi! > > I need a RS-232 interface for XILINX FPGAS. > > Who can help me ? > > I need a ready and tested UART-DESIGN for quick implementation. > -- > --- > Mit freundlichen Gruessen > Jens Weigle, Dept. T62 > ======================================================================= > ESW, Extel Systems Wedel > Gesellschaft fuer Ausruestung mbH | Phone : (+49) 4103 60-3664 > Industriestr. 23-33 | FAX : (+49) 4103 60-4513 > D-22880 Wedel | e-mail: weigle@tc-wedel.de > ======================================================================= One of the Xilinx LogiCore Alliance partners, MEMEC Design Services, provides UART designs for both the Xilinx XC4000E and XC5200 family FPGAs. Information via the Web is available at http://www.mds.memec.com/modules.shtml Information regarding other Xilinx LogiCore Alliance partners is available via the Xilinx web site at http://www.xilinx.com/products/logicore/lcpp.htm Thank you for your inquiry. --------------------------------------------------------------- Steven K. Knapp Xilinx, Inc. Vertical Applications Manager 2100 Logic Drive (408) 879-5172 (voice) San Jose, CA 95124 (408) 879-4442 (FAX) U.S.A. E-mail: stevek@xilinx.com Web: http://www.xilinx.comArticle: 4563
Peter wrote: > > Now, if someone published a 16550, complete with the FIFOs... I did a > design (not a UART) a while ago, with a 24-byte FIFO in it, and after > heavy layout tweaks it filled a 3020. A 16550 in a FPGA would be the > world's most expensive UART :) It turns out that the Xilinx XC4000E's on-chip RAM is quite efficient for building shallow FIFOs (< 128 locations deep). For example, the 24-byte FIFO that you mentioned about would consume only an estimated 16 to 24 logic blocks of the hundreds available on a device. If you are interested, here are a few potentially interesting locations: Synchronous/Asychronous FIFOs in Xilinx XC4000E =============================================== http://www.xilinx.com/xapp/xapp051.pdf Implementing FIFOs in XC4000E Series RAM ======================================== http://www.xilinx.com/xapp/xapp053.pdf XC4000E/EX Data Sheet ===================== http://www.xilinx.com/products/fpgaspec.htm#XC4000 16550-like Macro from MEMEC Design Services for Xilinx FPGAs ============================================================ http://www.mds.memec.com/xfiles/datasheets/xf8250.pdf -- --------------------------------------------------------------- Steven K. Knapp Xilinx, Inc. Vertical Applications Manager 2100 Logic Drive (408) 879-5172 (voice) San Jose, CA 95124 (408) 879-4442 (FAX) U.S.A. E-mail: stevek@xilinx.com Web: http://www.xilinx.comArticle: 4564
Kimiko Nemoto wrote: > > Dear Netters: > > Does anyone know some good pointers on very recent FPGA boards ? > (commercial products) > > I need around 100,000 available gates for my designs (several FPGA > chips on the same board). Depending on what type of "thing" you are trying to build, here are a few commercial prototyping systems that may be of interest. APTIX ===== http://www.aptix.com:80/Products/mp3_databook/mp3_databook.html Multi-FPGA board with field programmable interconnect (FPIC) devices. QUICKTURN ========= http://www.quickturn.com/prod/realizer/sysreal.htm Hardware emulation system(s) providing up to 3 million system gates. Highly sophisticated system. --------------------------------------------------------------- Steven K. Knapp Xilinx, Inc. Vertical Applications Manager 2100 Logic Drive (408) 879-5172 (voice) San Jose, CA 95124 (408) 879-4442 (FAX) U.S.A. E-mail: stevek@xilinx.com Web: http://www.xilinx.comArticle: 4565
> >I need a RS-232 interface for XILINX FPGAS. > > If anyone finds a *decent* UART schematic, I would be very interested > to see it. The best I have seen to date is a cut-down UART in an old > Actel app note book. Is there not any VHDL code available for UARTs. You would then be able to select the appropriate or general solution by importing/commenting out the relevant architectures. There must have been an engineer somewhere who has written some UART VHDL ??? Gareth BaronArticle: 4566
Peter wrote: > >Altera, Cypress et al have beeing giving away their s/w for >years if you attend some of their seminars. > >A Xilinx sales rep told me at a very recent seminar that they >would be quite happy to give it away, but they cannot ever do >that with the 3rd party tools, e.g. Viewlogic. If this were true, why doesn't Xilinx give away the back end for free? And this back end has a dongle on it, too. If this were true why does it cost more money to get back end tools that can work with bigger chips? The 3rd party tools don't care. If this were true, why does XBLOX cost extra? In other words, the rep made an excuse for the pricing policies of Xilinx. I guess they felt thay had to since they couldn't think of a valid reason for it. According to Xilinx (1996 annual report), software only accounts for 3% of gross sales. I am absolutely sure that free software would more than make up for that in increased chip sales. Xilinx is selling only about 6000 software packages a year, average price is $3k. That's a steep hill for a lot of users, especially when you consider that Xilinx chips are very well suited to low volume applications. Imagine someone builds a microprocessor where you can only get the assembler/compiler from them for $1k? And, oh, that's only for small programs, you want to write more than a thousand lines of code will cost you $5k! Anybody use that chip? A lot fewer people. Now days, companies work hard to get gcc ported to their chip, and then give that away free. Mike Ciholas (812) 858-1355 voice CEDAR Technologies (812) 858-1360 fax 5855 Fiesta Drive mikec@flownet.com Newburgh, IN 47630 mikec@lcs.mit.eduArticle: 4567
Currently have a need for 2 hardware engineers to transfer schematics (digital video processing) into VHDL code. An understanding of Xilinx FPGA tools is a big plus. The position is for 2-3 months paying in the $80/hr DOE range. Locations is Los Gatos CA (Bay Area) A flex schedule is available between the hours of 8am and 12 midinight. Please call: Jason Tayles Jason J. Tayles Volt Regional E-mail: voltj@ix.netcom.com Phone:800.422.8777 Fax:602.955.8536Article: 4568
I'm interested in finding out the relative merits of timing diagram editor tools like WaveformerPro from SynaptiCAD and TimingDesigner from Chronology. We need a tool to analyze and document timing between blocks at the system and unit levels. It would be nice if the tools can generate stimulus files in VHDL and/or Verilog for use in a testbench. It seems to me that WaveformerPro and TimingDesigner have about have about the same level of functionality, but the former is about half the price. Has anyone looked at both of them? Which one is the better value? Are there any other vendors I should be looking at? Thanks in advance. -- Lindo St. Angel PrairieComm, Inc. (847) 797-4085Article: 4569
deand@ontrack.com (Dean Dunnigan) wrote:
>I'm currently working with an Altera 880 running at 100 MHz
>but this is not going to be fast enough. Does anyone know
>of an FPGA currently available or available soon that can
>handle clock speed in excess of 100 MHz??
>
>Thanks in advance!
>
>Dean M. Dunnigan
>ddunnigan@ontrack.com
>
>
Wow, that's damn fast since Altera only claim 50-100Mhz for their
FLASHlogic, and we all know what maunufacturers statistics are like!
;-)
Have you tried it in an Altera MAX 7000 part? They claim 70-175 Mhz
for those.
If this gets you no further, give us some more information, such as
the naure of your circuit, what portions require full speed operations
etc.
Hope this helps
Bye
--
---------------------------------------------------------------------
Julian Cox
CoxJA@augustsl.demon.co.uk error: smartass.sig not found
Hardware development eng. August Systems Ltd
---------------------------------------------------------------------
Article: 4570Job; Upstate NY; Senior Engineer; FPGA; Altera; High Speed Digital. 5+ Years Exp. Must have: signal processing, algorithms, high speed digital design (40-50 MegaHertz), FPGAs, and exposure to imaging &/or sensor systems applications. Client using ViewLogic and Spice CAE/CAD tools. 60-70% design/ detailed design; 30-40% systems level work.Medical Imaging Applications Please refer to JO# 582RJS in your response. Richard Steinman. Career Marketing Associates. rjs@cmagroup.com Richard has 15 Years Experience In Nationwide Engineering,Technical & Scientific Search and PlacementArticle: 4571
Hi, We are looking for a VHDL code editor for Windows NT platform. All information is welcome. If you reply to the group, send also a copy to the address vrowley@hexavision.com . Thanks, Vincent Rowley -- ----------------------------------------------------------------------- -- Vincent Rowley -- HexaVision Technologies Inc. -- -- -- 2050 Rene-Levesque ouest -- -- Email: vrowley@hexavision.com -- Bureau 101 -- -- Tel: 418-686-5000 (233) -- Sainte-Foy, Quebec, Canada -- -- Fax: 418-686-5043 -- G1V 2K8 -- -----------------------------------------------------------------------Article: 4572
there must be a lot of stupid people out in cyberspace. And by the way..... this is very illegal, and you've just left a psedo-paper trail. STOP CLOGGING THIS NEWS GROUP WITH YOUR GARBAGE.Article: 4573
I'm using Xilinx's Foundation for VHDL. I'm trying to figure out how to change a 4 bit add to have a carry in and carry out. (I can't find anything like this in my VHDL books). Ie currently I have something like (from memory) signal A,B,C : STD_LOGIC_VECTOR (3 downto 0); signal C_IN, C_OUT : STD_LOGIC; ..... A <= B + C ; and I want something like A with C_OUT <= A + B + C_IN ; Anyone know how to do this? Cheers Chris Hart - chris.hart@iee.orgArticle: 4574
gavin@cypher.co.nz (Gavin Melville) wrote: >As a long time ViewLogic user I am considering changing to the Aldec >tools (Foundation) -- mainly to get a usable simulator. I've done just that. >Has anyone else done this, and how did the changeover go ? -- I am >aware that you can convert the schematics, but this involves a bigger >picture. Its early days I believe (from a colleague) that schematic conversion works but is a bit flaky. The simulator is great. VHDL is good too, although its a low cost package and I have the feeling you high cost packages would be better. I have had a problem with the simulator with VHDL which Xilinx are looking into. I think I would recommend the change but maybe you should evaluate it first ... Chris Hart - chris.hart@iee.org
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