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Dorian Nawrath wrote:
>
> Gerrit Telkamp (telkamp@eis.cs.tu-bs.de) wrote:
> : Hello,
> : where can I get a PIC16C71-core (schematic or VHDL) for a XILINX XC4000 design ?
> : Thank you for every comment,
> : Gerrit.
>
> I'm interested too,
> Dorian
Me too.....
--
Les Hughes - Applications Group
Computing Services | Phone: +44 (0)181 331 8390 / 8566
University of Greenwich |
Woolwich, London SE18 6PF | E-Mail: L.J.Hughes@greenwich.ac.uk
Article: 2826
The Hardware Compilation Group at Oxford University is pleased to
announce the formal start of a new collaboration between ourselves,
Advanced RISC Machines (ARM), and European Silicon Structures (ES2).
The `Aspire' project intends to use Oxford's hardware/software
co-design tools and expertise to offer a design flow into ARM-based
ASICs starting from system descriptions in the form of C-like
programs. The flow will also support a rapid prototyping phase on a
new ARM-based reconfigurable computer.
There is now a vacancy on this project the details of which have been
posted on uk.jobs.offered. Alternatively the job description is at:
http://www.comlab.ox.ac.uk/oucl/users/ian.page/hwcomp/aspire/aspire.html
==============================================================================
Ian Page, F.I.E.E., University Lecturer,
Head of Hardware Compilation Research Group,
Oxford University Computing Laboratory,
Wolfson Building, Parks Road, Oxford OX1 3QD, U.K.
Tel: (+44/0) 1865 273853 direct, 273840 sec, 0378 058921 mobile, 273839 fax.
www: http://www.comlab.ox.ac.uk/oucl/people/ian.page.html
==============================================================================
Article: 2827baten@hermes1.econ.uni-hamburg.de (Miranda Baten) wrote: >Dear Sir > >if today a best FPGA have some 100 k gater density >and some 50 % duty,is it possibly to make from >one FPGA chip R3000/r3010 or R3081 MP ? > >I would very pleased for some info .Please >post me. Very unlikely... Even the new high density FPGAs must be derated in the gate capactiy when designing real circuits. In general, FPGAs have way more DFFs than you can use. And the vendors compute their "gate capacities" by assuming you will use ALL of the DFFs in the FPGA. On the otherhand... THey are getting bigger all the time. 8 bit micros fit quite nicely in 13,000 gate FPGAs (then synthesize to <4,000 ASIC gates) which are available today. The Xilinx XC8100 family is real nice... check it out... It quotes very nearly the same number of gates as an ASIC! -- Eric Ryherd eric@vautomation.com VAutomation Inc. Synthesizable HDL Cores 20 Trafalgar Square http://www.vautomation.com Suite 443 Nashua NH 03063 (603) 882-2282 FAX:882-1587Article: 2828
When i posed this question, I got only one reply - from an Altera person who said there was an entry level package that included a programmer, schematic entry and route software for $500. He said it supported the lower end devices. This sounds ideal, but Altera are not represented here. 2 Questions : What devices does it support What is it called (& where can it be got in the SF Bay area) MArticle: 2829
Tony Clark <tonyc@perth.DIALix.oz.au> wrote: > > On Sat, 10 Feb 1996, HIKIMA Toshio wrote: > > > Hi FPGAers, > > > > I am using Xilinx XC4013. By the databook it is not specified > > minimum delay. > > My rep said, " there is no specificaton about minimum delay". Is it right? > > > > If true, how can I design DRAM I/F? DRAM's spec has many complex constraient > > so that it should be used minimum delay value. > > > > Thanks, > > -- > > T.Hikima > > > > The right way to do this is with a SYNCHRONOUS design clocked at a multiple of the bus speed. To get the high performance you will need for the DRAM controller you will have to observe high performance design rules and will likely need to floorplan at least the I/O paths to control the delays. It is really not that difficult to do, it just takes a little experience with the parts and the tools. As far as specifying minimum delays goes, there are very few logic devices that have these specified, and for good reason. If you are depending on min delays, what's going to happen when the parts are improved? You guessed it, your design that depended on min delays doesn't work anymore. Its a bitch going back into a design you haven't touched in a few years to chase down a problem that 'mysteriously' appears in production. If you're lucky, you've left the company by then and some other poor SOB has to figure it out. In the words of Raytheon's Bob McGurrin: "Speed Kills". Design for it now so you don't become the next victim. -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure.Article: 2830
Les Hughes <L.J.Hughes@gre.ac.uk> wrote: >Hi, >We teach digital systems using the Mentor / Xilinx s/ware. This consists >of a basic schematic capture - simulation - bit file production - >download to a test rig using xchecker, exercise followed by >similar tasks using VHDL - QuickSim - Autologic - XACT - XChecker >As for QuickVHDL and A/logic II, this was only released for our >OS last month so I haven't installed it yet. > >We have a direct support agreement with MGC and I have found >there help excellent. Our Xilinx support is through an academic >scheme and is not as good. > >Just for the record, we're using the A3F release and XACT 5.1.1 on >Sun Solaris 2.5. Generally, once bashed into shape by my mate vi ;-) >the system works well. hi les, thanks much for your input ... is XCHECKER really available to you under XACT 5.1.1 on solaris? we were told by our xilinx rep last week that this debug capability is not available under XACT 5.1 on *any* unix platform (we're an HP house) and that its only available under the new XACT 6.0 release for PC's (windows). we're about to embark on our first xilinx design, a large XC4025E, so i'm interested in running XACT on unix where we have adequate cpu/memory/disk resources. however, we anticipate a feature like XCHECKER will be very useful, indeed, enough to sway our platform decision. perhaps XCHECKER has been unbundled for sale in the UK? based on responses to my posting, xilinx and mentor tools appear to be popular teaching vehicles. i tend to be methodology-oriented and was wondering if you might have any class/lab notes describing your design process which you'd be willing to share? i suppose this would only be feasible if your docs were in electronic form. thanks again for your comments, -- ____________________________________________________________________________ Lance Gin "off the keyboard Delco Systems - GM Hughes Electronics over the bridge, OFC: 805.961.7737 FAX: 805.961.7329 through the gateway, C43LYG@dso.hac.com nothing but NET!" ____________________________________________________________________________Article: 2831
In <DMI1r0.GyB@maz-hh.de> pwu@maz-hh.de (Peter Wurbs) writes: > > >Hi Xilinx-Freaks, > >I use an output of a XC3195A as a Chip-Select for a SRAM. >The CS-Signal has a pullup to a battery-buffered voltage to >maintain RAM data if the power is down. The FPGA is supplied >by the unbuffered power supply. > >It is the normal behavior of the IOB, that it is high impedance >if the power voltage is below a certain level. >But I could measure that the CS-signal is pulled to Low by the >FPGA if the power voltage is near 0.8V. For less than 0.8 V it is >o.k. again. >But the precondition for the pullup to Vbatt is, that the FPGA output >is high impedance over the full range of power supply. > > > > | Vbatt (1.8V if power down) > | > | > | > - > | | > | | > |_| >|---------------| | |------| >| | | CS | | >| FPGA |-------------------| RAM | >| | | | >|---------------| |------| > | | > | | > VCC Vbatt > > >Is this behavior a property of Xilinx-FPGA's ? >Or is it the problem, that I pull the output to Vbatt while VCC is low ? >Can I avoid this problem ? > >Thanks in advance for your help . > >Bye, > >Peter. > >--------------------------------------------------------- >Peter Wurbs (MAZ Hamburg GmbH, Dep. Broadband Communication) >Phone: ++40-76629 1771 >Fax: ++40-76629 199 >e-Mail: pwu@maz-hh.de >--------------------------------------------------------- > > Peter, We had a problem similar to this ... except it was with EEProm. We were getting data corruption of our calibration tables during power up/down. First, a small cap combined with the 5 nH/inch lead inductance can filter out spikes on the CS line. Next, using a power supervisor such as the TI7705B will give you a signal to gate the CS line off when power dips below 10 percent of nominal voltage. Be sure to use the R_ output so the default condition is RESET. Finally, the FPGA will be more predictable if you use the supervisor output to RESET the FPGA. This will give several hundred mSecs delay before the following recover/restart. The power on/off sequence gets a bit involved but you may have to go through it. We did. And EEProms have software data lockout protection built in along with some hardware protections. Paul FredaArticle: 2832
Has anyone out there used FPGA devices from Crosspoint Solutions?
I'd would like to know if there are things that I must be aware of.
Due to the fine grain technology that Crosspoint has, I'd like to
use top down tools to target Crosspoint FPGAs. I am most concerned in the
layout and routing phases of the design process--what's the chance for
first time success, the accuracy of timing parameters from back
annotation etc...
Another issue that concerns me is that I'm using COMPASS synthesis
tools and COMPASS did not have Crosspoint's library. I heard a rumor
that COMPASS is coming out with a synthesis library to support
Crosspoint's FPGAs. Can anyone confirm this? Is anyone using COMPASS
tools to target Crosspoint? Any major problems using COMPASS tools with
Crosspoint FPGAs?
I'll certainly appreciate your comments/suggestions/viewpoints on
the above.
--Bin
Article: 2833In article 100000@perth.DIALix.oz.au, Tony Clark <tonyc@perth.DIALix.oz.au> () writes: >On Sat, 10 Feb 1996, HIKIMA Toshio wrote: > >> Hi FPGAers, >> >> I am using Xilinx XC4013. By the databook it is not specified >> minimum delay. >> My rep said, " there is no specificaton about minimum delay". Is it right? >> >> If true, how can I design DRAM I/F? DRAM's spec has many complex constraient >> so that it should be used minimum delay value. >> >> Thanks, >> -- >> T.Hikima >> >> >You really need to simulate after working out the delays due to routing >etc. I'm not a Xilinx user yet, but thats the impression I get from >looking at the Databook... > Even the post layout simulation does not include Min-Delays. If you generate a SDF-File from the LCA-File it only includes Max-Delays. Bye, Peter. --------------------------------------------------------- Peter Wurbs (MAZ Hamburg GmbH, Dep. Broadband Communication) e-Mail: pwu@maz-hh.de ---------------------------------------------------------Article: 2834
In article <9602131539.AA06279@peridot.comlab.ox.ac.uk> Ian.Page@comlab.ox.ac.uk (Ian Page) writes: The `Aspire' project intends to use Oxford's hardware/software co-design tools and expertise to offer a design flow into ARM-based ASICs starting from system descriptions in the form of C-like programs. The flow will also support a rapid prototyping phase on a new ARM-based reconfigurable computer. Ian, can you give some more information on the reconfigurable computer? I wasn't able to find a dns entry for your web page. BillArticle: 2835
john, you pose some interesting issues, and of course, i have questions ... >We are using Mentor's Top down tools to target Xilinx devices using XACT and NeoCAD. what versions of mentor and XACT are/were you running? is XACT running on HP as well? >1/ XACT did not install correctly on our HP-UX host was this problem recognized by xilinx? has it been fixed? >2/ Mentor creates ModelName_s; Xilinx does not like _s. We couldn't create a .xnf >file for months was this problem recognized by xilinx/mentor? has it been fixed? >3/ Xilinx recommend XBlox. XBlocks models don't have timing characteristics. are you referring to models for use by the XACT XDELAY static TA tool? or perhaps you're referring to QuickPath? does xilinx have any plans to supply the models you need? >4/ TimSim8 (backannotation of routed design timing to "Schematic") does not modify >the source schematic (EDDM database) via a viewpoint. It generates another design >database in a separate directory. This presents a rather serious configuration >control problem. heard something about this. understand VHDL VITAL libraries are not available with the mentor/XACT kit :-( therefore, must be a problem with schematic design method. possibly related to XACT performing an additional level of optimization on the XNF created by mentor? if true, the new XNF may not have 1:1 structural correspondance to your original schematics. thus the need to generate a new set of schematics. right? or off-base? >5/ An EDIF read licence is required, at the unreasonable price of ~=A32000. how is this used in the mentor/XACT flow? >6/ XNFBA still does not work. we're new to the xilinx world. what's XNFBA? >Mentor tools work well together and deliver good results. Xilinx tools are good and >deliver well. The integration, intertool communications and design control are >absolutely lousy. It is particularly annoying given that Mentor's Framework >Initiative promised to solve these problems! (Oh yes, its Xilinx's problem for not >integrating......) a big concern of mine, esp if i start having problems. here in the US, i have to deal with *many* interfaces: 1. a distributor who sells the mentor XACT kit. mentor is not allowed to sell the kit to me (so where is mentor's $$ motivation to support my new xilinx flow?). the distributor has an FAE, but he's experienced with viewlogic on PC's, not mentor. 2. a xilinx FAE. he too, is not that familiar with mentor (but good on other stuff). 3. the xilinx tech support hotline. i asked if xilinx supported VITAL. they said "yes" and cited their preferred 3rd-party partners. i talked to mentor. no VITAL. good advice when it comes to device questions though. 4. our local mentor FAE. finally, someone who might be able to help. he's a sharp guy, but overworked and supporting sales. (see also 1. above). 5. mentor tech support. ok, haven't tried them yet. my experience tells me they're more helpful in detailed, tool-specific questions as opposed to multi-vendor, multi-tool flow problems. we'll see. as a side note, i wonder how this issue will be handled once ANTARES gets going. imagine a flow with mentor, model tech, exemplar, meta, co-soft, xilinx, ... how many people will i need to talk to then? >Neither Mentor nor Xilinx could provide us with an overall process diagram and >process description. hope this has changed. actel documents their mentor flow in their docs (although i found actel hotline's mentor experience to be lacking as well - seems they have lots of viewlogic expereience). >We have, somehow, managed to knife and fork a usable process. hope this changes too. as fpga's get bigger, design flows will look more like asic flows - right up mentor's alley. last question: is the XChecker debug utility avail in your XACT kit (apparently a newer utility, may not be in your XACT version on your platform). "opinions expressed are my own and not my company's" -- ____________________________________________________________________________ Lance Gin "off the keyboard Delco Systems - GM Hughes Electronics over the bridge, OFC: 805.961.7737 FAX: 805.961.7329 through the gateway, C43LYG@dso.hac.com nothing but NET!" ____________________________________________________________________________Article: 2836
i recently received a pile of literature from a local xilinx rep which goes to great length to point out the deficiencies in altera fpga routing resources. while i can easily see the limitations on paper, i'm curious as to what people have experienced in reality. so how about it? anyone care to share their real life success stories and/or tales of woe relating to altera and xilinx routing issues? later. joe.Article: 2837
In <4ftikh$sig@hacgate2.hac.com> Lance Gin <c43lyg@dso.hac.com> writes: In answer to issue 5 below, Antares is up and running. The flow you are looking for is available now. The Exemplar Galileo environment is a fully, interactive environment with synthesis, back annotation, timing analysis, and verification. The Verification is provided by Model Technology. The flow is fully VITAL compliant and Exemplar maintains the VITAL libraries. For Xilinx Exemplar supports both EDIF and XNF netlist formats. They even extract timing from the Xilinx netlist after PPR and overlay it to the VITAL models. The whole flow makes use of the VITAL acceleration capability of the MTI simulator. The flow is identical on PCs and Workstations. The entire flow is supported by Exemplar, except for PPR, but they are also quite knowledgeable about the vendor place and route tools. Bob > >john, > >you pose some interesting issues, and of course, i have questions ... > >>We are using Mentor's Top down tools to target Xilinx devices using XACT and NeoCAD. > >what versions of mentor and XACT are/were you running? is XACT running >on HP as well? > >>1/ XACT did not install correctly on our HP-UX host > >was this problem recognized by xilinx? has it been fixed? > >>2/ Mentor creates ModelName_s; Xilinx does not like _s. We couldn't create a .xnf >>file for months > >was this problem recognized by xilinx/mentor? has it been fixed? > >>3/ Xilinx recommend XBlox. XBlocks models don't have timing characteristics. > >are you referring to models for use by the XACT XDELAY static TA tool? >or perhaps you're referring to QuickPath? does xilinx have any plans to >supply the models you need? > >>4/ TimSim8 (backannotation of routed design timing to "Schematic") does not modify >>the source schematic (EDDM database) via a viewpoint. It generates another design >>database in a separate directory. This presents a rather serious configuration >>control problem. > >heard something about this. understand VHDL VITAL libraries are not available >with the mentor/XACT kit :-( therefore, must be a problem with schematic design >method. possibly related to XACT performing an additional level of optimization >on the XNF created by mentor? if true, the new XNF may not have 1:1 structural >correspondance to your original schematics. thus the need to generate a new >set of schematics. right? or off-base? > >>5/ An EDIF read licence is required, at the unreasonable price of ~=A32000. > >how is this used in the mentor/XACT flow? > >>6/ XNFBA still does not work. > >we're new to the xilinx world. what's XNFBA? > >>Mentor tools work well together and deliver good results. Xilinx tools are good and >>deliver well. The integration, intertool communications and design control are >>absolutely lousy. It is particularly annoying given that Mentor's Framework >>Initiative promised to solve these problems! (Oh yes, its Xilinx's problem for not >>integrating......) > >a big concern of mine, esp if i start having problems. here in the US, >i have to deal with *many* interfaces: > >1. a distributor who sells the mentor XACT kit. mentor is not allowed to sell > the kit to me (so where is mentor's $$ motivation to support my new xilinx > flow?). the distributor has an FAE, but he's experienced with viewlogic on > PC's, not mentor. > >2. a xilinx FAE. he too, is not that familiar with mentor (but good on other > stuff). > >3. the xilinx tech support hotline. i asked if xilinx supported VITAL. they > said "yes" and cited their preferred 3rd-party partners. i talked to > mentor. no VITAL. good advice when it comes to device questions though. > >4. our local mentor FAE. finally, someone who might be able to help. he's a > sharp guy, but overworked and supporting sales. (see also 1. above). > >5. mentor tech support. ok, haven't tried them yet. my experience tells me > they're more helpful in detailed, tool-specific questions as opposed to > multi-vendor, multi-tool flow problems. we'll see. > >as a side note, i wonder how this issue will be handled once ANTARES gets >going. imagine a flow with mentor, model tech, exemplar, meta, co-soft, >xilinx, ... how many people will i need to talk to then? > >>Neither Mentor nor Xilinx could provide us with an overall process diagram and >>process description. > >hope this has changed. actel documents their mentor flow in their docs >(although i found actel hotline's mentor experience to be lacking as well - >seems they have lots of viewlogic expereience). > >>We have, somehow, managed to knife and fork a usable process. > >hope this changes too. as fpga's get bigger, design flows will look more >like asic flows - right up mentor's alley. > >last question: is the XChecker debug utility avail in your XACT kit >(apparently a newer utility, may not be in your XACT version on your platform). > >"opinions expressed are my own and not my company's" > >-- >______________________________________________________________________ _____ > >Lance Gin "off the keyboard >Delco Systems - GM Hughes Electronics over the bridge, >OFC: 805.961.7737 FAX: 805.961.7329 through the gateway, >C43LYG@dso.hac.com nothing but NET!" >______________________________________________________________________ _____ > >Article: 2838
Rerouting with locked pinout is possible with ALTERA if you have done
the
pinout well. That means that you have to do something like a
floorplanning to
determine your pinout. This is even reasonable if you don't want to
change
the pinout.
To do this floorplanning, you just have to use a copy of the footprint
of your
choosen device and write down the ROW/COLUMN information you will find
in the
device & adapter section of the ALTERA online help. This should help to
assign pins
belonging to a logical block close to each other. Tis is the reason why
I call it
floorplanning, because you define the area where the logic block is
placed.
Even, it is a good practice to put the outputs on the rows and the
inputs on
columns.
--
_/ _/ _/
_/ _/ _/ EED/E/X/A/ Andreas Hofmann Phone:
+49-5121-707-378
_/ _/ _/ Ericsson Eurolab Deutschland GmbH FAX :
+49-5121-707-333
_/ _/ _/ Daimlerring 9 Memo : EED.EEDANHO
_/ _/ _/ 31135 Hildesheim - Germany Email:
ftdanho@ftd.ericsson.se
_/ _/ _/
Article: 2839Anyone know if there's an Abel mode for Emacs? Know where I can get it? Chris -- ============================================================================= Christopher G. Holmes Me: holmes@chrysal.com Chrysalis Research Corporation Inquiries: info@chrysal.com 52 Domino Drive Voice: 508-371-9115 Concord, MA 01742-2817 Fax: 508-371-9175 -- ============================================================================= Christopher G. Holmes Me: holmes@chrysal.com Chrysalis Research Corporation Inquiries: info@chrysal.com 52 Domino Drive Voice: 508-371-9115Article: 2840
In article <311bcc22.274923224@news.jf.intel.com> you write: >>>Is floating point important or because current FPGAs don't have floating point >>>structures do we just through up our hands and keep to integer math? >Add an FPU co-processor slave, and save the FPGA real-estate for more >important stuff. Absolutely. > >> What will it take to get reconfigurable computing off the ground? >The reconfigurable FPGA JAVA processor. Say, what about modifying >Phil Friedin's small RISC into a JAVA interpreter? Where do I get a spec so I can start on this. (at least half serious). Maybe just a sw interpretor running on the existing R16 would be fine. Do Java interpretors tend to be big or small (i.e. lines of C). > >More importantly Steve, and the whole point of this followup, what >kind of beer are you going to bring to FCCM'96 this year? And what >shall I bring down from Portland? :-) > >--Richard Vireday I have every intention of being there this year too. I will bring some iced tea. Philip Freidin.Article: 2841
Andreas Hofmann <ftdanho@ftd.ericsson.se> wrote: >Rerouting with locked pinout is possible with ALTERA if you have done the >pinout well. That means that you have to do something like a >floorplanning to >determine your pinout. This is even reasonable if you don't want to >change the pinout. Using Adreas's methodology is also very important with Xilinx devices. Floorplanning not only improves the ability to do rerouting, but it also improves the routed timing of the device. I have found that Actel devices seem to have more robust routing resources than Xilinx and Altera. The last time I used their tools, Actel didn't even provide the user the ability to do floorplanning or hand routing. Yet I was still able to get >90% utilization with multiple reroutes for small design changes. I let the tool set the pinout only the first time I routed. Next time, I plan to let the tool show me where it thinks the pins should go. Then I will try adjusting the pinout slightly for a more PCB-layout friendly pin ordering and see if the tools can reroute with my pinout locked in. Greg Peek | The opinions expressed are greg_peek@ccm.jf.intel.com | my own, who else would claim them?Article: 2842
CALL FOR PAPERS
* ENGINEERING COMPLEX COMPUTER SYSTEMS *
Thirtieth Annual
HAWAII INTERNATIONAL CONFERENCE ON SYSTEMS SCIENCES
HICSS - 30
Maui, Hawaii, January 7-10, 1997
Papers are invited for the Minitrack on ENGINEERING COMPLEX COMPUTER SYSTEMS
as part of the Advanced Technology track at the Hawaii International
Conference on System Sciences (HICSS).
1. PURPOSES
Modern computer systems and applications embody many different
characteristics and properties that are currently addressed, studied, and
optimized independently. Nevertheless, although it is of basic importance to
focus on these aspects independently, as a whole these properties feature a
complex interrelationship, and thus a higher-level view of the complete
project becomes mandatory.
While perhaps some of the earlier computer systems could be described,
designed and implemented with a particular focus on one objective (such as
fault-tolerance or timeliness), or using a single method (such as Structured
Programming), it is very questionable whether such modern and future
applications can be. Nowadays almost all electronic products are becoming more
and more software based: complex computer systems are becoming common in many
sectors, such as manufacturing, communications, defense, transportation,
aerospace, hazardous environments, energy, health care, etc. These systems
feature a number of different characteristics (such as distributed processing,
heterogeneous computational paradigms, high speed networks, novel bus systems,
or special-purpose hardware enhancements in general) and performance
requirements (such as real-time behavior, fault tolerance, security,
adaptability, development time and cost, long life concerns). The concurrent
satisfaction of the systems requirements have a considerable impact on the
hardware characteristics and vice-versa. The analysis of the complete project,
as a whole, is a major point in the design of the computer system itself and
plays a basic role throughout the entire system life.
The ECCS Minitrack will bring together industrial, academic, and
government experts from these various disciplines, to determine how the
disciplines' problems and solution techniques interact within the whole
system. Researchers, practitioners, tool developers and users, and technology
transition experts are all welcome.
2. ADDRESSED TOPICS:
Papers are solicited on all major aspects of ECCS including specifying,
designing, prototyping, building, testing, operating, maintaining, and
evolving of complex computer systems, including:
* Software engineering, re-engineering, reverse engineering
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* Highly heterogeneous, distributed and parallel platforms
* Case studies and project reports
3. MINITRACK COORDINATORS
Alberto Broggi Alexander D. Stoyenko
Dip. Ingegneria dell'Informazione Real-Time Computing Laboratory, CIS
Universita` di Parma New Jersey Institute of Technology
I-43100 Parma, Italy Newark, New Jersey 07102 USA
Fax: +39 - 521 905723 Fax: (201) 596-5777
Email: broggi@CE.UniPR.IT Email: alex@vulcan.njit.edu
Papers should be submitted to:
Alberto Broggi
HICSS'97 ECCS Coordinator
Dipartimento di Ingegneria dell'Informazione
Universita` di Parma, Viale delle Scienze
I-43100 Parma, Italy
4. FURTHER AND UP-TO-DATE INFORMATION:
Further information about the ECCS Minitrack are available at the
following WWW address:
http://WWW.CE.UniPR.IT/hicss/eccs
* INSTRUCTIONS FOR SUBMITTING PAPERS:
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4. The first page of the paper should include the title and a 300-word
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* DEADLINES:
March 15, 1996: Abstracts submitted to track coordinators for guidance and
indication of appropriate content. Authors unfamiliar with HICSS or those
who wish additional guidance are encouraged to contact any coordinator to
discuss potential papers.
June 1, 1996: Full papers submitted to the appropriate track, or
minitrack coordinator.
August 31, 1996: Notification of accepted papers mailed to authors.
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November 15, 1996: All other registrations must be received. Registrations
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* CONFERENCE PROCEEDINGS:
The conference Proceedings are published and distributed by IEEE Computer
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The ENGINEERING COMPLEX COMPUTER SYSTEMS Minitrack is part of the Advanced
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Article: 2843On Sat, 10 Feb 1996, HIKIMA Toshio wrote: > Hi FPGAers, > > I am using Xilinx XC4013. By the databook it is not specified > minimum delay. > My rep said, " there is no specificaton about minimum delay". Is it right? > > If true, how can I design DRAM I/F? DRAM's spec has many complex onstraient > so that it should be used minimum delay value. No minimums. If you have an asynchronous design which really requires min delays, try asking your Xilinx representative if a Speeds File exists for a very fast, possibly unnanounced, possibly hardwired part. It may well be safe to assume that the typical or max delays of such a part represent practical 3-4 sigma minimums of parts to be offered for 2-3 years. Clearly, you will have to know a bit about Xilinx's plans to have confidence in this! Very likely Xilinx prefers not to specify minimums to allow freedom for process improvements -- just like every other manufacturer of other than consumer Si. -- Bill Clark, wclark@clark.com, Clark Associates, Inc. +1303 444 1890Article: 2844
I spoke with a rep & they said that even if you order a slow speed part you may very well receive a faster one if it's in inventory. They also said that process changes occur rapidly and that Xilinx only attempts to meet the max specs & doesn't care about min specs. Peter Wurbs (pwu@maz-hh.de) wrote: : In article 100000@perth.DIALix.oz.au, Tony Clark <tonyc@perth.DIALix.oz.au> () writes: : >On Sat, 10 Feb 1996, HIKIMA Toshio wrote: : > : >> Hi FPGAers, : >> : >> I am using Xilinx XC4013. By the databook it is not specified : >> minimum delay. : >> My rep said, " there is no specificaton about minimum delay". Is it right? : >> : >> If true, how can I design DRAM I/F? DRAM's spec has many complex constraient : >> so that it should be used minimum delay value. : >> : >> Thanks, : >> -- : >> T.Hikima : >> : >> : >You really need to simulate after working out the delays due to routing : >etc. I'm not a Xilinx user yet, but thats the impression I get from : >looking at the Databook... : > : Even the post layout simulation does not include Min-Delays. : If you generate a SDF-File from the LCA-File it only includes : Max-Delays. : Bye, : Peter. : --------------------------------------------------------- : Peter Wurbs (MAZ Hamburg GmbH, Dep. Broadband Communication) : e-Mail: pwu@maz-hh.de : ---------------------------------------------------------Article: 2845
>>>>> "Philip" == Philip Freidin <fliptron@netcom.com> writes:
Philip> In article <311bcc22.274923224@news.jf.intel.com> you
Philip> write:
>> The reconfigurable FPGA JAVA processor. Say, what about
>> modifying Phil Friedin's small RISC into a JAVA interpreter?
Philip> Where do I get a spec so I can start on this. (at least
Philip> half serious). Maybe just a sw interpretor running on the
Philip> existing R16 would be fine. Do Java interpretors tend to
Philip> be big or small (i.e. lines of C).
You'll want a processor for the Java bytecode. BTW, Sun's already
working on that (not FPGA), supposedly to put them into their internet
terminals. Specs can be ordered from Sun; if you're only half
serious, so you don't want to license Java, the stuff on their
http://java.sun.com/ might do.
--
Achim Gratz
--+<[ It's the small pleasures that make life so miserable. ]>+--
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 4575 - 325
Article: 2846Dear Sir I have suspect that in future 5 jears ASIC and full cust. would have full advantage in field MP or DSP implantation (more as 100 000 gater) Alsow a standard 64-bit MP -MIPS 4660 have today a price smaller as FPGA (28 $ ) In GaAs field ASIC have not competition from FPGA. Some comment wilcome .Please post me.Article: 2847
Hi! I am strongly interested to find anyone who can answer me to this question: Is there a C function to convert binary decision trees to reduced ordered binary decision diagrams ? (In other words, ROBDD, BDD, ...). Please, if you know it, send me an e-mail. Thank you very much. ========================================================================== Juan A. Gomez Pulido email: jangomez@ba.unex.es Departamento Informatica fax: +34-27-257203 Universidad Extremadura tel: +34-27-257264 10071 Caceres Spain ==========================================================================Article: 2848
neal@ctd.comsat.com (Neal Becker) wrote: >I am just trying simulation on Altera for the first time. I want to >initialize some internal registers. Is Altera's simulator really not >capable of performing this basic function? I can't seem to find any >way to do this! Hopefully, you have used the global set/reset signal to initialize your registers/flip-flops. It's an external pin. It will make your simulation task more simple.Article: 2849
In <fliptronDMtsD6.HGq@netcom.com> fliptron@netcom.com (Philip Freidin) writes: >>> What will it take to get reconfigurable computing off the ground? >>The reconfigurable FPGA JAVA processor. Say, what about modifying >>Phil Friedin's small RISC into a JAVA interpreter? (Well, an FPGA based Java machine might not be dynamically reconfigured, so I'm not sure how this helps, except to glamourize processor implementations in FPGAs.) >Where do I get a spec so I can start on this. (at least half serious). >Maybe just a sw interpretor running on the existing R16 would be fine. >Do Java interpretors tend to be big or small (i.e. lines of C). The Java VM spec is at //java.sun.com/doc/programmer.html/... A good Java microprocessor should have a 32-bit datapath. XC4013Es not XC4005s... Java bytecodes are a cross between the Smalltalk-80 virtual machine bytecodes and Microsoft C compiler pcode. That is, 32-bit oriented, stack oriented, with a locals frame, constant pool, generically typed object instructions, plus several varieties of explicitly typed numeric opcodes (e.g. explicit iadd vs. ladd vs. fadd etc.). Requires a runtime object system providing object typing and garbage collection. A simple Java interpreter plus object system would be a few thousand lines of code. A good one would be much more sophisticated. (Folks interested in implementing Java VMs should go read the last third of "Smalltalk-80: The Language and Its Implementation", and most of "Smalltalk-80: Bits of History, Words of Advice". Plus look at Deutsch and Schiffman's Smalltalk-80 interpreter, Self, SOAR, and possibly the various hardware LISP implementations for ideas. And don't forget the ACM Architectural Support for Programming Languages and Operating Systems conferences' proceedings!) Many of the instructions are easy to do in hardware "at speed". On the other hand, many of the instructions, such as new, invokevirtual, putfield, athrow, or floating point, are more involved, and for those you would want to drop down to "microcode" to emulate. Which could mean that a microarchitecture with unaligned ifetch hardware, stack orientation, and possibly type tags (I'm still trying to understand if tags help) together with a fast underlying RISC datapath could be a good start. Or it might be exactly the wrong way to go! The fundamental design issue is how sophisticated is your download-time translation pass over the bytecodes, in order to canonicalize or regularize them? For example, a register file can emulate a frame + stack, so a translator which tracks stack contents can translate "iload local #1" "iload local #2" "iadd" "istore local #1" into "add r29, r29, r30". Too little canonicalization, and your microarchitecture is too complex. Too much, and congratulations, you have just written a Java-to-RISC optimizing compiler on top of a simple pipelined RISC. For Java, the SOAR approach seems pretty good. Translate to a RISC-like instruction set, probably once, at code download time. (I'm not sure there is much value to *dynamic* Java bytecode translation, and therefore it probably doesn't justify much/any hardware assist. A little dynamic in-line self-modifying code might be apropriate, however!) Then add additional hardware to accelerate tag checks, putfield GC space testing (e.g. for remembered sets), frame management, or whatever else takes up the time. I used to worship the Alto and Dorado architects. Now FPGAs put their tools (and more) into my hands, our hands. Who needs ECL and microwire when we have LUTs and PIPs? Ha ha ha ha ha ha ha! Jan Gray Redmond, WA
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