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_______________________________________________________________________
Abstract Due: 8 April 96
CALL FOR PAPERS Manuscript Due: 26 August 96
Presentation: 18-22 November 96
_______________________________________________________________________
Reconfigurable Technology for Rapid Product Development & Computing
Part of SPIE's International Symposium
VOICE, VIDEO and DATA COMMUNICATIONS
PHOTONICS EAST
18-22 November 1996, Hynes Convention Center,
Boston, Massachetts USA
-----------------------------------------------
Many systems engineers are overcoming current computation and product
development bottlenecks through the use of reconfigurable device
technologies, such as user-programmable FPGA and CPLD devices. This
conference focuses on two areas utilizing reconfigurable technology:
1) Rapid Product Development
2) Reconfigurable Computing
Today's reconfigurable devices can be used for datapath and data
processing applications, as well as general logic replacement. Processors
built from reconfigurable logic devices are being applied to a wide
range of computationally-intensive tasks.
This conference will present papers that illustrate applications and
techniques for using reconfigurable technology in the design and
manufacturing cycles, as well as high-performance computing.
Papers are solicited in the following and related areas:
* reconfigurable digital and analog components and their
use in the product development cycle
* applications and platforms utilizing reconfigurable technology
for rapid product development and high-performance computing
* applications utilizing reconfigurable technology for image
and signal processing, communication and data processing
Conference Chairs: John Schewel, Virtual Computer Corp.
Peter M. Athanas, Virginia Polytechnic Institute & State University
V. Michael Bove, Jr. MIT Media Lab
Bradly K. Fawcett, Xilinx Inc.
This is the second year the conference on Reconfigurable Computing is
being held. Last year twenty two papers were presented ( 14 papers from
academia and 8 from industry) by authors from 7 countries. This conference
is the first of it's kind outside the traditional FPGA community and serves
as an opportunity to introduce newcomers to this arena.
Last years papers were published by SPIE and the Proceedings can be ordered
from them (Volume 2607) tel. (360)-676-3290. Proceedings from this conference
will be published and available at the conference. For this reason the
manuscript due dates must be observed.
Being held in Boston this year, Photonic East has a track record of
attracting 4000+ engineers, developers and scientists from all over
the world.
INSTRUCTIONS FOR SUBMISSION
On-site Abstracts due 8 April 1996 On-site Manuscripts due 26 August 1996
1. Submit To: Conference Title & Chair
2. Abstract Title
3. Author Listing (principle author first) First, Last, Affiliation, mailing
address, telephone, fax, email
4. Presentation will be Oral Presentation at the conference
5. Abstract Text Aprox. 250 words.
6. Keywords (max five)
7. Brief Biography of principle author (aprox. 50 words)
To be considered for acceptance please use only ONE of the following methods:
SPIE WEB - Complete the form found at:
http://www.spie.org/web/meetings/calls/submissions.html
E-MAIL - Submit in ASCII form (not encoded) to:
abstracts@spie.org ( Subject: PE96 (John Schewel) )
POST - SPIE, PO Box 10, Bellingham WA 98227-0010 USA
or/ 1000 20th St. Bellingham, WA 98225 USA
FAX - 360/647-1445 (telephone) 360/676-3290
Abstracts should contain enough detail to clearly convey the approach and
the results of the research.
Applicants will be notified of acceptance before August 26, 1996.
Authors and co-authors are accorded a reduced symposium registration fee.
John Schewel, the Conference Chair maybe contacted at jas@vcc.com for
further information.
Article: 2851
I was reading that SUN has 3 JAVA processors in mind:
picojava, microjava and ultrajava. The picojava processor
was (from what I remember) 2mm square so should should
fit into an FPGA. As for the beer we will have 2 beers
a red beer and maybe a bitter. I've been brewing for 16
years and designing reconfigurable computer systems for
10. Currently I'm working on a input method that uses C
(but is NOT a hardware C).
#include <stdio.h>
#include "xc4000.h"
main () {
FILE *outfile;
/* opens the output file outfile can be used by a fprintf
to help in debugging */
outfile = (FILE *) open_outfiles("xnf/test.xnf", "4013MQ208-4");
/* Sets the add/addsub geometry to carry chain up can be set to down or to
use the carry chain along the edge */
setaddgeom(1);
/* moves a hardware pointer for exact placement */
mvhwptr(4,1);
/* equations entered in the same format as you see in exact */
eqn("a*b = c",FMAP);
eqn("~(a + b) = d",GMAP);
eqn("(c + ~d * feedback) = e",HMAP);
/* defines a flip-flop and places in the FFX position */
dff("ffin","ffout",NO_SIG,NO_SIG,"sclk",FFX,RESET);
dff("ffin","feedback",NO_SIG,NO_SIG,"sclk",FFY,RESET);
/* uses a subroutine to place ios. */
do_my_ios();
mvhwptr(10,1);
/* creates a subtractor carryout starts at row 1 col 10 */
addsub("a<3:0>","b<3:0>","c<3:0>",NO_SIG,"carryout","over",GND);
/* closes the outputfile you could open and start another design after this */
close_outfiles();
}
do_my_ios(){
/* does and ibuf at P15 with no attributes */
ibuf("a<0>","P15",0);
ibuf("a<1>","P16",0);
ibuf("a<2>","P17",0);
ibuf("a<3>","P18",0);
ibuf("b<0>","P19",0);
ibuf("b<1>","P20",0);
ibuf("b<2>","P21",0);
ibuf("b<3>","P22",0);
obuf("c<0>","P23",0);
obuf("c<1>","P24",0);
obuf("c<2>","P27",0);
obuf("c<3>","P28",0);
obuf("carryout","P29",0);
obuf("over","P30",0);
ibuf("a","P11",0);
ibuf("b","P12",0);
obuf("e","P13",0);
ibuf("ffin","P9",0);
obuf("ffout","P10",0);
gclk("sclk","P57");
}
This gets complied by a C complier when you execute the program out comes an XNF.
This allows one to use SCCS or any kind of software control program to keep track
of design changes. Also one could use C "for loops" or "while loops" to generate
hardware designs. But it really allows the user to place everything (almost forces)
exactly. While you can place everything in other systems it seems to be an after
thought. Subroutines of larger functions can be created and parameters passed
just like in C. It can be used as a backend to real hardware C compliers. Right
now you must place the add/addsub exactly while the eqns and dff can float. I
will soon put in support for RLOCS (although subroutines can be created that
get passed global row-column info).
Steve Casselman
Virtual Computer
Article: 2852In article <DMurzL.EpH@world.std.com>, tartis@world.std.com (Tad B Artis) wrote: > I spoke with a rep & they said that even if you order a slow speed part you Let me explain the problem with min specifications, and why all semiconductor manufactuers shy away from them: In CMOS technology, all delays decrease when the temperature is lowered and when the supply voltage is increased. Therefore, we test our devices at a high temperature (85 degrees C junction temperature ) and a low supply voltage ( 4.75 V for 5-V commercial parts ). If we call this specified and guaranteed delay 100%, how short can it be "best case"? Let us subtract 10% for tester guardband ( we always test tighter than we promise, in order to avoid disagreements over tester calibration. 10% may be ultra-conservative, but 5% would be aggressive ) Then we subtract 10% for the difference between 4.75 V test, and 5.25 V best case supply voltage. Then we subtract 25% to 30% for the difference between 85 degr. test, and 0 degree best case junction temperature. Then we subtract 40% for the difference between our slowest processing and fastest processing. We can catch some of that by speed-binning, but - as mentioned before- all manufacturers takes the liberty of "down-binning", i.e. shipping a faster part against an order for a slower part. Multiply 0.9 x 0.9 x 0.7 x 0.6 and you get 0.34 That means, you can expect to get a best-case delay of about a third of the specified value. And the difference is even larger for industrial and military parts, and also larger when we consider processing improvements from year to year. For any given parameter, we suggest that you assume a best-case value of 25% of the number that we specify for the same parameter at the fastest available speed grade. Thus, for the top-of-the-line fastest part, the ratio between worst- and best case delay is 4:1, for slower parts it is a larger ratio. Internal to the chip, we guarantee that min delays will never cause hold-time problems. Let me repeat the old saying: Design synchronously, whenever possible. A synchronous design is inherently insensitive to min delays. Peter Alfke, Xilinx ApplicationsArticle: 2853
In article <peter-1602961419210001@appsmac-1.xilinx.com>, peter@xilinx.com (Peter Alfke) writes: [much good stuff snipped] > Let me repeat the old saying: Design synchronously, whenever possible. A > synchronous design is inherently insensitive to min delays. I think that's an overly strong statement, although it is correct if you are only talking about a design within a single Xilinx chip. In general, you have to consider min delays if you have clock skew or positive hold times.Article: 2854
What is in <4000.h>?
In article <1996Feb16.204851.23026@super.org>
sc@vcc.com "Steve Casselman" writes:
>> I was reading that SUN has 3 JAVA processors in mind:
>> picojava, microjava and ultrajava. The picojava processor
>> was (from what I remember) 2mm square so should should
>> fit into an FPGA. As for the beer we will have 2 beers
>> a red beer and maybe a bitter. I've been brewing for 16
>> years and designing reconfigurable computer systems for
>> 10. Currently I'm working on a input method that uses C
>> (but is NOT a hardware C).
>>
>>
>> #include <stdio.h>
>> #include "xc4000.h"
>>
>>
>>
>> main () {
>>
>> FILE *outfile;
>>
>> /* opens the output file outfile can be used by a fprintf
>> to help in debugging */
>>
>> outfile = (FILE *) open_outfiles("xnf/test.xnf", "4013MQ208-4");
>> /* Sets the add/addsub geometry to carry chain up can be set to down or to
>> use the carry chain along the edge */
>> setaddgeom(1);
>> /* moves a hardware pointer for exact placement */
>> mvhwptr(4,1);
>> /* equations entered in the same format as you see in exact */
>> eqn("a*b = c",FMAP);
>> eqn("~(a + b) = d",GMAP);
>> eqn("(c + ~d * feedback) = e",HMAP);
>> /* defines a flip-flop and places in the FFX position */
>> dff("ffin","ffout",NO_SIG,NO_SIG,"sclk",FFX,RESET);
>> dff("ffin","feedback",NO_SIG,NO_SIG,"sclk",FFY,RESET);
>> /* uses a subroutine to place ios. */
>> do_my_ios();
>> mvhwptr(10,1);
>> /* creates a subtractor carryout starts at row 1 col 10 */
>> addsub("a<3:0>","b<3:0>","c<3:0>",NO_SIG,"carryout","over",GND);
>> /* closes the outputfile you could open and start another design after this */
>> close_outfiles();
>> }
>>
>>
>> do_my_ios(){
>> /* does and ibuf at P15 with no attributes */
>> ibuf("a<0>","P15",0);
>> ibuf("a<1>","P16",0);
>> ibuf("a<2>","P17",0);
>> ibuf("a<3>","P18",0);
>> ibuf("b<0>","P19",0);
>> ibuf("b<1>","P20",0);
>> ibuf("b<2>","P21",0);
>> ibuf("b<3>","P22",0);
>> obuf("c<0>","P23",0);
>> obuf("c<1>","P24",0);
>> obuf("c<2>","P27",0);
>> obuf("c<3>","P28",0);
>> obuf("carryout","P29",0);
>> obuf("over","P30",0);
>> ibuf("a","P11",0);
>> ibuf("b","P12",0);
>> obuf("e","P13",0);
>> ibuf("ffin","P9",0);
>> obuf("ffout","P10",0);
>> gclk("sclk","P57");
>> }
>>
>>
>> This gets complied by a C complier when you execute the program out comes an
>> XNF.
>> This allows one to use SCCS or any kind of software control program to keep
>> track
>> of design changes. Also one could use C "for loops" or "while loops" to
>> generate
>> hardware designs. But it really allows the user to place everything (almost
>> forces)
>> exactly. While you can place everything in other systems it seems to be an
>> after thought. Subroutines of larger functions can be created and parameters
>> passed
>> just like in C. It can be used as a backend to real hardware C compliers. Right
>> now you must place the add/addsub exactly while the eqns and dff can float. I
>> will soon put in support for RLOCS (although subroutines can be created that
>> get passed global row-column info).
>>
>>
>> Steve Casselman
>> Virtual Computer
>>
Article: 2855
In article <4g1cje$gov@ite123.inf.tu-dresden.de> gratz@ite.inf.tu-dresden.de (Achim Gratz) writes:
>>>>> "Philip" == Philip Freidin <fliptron@netcom.com> writes:
Philip> In article <311bcc22.274923224@news.jf.intel.com> you
Philip> write:
>> The reconfigurable FPGA JAVA processor. Say, what about
>> modifying Phil Friedin's small RISC into a JAVA interpreter?
Philip> Where do I get a spec so I can start on this. (at least
Philip> half serious). Maybe just a sw interpretor running on the
Philip> existing R16 would be fine. Do Java interpretors tend to
Philip> be big or small (i.e. lines of C).
You'll want a processor for the Java bytecode. BTW, Sun's already
working on that (not FPGA), supposedly to put them into their internet
terminals. Specs can be ordered from Sun; if you're only half
serious, so you don't want to license Java, the stuff on their
http://java.sun.com/ might do.
What sort of specs are available. The stuff originally at java.sun was laughable,
you couldn't even tell for sure that they were building a processor and not
reusing a sparc core with custom ROMs. Details of any sort would be interesting.
Bill
Article: 2856I'm looking for the lowest power PLD I can find. Speed isn't much of an issue, 25ns or so is fine for my simple combinitorial products. My state machines will be simple and no faster than 20MHz. Basicly all I'm going to do is generate a bunch of chip selects on a low speed bus. A Xilinx XC2064 would be over kill. I'd use one if it didn't use so much power. Then there is the 3.3 volt problem. Cost is not an issue. An pointers or horror stories welcome. To make it worth your while, I'll offer a bin full of XC2018's to whomever can point me in the right direction. rick@ratio.com Rick Farmer | Ratio DesignLab Electrical Engineer | 3040 Peachtree Rd. rick@ratio.com | Atlanta, Ga. 30305 USAArticle: 2857
-- takashi@hpcc01.corp.hp.com (Takashi Hidai) wrote:
>I am having a problem to translate my FPGA design to an ASIC.
>Basically, I am giving the original XNF files created from the
>WIR netlist by wir2xnf command. Then the ASIC vendor was having a
>difficulty to translate to their format since I am using a lot of
>Xilinx XBLOX libraries. According to a suggestion I've got from
>Xilinx guy, I changed to give a different xnf file created from
>LCA file by lca2xnf. Then, the ASIC vendor found another problems.
>The problems are timing violation and unproper optimization.
>I would like to hear the absolute solution for these chaos.
>Can anyone give me a great suggenstion ??
One other solution is a Xilinx technology called HardWire. Xilinx
can take your design and create a 100% pin- anf function-compatible
device that drops into the same socket as your FPGA device.
Xilinx does the migration work. You do not need test or simulation
vectors like you would with a third-party ASIC house. Basically, you
only have to design once and Xilinx takes care of the rest.
Depending on the production volume, HardWire devices approach ASICs
prices, especially when you consider fault-coverage and conversion
time.
Also, the HardWire devices are manufactured at the same production
foundary as Xilinx FPGAs. If your production line has qualified
Xilinx FPGAs, then they have essentially also qualified the HardWire
devices.
Just contact me by return E-mail and I'll make sure to get the right
person in contact with you.
=====================================================================
_
/ /\/ Steven K. Knapp E-mail: stevek@xilinx.com
\ \ Corporate Applications Mgr. Tel: 1-408-879-5172
/ / Xilinx, Inc. Fax: 1-408-879-4442
\_\/\ 2100 Logic Drive Web: http://www.xilinx.com
San Jose, CA 95124
=====================================================================
Article: 2858
Xilinx offers two CPLD devices with 5 ns Tpd.
The XC7318 device has 18 macrocells and is available in 44-pin
packaging.
The XC7336 device has 36 macrocells and is also available in 44-pin
packaging.
Please contact the local Xilinx sales office at (408) 245-9850 or
please send a return E-mail with your phone number. Thank you.
--
=====================================================================
_
/ /\/ Steven K. Knapp E-mail: stevek@xilinx.com
\ \ Corporate Applications Mgr. Tel: 1-408-879-5172
/ / Xilinx, Inc. Fax: 1-408-879-4442
\_\/\ 2100 Logic Drive Web: http://www.xilinx.com
San Jose, CA 95124
=====================================================================
Article: 2859
>
>Peter Wurbs (pwu@maz-hh.de) wrote:
>: In article 100000@perth.DIALix.oz.au, Tony Clark <tonyc@perth.DIALix.oz.au> () writes:
>: >On Sat, 10 Feb 1996, HIKIMA Toshio wrote:
>: >
>: >> Hi FPGAers,
>: >>
>: >> I am using Xilinx XC4013. By the databook it is not specified
>: >> minimum delay.
>: >> My rep said, " there is no specificaton about minimum delay". Is it right?
>: >>
>: >> If true, how can I design DRAM I/F? DRAM's spec has many complex constraient
>: >> so that it should be used minimum delay value.
>: >>
>: >> Thanks,
>: >> --
>: >> T.Hikima
>: >>
>: >>
>: >You really need to simulate after working out the delays due to routing
>: >etc. I'm not a Xilinx user yet, but thats the impression I get from
>: >looking at the Databook...
>: >
>
>
>: Even the post layout simulation does not include Min-Delays.
>: If you generate a SDF-File from the LCA-File it only includes
>: Max-Delays.
>
>
>: Bye,
>
>: Peter.
>
>: ---------------------------------------------------------
>: Peter Wurbs (MAZ Hamburg GmbH, Dep. Broadband Communication)
>: e-Mail: pwu@maz-hh.de
>: ---------------------------------------------------------
>
(This is an experiment. I'm trying to learn to use the news groups
and this is a good question.)
*Ideally you have a very high speed clock such as 66Mhz to use and RAMs
which match well to the clock rate in terms of timing. If the clock
does not match up well, then tricks such as using the clock to gate a
signal can be used, as well as both edges of the clock. When the clock
is at the same rate as the data rate, such tricks need to be used to
generate such signals as CAS and RAS. The most important spec for the
FPGAs is not the min delay but the tracking delay. Xilinx refers to the
tracking delay, in several places in their app notes, but does not
guarantee it in the data sheets. Xilinx states that the tracking delay
is 70% which means (as I understand it) that if one path of delay is at
max delay, no other path will be faster that 70% of the max delay
for that path.
For example if we have 2 paths that generates CAS and they both have a
delay of 18 ns, we can use tracking to guarantee that CAS has a min high
time of 10 ns.
reg1 -|path1|------|\
|&>--|>---CAS
reg2 -|path2|------|/
max delay path1 = 18ns
min delay path2 = 18*.70=12ns
clock ___/~~~\___/~~~\___/~~~\___
reg1 ___/~~~~~~~\_______/~~~~~~~\____
reg2 _______/~~~~~~~\_______/~~~~~~\____
CAS _______/~~~\___________/~~~\_____
->| |<-Tcp
Tcasmax = 18ns
Tcasmin = 12ns
Tcpmin = 10ns = .5 Tclock + Tcasmin - Tcasmax ;
(spec) 10ns = .5 * Tclock + 12ns -16ns
16ns = .5 * Tclock
Tclock = 32ns
What this says is that the minimum clock period necessary to guarantee
a 10 ns CAS hi time is 16ns. This is the type of derivation I typically
use to deal with real devices such as DRAMS. Note that I had to use a
non guaranteed spec (tracking). I really don't know if this is legal!!
Note that Min delays could be used instead. In this case Tcasmin
would be 0ns (from data sheets) and the clock period would be
56ns instead of 32ns. 56ns=2*(10ns+18ns-0ns). Using a 20% min delay
the min clock period would be 48ns=2*(10ns+18ns-4ns).
Im going to try to post this now, I hope this helps.
Brad Taylor (blt@emf.net)
Article: 2860Rick Farmer wrote: > > I'm looking for the lowest power PLD I can find. Speed isn't much of an > issue, 25ns or so is fine for my simple combinitorial products. My state > machines will be simple and no faster than 20MHz. Basicly all I'm going to > do is generate a bunch of chip selects on a low speed bus. A Xilinx XC2064 > would be over kill. I'd use one if it didn't use so much power. Then there is > the 3.3 volt problem. Cost is not an issue. An pointers or horror stories > welcome. To make it worth your while, I'll offer a bin full of XC2018's to > whomever can point me in the right direction. ICT makes a low power EEPROM based 22V10 (2mA typ @ 3.3V for a 1MHz 10-bit counter). Vcc = 2.7-3.6V Tpd = 25ns I've done XC3020L designs that run at 3-4mA @ 3.3V with a few FF's running as fast as 20MHz. Regards, ScottArticle: 2861
>>>>> "Bill" == Bill Mangione-Smith <billms@nixon.icsl.ucla.edu> writes:
Bill> What sort of specs are available. The stuff originally at
Bill> java.sun was laughable, you couldn't even tell for sure that
Bill> they were building a processor and not reusing a sparc core
Bill> with custom ROMs. Details of any sort would be interesting.
I meant specs for the Java language, the virtual machine and the
bytecode. These cannot be too bad, because there's already another
Java compiler named Espresso, that is said to be twice as fast
(compiling, I assume, have to get that one myself yet).
As for the processors, the only thing I heard was they'll call them
MicroJava, SuperJava and UltraJava; now you guess what they'll do. I
would think they'll put in some spare transistors to microcode the
Java virtual machine. I might be completely wrong though, and the
micro, super and ultra prefixes are just marketing labels attached to
make them look like the line of SparcStations.
--
Achim Gratz
--+<[ It's the small pleasures that make life so miserable. ]>+--
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 4575 - 325
Article: 2862
sc@vcc.comß wrote:
> Currently I'm working on a input method that uses C
> (but is NOT a hardware C).
> [ example deleted ]
If you used C++, you could overload operators so that equations can be
entered just like normal equations:
A=B+C;
FFD(CLK,RS,CKE) = /A * (B+C);
Or, you might be able to create a := operator so that DFF's are also
natural.
I already have a dis-assembler for this which takes an .LCA (X4000) or
.NCD (ORCA) file and lists it as equations. Here's an example output
for an ORCA file. Each block is represented as a paragraph. Common
control signals (Clock,enable, etc. are in [] at the end of each paragraph.)
Note that it disassembles the ORCA FFMUX into the C language A?B:C syntax.
IN0/COM2:= EXP1 ? {EX2} : {(EX4*EXP0)+(EX3*/EXP0)}
IN0/COM1:= EXP1 ? {EX1} : {(EX3*EXP0)+(EX2*/EXP0)}
IN0/COM0:= EXP1 ? {EX0} : {(EX2*EXP0)+(EX1*/EXP0)}
[CLK=CLK CE=COM_END (GSR): R3 #2 R1 R0]
IN0/AD0$8=/ADR1*/ADR2*/ADR3
IN0/ADF$2=(ADR0*ADR1)*ADR2*ADR3
IN0/DQ29:=RAM[ADR3 ADR2 ADR1 ADR0]= Din=OUT29 WE=WPULSE$4
IN0/DQ28:=RAM[ADR3 ADR2 ADR1 ADR0]= Din=OUT28 WE=WPULSE$4
[CLK=CLK CE=/POP0- (GSR): #3 #2 #1 #0]
IN0/ADR3:=CNTUPDN(ADR3, 0, Cout=)
IN0/ADR2:=CNTUPDN(ADR2, 0)
IN0/ADR1:=CNTUPDN(ADR1, 0, ADD/SUB=PUSH)
IN0/ADR0:=CNTUPDN(ADR0, 0, Cin=POP0-)
[CLK=CLK CE=1 SYNC=0: S3 S2 S1 S0]
IN0/COM/SLOG1=ROM[S4 S3 S2 S1 S0]=0xFC1E1E1C
IN0/COM/SLOG0=ROM[S4 S3 S2 S1 S0]=0xE3199992
IN0/QIN5:=DIN5
IN0/QIN4:=DIN4
IN0/QIN3:=DIN3
[CLK=CLK CE=IDAV ASYNC=0: R3 R2 R1 #0]
Also, I have extended the Viewlogic schematic entry to allow equations
to be entered directly on the schematic page in a similar format. It would
be a piece of cake to convert these tools to scan your C syntax instead
of viewlogic .WIR files.
Article: 2863In article <4g3l9r$1fq@src-news.pa.dec.com>, murray@pa.dec.com (Hal Murray) wrote: > In general, you have to consider min delays if you have clock skew or > positive hold times. Agreed. That's why Xilinx inputs have an added delay ( optional in XC4000 ) that guarantees that there is no data hold time even on the chip input. For the XC4000 families, Xilinx also specifies guaranteed pin-to-pin parameters, including set-up and hold times between data and clock inputs. Keeping clock skew between chips close to zero is the obligation of the systems designer. I assume everybody knows that clock skew in a direction opposite to the data flow is safe, only sacrifices performance. Peter Alfke, Xilinx ApplicationsArticle: 2864
No doubt this would make a FAQ if this newsgroup had one: I'm trying to decide between Verilog and VHDL for FGPA design now and possible ASIC design in the future. Does anyone know of any articles or reports that compare the two? Preferably something less biased than an article by a company with an interest in either... -- Fred Fierling fff@microplex.com Tel: +1 604 444-4232 Microplex Systems Ltd http://microplex.com/ Tel: +1 800 665-7798 8525 Commerce Court Fax: +1 604 444-4239 Burnaby, BC V5A 4N3Article: 2865
EE Times had a short, but informational article a couple of months back comparing VHDL and Verilog syntax. As I recall there was about an 80% eqivalence between the two - that is functions that could be done pretty much the same with differering syntax in both languages. They even summarized it in a nice table that's sitting at my desk at work.. As you may have noticed, there are a lot of people that get real emotional about this issue! RickArticle: 2866
In article <rfarmer.98.01C0432A@mindspring.com>, rfarmer@mindspring.com (Rick Farmer) wrote: > I'm looking for the lowest power PLD I can find. The 3.3-V XC2064L, has a static Icc consumption of only 20 microamps worst-case. Actual power consumption in your system then depends on the speed of your clock, and the number of active nodes and their respective frequency. If you worry about the Icc used by the SPROM, there is a simple way to reduce that to zero ( well, let's call it less than one microamp.) EPLD tend to have much higher static current consumption, and even antifuses tend to have higher leakage currents. And the XC2064 is by far the smallest SRAM-based programmable device in the industry. You will be hard pressed to find any other programmable device using less power. What is your power budget? Peter Alfke, Xilinx Applications, e-mail: peter@xilinx.comArticle: 2867
Hello, Could someone please tell me the status of the Xilinx 8100 "Sea Of Gates" FPGAs? Are these parts available? Will the current XACT software be used for these parts or is there another software package which must be used - If so, can XACT be "upgraded" ?? I have read that these FPGAs yield excellent routing when used with logic synthesis (e.g. VHDL), and I am interested in any feedback / information. Thanks, Edward Leventhal Omitron, Inc. 6411 Ivy Lane Suite 600 Greenbelt, MD 20770 (301) 474-1700Article: 2868
We are looking for major areas of FPGA usage and their share in the industry specifically for the following areas: (i) Glue logic (ii) Rapid prototyping (iii) Custom computing or FPGA-based computing (iv) Any other If you would like to add other application areas of FPGAs, please feel free to do so. Any pointer to the info will be highly appreciated. Nalini RathaArticle: 2869
bob, thanks for your reply. i was not aware that exemplar had built their own xilinx vital library. i belive they now share that distinction with cadence and summit design (i wonder when xilinx will be providing their version of their own vital libs ?!). larry lapides, who is associated with exemplar, had replied to one of my earlier posts concerning graphical hdl generators and has given me an overview of their products (as has our local exemplar rep). we're leaning towards using mentor's autologic II right now because we own a few AL2 licenses. i have not heard back from john murray (GEC-marconi) yet concerning my follow-up questions to his 2/12/96 reply to my original posting. at this point, i'm very concerned about the ability of xilinx's XACT 6.0 and/or XACT 5.2 to place/route an XC4025E device. i've been hearing some negative remarks concerning their so-called "version 1.0 pre-release" which is required for the XC4025E. -- ____________________________________________________________________________ Lance Gin "off the keyboard Delco Systems - GM Hughes Electronics over the bridge, OFC: 805.961.7737 FAX: 805.961.7329 through the gateway, C43LYG@dso.hac.com nothing but NET!" ____________________________________________________________________________Article: 2870
Note, that there are a number of "synchronous" bus spec's that mandate a non-zero hold time. Several members of the Intel processor family, and the PCI bus are typical examples. This makes the issue of minimum specified hold time particularly significant, for reliable operation. In the past, we have resorted to adding external buffers, or running doubled clock machines, where possible, to effectively pad the minimum delay, when PLD/FPGA vendors could or would not give a minima. As clock frequencies increase, and board real-estate diminishes, these padding or signal scheduling solutions becomes less and less practical, especially as the number of signals that must be managed grows. For my part, I will give extra weight, in component selection, to a PLD/FPGA vendor that can provide realistic minimum delay, over those that do not. == Tom Keaveny disclaimer " opinions are my own and not necessarily that of Hewlett Packard Co."Article: 2871
Initializing registers in the Max+Plus II simulator is actually quite easy. In the simulator window just select the initialize menu item. You can then automatically filter/list the desired registers and then select an initialization value. The one gotcha that often gets people is the use of an asynchronous reset at the same time that the initialization is occuring. The asynchrounous reset will override the initialization. Make sure that the asynchrounous reset is inactive during the initialization and you will be okay.Article: 2872
We are looking into a purchase of the reconfigurable computing boards from this company. Has anybody had any experience with them (good or bad) and with their products? What applications have been placed on these boards? We are investigating reconfiguable computing for use in scientific image processing and satalite data processing. thanks! mark -- mark stephens "In constraint, NASA GSFC Code 521 is freedom" Greenbelt, MD (301) 286-4269 mark.stephens@gsfc.nasa.govArticle: 2873
> > I'm looking for the lowest power PLD I can find.
This is a form about reconfigurable computing and not PLDs (or
one time burnable devices)
I think the Java thread is about reconfigurable computing in that
Java talks about virtual machines and these could be implemented as
FPGA based hardware objects. Below is a little SUN blurb about Java
processors comming out. I read that the pico Java will be 2mm square
this would fit in an 10,000 gate FPGA and the micro Java might fit in
a 40,000 gate FPGA. A good reconfigurable computing project would be
a JAVA to FPGA complier that could take the JAVA language and deside
what could go into hardware and what would be run in software. Then of
course design a machine that would speed up such a program:)
>
> You probably noted that even this thread degenerated into one about Java!
>
> I work for NASA and my task is to investigate the use of reconfigurable
> hardware for real time satalite image processing and scientific
> processing. Some of the questions you raise below are very dear to our
> hearts.
>
> This is especially true regarding fixed or floating point arithematic. We
> can't just throw up our hands as almost all the algorithms use some type
> of fixed/floating calculations. If reconfigurable hardware can't handle
> it (or handles it poorly), then the results of the investigation are
> negative. We'll give it a go though.
There are ways to do floating point in FPGAs. I estimate 3 MegaFlops/5000 gates
which would be 24 Mflops for a 40,000 gate device.
Steve Casselman
==============================================================================
SunFlash 86.02
Sun Unveils Java Processors
February 1995 John J. McLaughlin, Editor/Publisher flash@flashback.com
==============================================================================
Java Internet technology cast in low-cost processors and embedded
microcontrollers
SUNNYVALE, CA -- February 2, 1996 -- In a sweeping move designed
to reshape the economics of the microprocessor market, Sun
Microelectronics (formerly SPARC Technology Business), a division
of Sun Microsystems, Inc. unveiled today the industry's first
microprocessor family optimized for Java. The initial Java
processor offering includes a three-member product family, a core
licensing program, and an upcoming reference platform program.
With estimated application performance many times that of general
purpose processors at a fraction of the cost, Sun Microelectronics
officials estimate that the new class of low-cost Java processors
will lead to a networked microprocessor market topping $15 billion
by the year 2000.
----------------------------------------------------------------------------
"Java presents the microprocessor world with a new product paradigm -
simple, secure and small," stated Chet Silvestri, president of Sun
Microelectronics. "And our Java processors cast this paradigm in silicon."
"Java software, Java processors and Java systems are central to Sun's inter-
and intranet strategy," stated Scott McNealy, chairman and CEO of Sun
Microsystems, Inc. "Creating low-cost Java processors will take this
powerful technology directly to the consumer, and takes the consumer
directly into the new paradigm of network computing." Silvestri continued,
"Java processors extend our reach into the low-cost consumer and enterprise
marketplace. Sun Microelectronics will not only offer a full range of
Java-optimized component- and board-level products, we'll also license these
designs to third parties who can embed the technology into the wide range of
products that will be enabled by the rapid growth of the internet and Java."
"Industry analysts estimate that the overall microprocessor and
microcontroller market will top $60B by the year 1999," stated Rajesh
Parekh, Sun Microelectronics' Embedded Products Group vice president and
general manager. "Today the average business person harbours more than 10
microcontrollers. By 1999, the average home will contain between 50 and 100
microcontrollers. And worldwide there will be more than 145 million cellular
phone users -- each with at least one microcontroller. The result? Millions
of cellular phones, security systems, entertainment systems, low-cost
network terminals, and other internet appliances operating within a network
and highly optimized for small applications or applets running at top speed.
We believe that our Java processors can provide a more optimum solution in a
quarter of these applications."
"Java opens new doors for processor architecture. Our Java processors
capitalize on this opportunity by streamlining the architecture, increasing
parallelism and providing advanced 3D graphics operations," noted Anant
Agrawal, Sun Microelectronics' vice president of engineering. "And our
architectural strategy allows us to offer processors at price and
performance points for high-volume consumer and enterprise applications."
About picoJAVA-, microJAVA-, and UltraJAVA- The Java processor family
consists of three lines of microprocessors - picoJAVA, microJAVA and
UltraJAVA - that vary in price, performance and application.
The picoJAVA core is designed to be the industry's best price/performance
silicon design supporting the Java Virtual Machine specification. Licensing
of the low-cost core will enable sub $25 Java-optimized processors for
cellular phones, printers and other consumer and peripheral markets. The
first picoJAVA core is expected to be available in mid-1996 for industry
wide licensing.
The microJAVA chip-level products are based upon the picoJAVA core and add
application-specific I/O, memory, communications and control functions.
Targeted at both general-purpose and industry-specific markets, microJAVA
processors will range in price from $25 to $100. These chips will be ideal
for a broad range of network- based devices such as controllers and telcom
carrier equipment, as well as consumer products such as low-end games and
service stations (print/reservation/directory/mail centers). The first
microJAVA processors are expected to sample in the first quarter of 1997.
The UltraJAVA processor line will include the industry's fastest Java
processors. This line leverages advanced graphics circuits and features
next-generation enhancements of Sun Microelectronics' VIS instruction set.
UltraJAVA processors will target advanced 3D graphics and other
multimedia-intensive applications. Starting at $100, the first UltraJAVA
processors are expected to sample in late 1997.
About Java
The Java language is the result of several years of research and development
at Sun Microsystems, Inc. It is the first language to provide a
comprehensive, robust, platform-independent solution to the challenges of
programming for the Internet and other complex networks. Java features
portability, security and advanced networking without compromising
performance. Sun Microelectronics' traditional family of SPARC processors,
as well as processors of other architectures, will run Java software. By
optimizing the new Java processor family for Java-only applications, an
unprecedented level of price/performance will be reached.
Article: 2874In article <Dn3uCy.25v@icon.rose.hp.com>, tak@core.rose.hp.com (Tom Keaveny) wrote: > Note, that there are a number of "synchronous" bus spec's that mandate > a non-zero hold time. Please let me suggest a more careful noemnclature: "Hold-time" is not an OUTPUT characteristic, "Hold time" is always an INPUT requirement. A positive hold time means that input data is required to be "held" valid until after the active clock edge. "Propagation delay" or "clock-to-out" is the relevant OUTPUT specification. If two devices are directly interconnected, and share a common clock without any skew, then a positive hold-time requirement at the input can only be satisfied by a guaranteed minimum clock-to-out delay on the output that drives that input. That's why a positive hold-time requirement on a data input is so bad, and that's why Xilinx has added internal delay to increase the data set-up time so much that the pin-to-pin hold-time requirement on all inputs is never positive. As a result, you can take data away simultaneously with the clock, and still be sure that the old data is being clocked in. A minimum clock-to-out delay specification is then not needed. The actual, physically unavoidable shortest output delay acts as additionasl protection against clock-skew problems. Peter Alfke, Xilinx Applications.
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