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In article <idr.798883860@sycamore>, idr@ee.ed.ac.uk (Iain Rankin) writes: |> Hi, |> |> Does anyone know of, or can anyone suggest, a simple compression (s/w PC) and |> decompression (Altera FLEX8000 devices) algo that i could use. |> |> I am interested in coding byte streams to increase my through put to |> an FPGA interface (RIPP10 - supplied by Altera) from a PC. |> |> Cheers, |> |> Iain You can use a simple run length coding scheme to get significant bit-stream compression. Most bit-streams have long strings of 1's or 0's (very little relative information). You need to be careful when testing your algorithm, however, because a faulty bitstream compression/decompression scheme can easily burn or destroy your FPGA. I would recommend extensive testing on your compression/decompression *off-line* before attempting it on the FPGA. -Mike -- Michael J. Wirthlin Brigham Young University - Electrical Engineering Department Reconfigurable Logic Laboratory (801) 378-7206Article: 1126
I am a graduate student at Iowa State University and I need some information about a techinical report in Western Michigan University relating to routing of FPGA's. The title is " New Channel Segmentation and Associated Routing Algorithms for High Performance FPGA's" by Naveed Sherwani, Surendra Burman and Chander Kamalanathan. Techinical report 92/18 Please do let me know Respond to venki@iastate.edu (or) venki@cpre1.ee.iastate.edu Thanking you VenkiArticle: 1127
chibane@alpha.fdu.edu (Cherif Chibane) writes: stuff deleted >So can anybody, who has used Lattice, share with me his thrills of victories >and agony of defeats. Having suffered many griefs with XILINX, I >can take anything. I have used ISP3256, ISP1048 and ISP1032. Early on in the design I decided to fix the pinouts just to see what happened when a re-fit was required. After many design iterations I have not once had to change the pinout. Of the two 3256 designs one has high pin utilization, the other high logic. They have been a pleasure to use. Cheers, T.H.Article: 1128
Can anyone provide a telephone number for ordering Lattice databooks? Please reply via e-mail to "milne@petra.cv.com". Thanks in advance. EwanArticle: 1129
One of the things that was good at the fccm conferance was the paper on short floats. I'm wondering if this might not be a good thing to get in the IEEE spec. A short float would be fast in a normal CPU as well as being a good fit for FPGAs. Steve Casselman Virtual ComputerArticle: 1130
I have recently been using the ispLSI2032 part for a project at work, the basic design system costs only 60 U.K pounds, but is limited to the 1016 and 2032 parts, the full systems costs 500 U.K pounds. The design I was working on went very well, the fact that each group of 4 registers can have a seperate clock, even a product term clock was very use full as I had a counter, whoes clock was internally selected by logic. The only draw back I can see is that you have to manually assign your logic to the register groups, I don't know if this is just with the basic design kit, it might be a bit different in the full system. Our design was based on the cheeper 2032 parts, these contain fewer internal registers, and no registers on the inputs, which we did not need any way. Thats all I have done with the device so far, but it worked, and the design system was reasonably simple to use, although I found the logic function machros not to use full. The counters for instance all have a Carry Out, which uses an extra logic term and we did not need. Hope that helps. Oh, the I/O pins also have a selectable pull-up resistor, this makes the device use full if you have setup DIP switches feeding it, one less component per switch. I liked that. -- God Bless Chris Abbott ============================================================================Article: 1131
Anyone got a number for lattice in the US. At 16 pounds, I can afford this for my hobby. Just think , I (and other hobbyists) could be buying millions (well maybe thousands) of orca (or other vendor) devices if they had a cheap entry level system ! I know an old thread, but it is frustrating. thanks Clive B.Article: 1132
Sashi Obilisetty (obiliset@ascinc.com) wrote: > I was wondering if there is a Web site I can look into for > papers in FPGA based research. I suggest http://www.mrc.uidaho.edu/fpga/fpga.html as a good place to start. -- Jim Frenzel, Asst. Prof Electrical Engineering, BEL 213 208-885-7532 University of Idaho jfrenzel@uidaho.edu Moscow, ID 83844-1023 USAArticle: 1133
In article <1995May2.003904.14885@sun490.fdu.edu> chibane@alpha.fdu.edu (Cherif Chibane) writes: >I have been looking to LATTICE EPLD. They seem to be good. From my Lattice doesn't make EPLDs. They make EEPLDs which are Electrically Erasable and reprogrammable In Circuit. This is wonderful for high pin count surface mount devices. (you wouldn't call a Flash memory device an EPROM even though it is erasable) >research, they seem to have extra resources for pin routing. Since my This is indeed a useful feature. I have been using AMD MACH 445s which have a similar concept and indeed, the pin routing works very well. Note that AMD's pin routing resources are greater than Lattice, but that doesn't mean Lattice's resources are insufficient. One of the things that keeps me from using Lattice is that their timing model is so complex for a CPLD. On the other hand, their largest device is larger than any available MACH part. -- Question Authority, but never shoot back.Article: 1134
It has been a while since I have posted and I know more Web Sites have appeared, so... I have put together a collection of links to VLSI related WWW Servers at: <URL:http://www.mrc.uidaho.edu/vlsi/vlsi.html> an I am looking for Web Servers that are directly related to VLSI to add to the list. There is also a FPGA page at: <URL:http://www.mrc.uidaho.edu/fpga/fpga.html> So if you know of any sites that I am missing on these lists, let me know. Thanks, Len Harold -- _______________________________________________________________________ | __ ___ ___ _______ _____ | | /| | /\ \ /| \|\ _ \/\ __\ Len Harold | | | | | \ \ - | \ \ \_\ /_ \ \_/ | | | | \ \ \ \ _|\ \ \ _ \ \ \___ Phone: 208-885-7034 | | | | \ \ \__\/\ \__\ \__\ \__\ \_____\ Fax: 208-885-6840 | | | |* | \/__/ \/__/\/__/\/__/\/_____/ Internet: | | |/\ |/\ lharold@uidaho.edu | | \/ \_/\ University of Idaho | | /| | Microelectronics Research Center | | | | | NASA Space Engineering Research | | | |____________| Center for VLSI System Design | | |/____________/ WWW[URL]: http://www.mrc.uidaho.edu/ | |_______________________________________________________________________|Article: 1135
Hello,
I am looking for a tool that will "automatically"
create a constraint (.CST) file for a Xilinx 4013 FPGA Design.
I am using the Viewlogic ProSeries / Xilinx XACT tools.
I tried the utility called IOLOC which I downloaded
from the Xilinx BBS. However, it worked partially, and
then crashed my computer. IOLOC is supposed to extract
the IO information from the given .LCA file.
I am looking for any utility that would perform
a similar function of IOLOC such that the IO Pins on the FPGA
(and perhaps the CLB use) can be fixed in place in preparation
of board level schematic entry.
Thank you,
Ed Leventhal
Article: 1136In article <3o8ket$1cd@spock.asic.sc.ti.com> clyvb@asic.sc.ti.com writes: >Anyone got a number for lattice in the US. >At 16 pounds, I can afford this for my hobby. Why don't you reserve judgement until you use the Lattice design software... -- Question Authority, but never shoot back.Article: 1137
pngai@mv.us.adobe.com (Phil Ngai) writes :- >One of the things that keeps me from using Lattice is that their >timing model is so complex for a CPLD. On the other hand, their >largest device is larger than any available MACH part. Although the timing model looks complex a rough rule of thumb for 3000 series parts is :- operating frequency (MHz) = device max frequency / no of CLB levels between registers This worked well for me and proved about right when the design was simulated. Cheers, T.H.Article: 1138
>> I am looking for a tool that will "automatically"
>> create a constraint (.CST) file for a Xilinx 4013 FPGA Design.
>> I am using the Viewlogic ProSeries / Xilinx XACT tools.
>>
Do you think it is sensible to create a constraints file based on a
single routing (i.e. LCA file)? In the past I have manually
constructed constraints files based on groups of known good routings,
in order to find placement trends. For example constraining known
critical signals first and performing further routes to find IOs that
always get placed in similar locations.
This gives me some confidence that if I need to do some rework the
placement I have is based on many passes and not just a single 'fluke'
routing. Having said this on my latest design I didn't have time to do
the routing before getting the PCBs made so I had to guess a suitable
pinout.
It is well worth using XACT to look at the internal structure of your
chosen device when choosing the pinout. For example if you use an
internal bus with tri-state drivers then note that the tri-state
buffers drive only horizontal long lines, so place your data pins
along the left or right edges. Clocks are another obvious area for
consideration. Clearly it is better to do some placement and routing
before fixing the pinout.
What I would like to see is a program that scans a number of *.rpt
files looking for the pin placement section in order to find
trends. The output could be a table with pin number and number of
occurances of each signal on that pin. It would then help if the
format was suitable for generating the constraints file without too
much editing. I wrote a simple script using grep that collated the
information, but then sorted it out manually.
I'm sure there's an awk or perl hack out there who could do this in a
matter of minutes. A section of the report file looks like this:
Package Pin Location Pin Name
-------------------- -----------------
P2 : MCLK
P4 : A<3>
P5 : A<2>
P7 : A<1>
P8 : A<0>
P10 : MAS<1>
P11 : MAS<0>
P12 : NRW
P13 : NMREQ
The required constraints file format is:
place block A<28> : P105;
place block A<29> : P104;
place block A<30> : P102;
place block A<31> : P100;
place block MAS<1> : P10;
place block MAS<0> : P11;
place block nRW : P12;
place block nMREQ : P13;
where 'block' is 'instance' for XC4000 series.
So a suitable output format (for 8 input files) might be:
place block A<28> : P105(5) P104(2) P23(1);
place block A<29> : P104(4) P105(3) P103(3);
place block A<30> : P102(7) P45(1);
place block A<31> : P100(8);
place block MAS<1> : P10(2) P2(2) P3(2) P45(2);
place block MAS<0> : P11(6) P12(2);
place block nRW : P12(8);
place block nMREQ : P13(4) P32(4);
etc..
I wonder what other Xilinx users think?
Mark Snook
(mark.snook@armltd.co.uk)
Article: 1139Chris G Abbott <Chris@ruatha.demon.co.uk> writes :- >The only draw back I can see is that >you have to manually assign your logic to the register groups, I don't know >if this is just with the basic design kit, it might be a bit different in the >full system. It is all automatic with the full system. T.H.Article: 1140
Hi, Can anyone enlighten me about trends in prices in (largeish) FPGAs? I naively assumed 'volumes are increasing - prices will go down' and put off buying some for a while - now I find the price has gone up! Are they behaving like DRAMs with artificial shortages inflating prices, are the trends very specific to each manufacturer, or what? Is it possible to make any predictions about (low-quantity) pricing? Thanks Graham -- -------------------------------------------------------------------- Graham Seaman, School of Computer Science, University of Westminster, 115 New Cavendish St. London W1M 8JS email: seamang@wmin.ac.uk www: http://www.wmin.ac.uk/~seamangArticle: 1141
********************************************************* DIRECTIONS TO ACCESS THE verilog2vhdl(tm) ONLINE DEMO ********************************************************* About verilog2vhdl ------------------ verilog2vhdl translates hierarchical Verilog HDL to VHDL by using an HDL object kernel. It makes a full translation of structural Verilog, and a partial translation of behavioral Verilog. It supports a subset of Verilog and uses a combination of IEEE and tool-specific VHDL packages to perform the translation. VHDL that is created by verilog2vhdl is functionally equivalent to input Verilog, and because of one-to-one mapping of Verilog to VHDL, output VHDL is easy to understand. Output VHDL is IEEE 1076-1993 compliant, and VHDL produced by the system is compatible with a 1076 compliant VHDL simulator. How to access the demo ---------------------- The on-line demo can be accessed by following the directions below: 1. Connect to URL - http://www.ascinc.com 2. Select the 'verilog2vhdl' option from the list of products Alternatively use URL- http://www.ascinc.com/v2vhdl/v2vhdl.html when you invoke your favorite Web browser 3. Select option 'on-line verilog2vhdl demo'. You will need to fill out a registration form. Click the 'Submit' button, to proceed with the registration. You will receive an email confirmation of the Registration from ASC. (The response is automatic, so this should take about as long as regular emails). After confirmation, you are eligible to send 3 designs for translation. Please read the directions in the email response carefully, before submitting your designs for translation. Happy translating! -- * Sashi Obilisetty * * Alternative System Concepts, Inc. * * PO Box 128 Windham NH 03087 * * tel (603) 437-2234 fax (603) 437-ASC2 URL http://www.ascinc.com *Article: 1142
I hope someone can help. I would like to build a VXI register based device. The problem I am having is that the interface spec is very overwhelming. Does any one know of a design that is publically available. I can do Lattice PLD development, so something that can be implemented in PLD would be very useful. Any information would be useful to start off with. Thanks GREG tate@nosc.milArticle: 1143
In article <3o2fnd$fgj@rzsun02.rrz.uni-hamburg.de>, Andre Klindworth <klindwor@tech12.informatik.uni-hamburg.de> wrote: > >Hello, everybody > >I would like to know where I may obtain a databook on AT&Ts ORCA FPGAs? [..] >----------------------------------------------------------------------- >Andre' Klindworth Universitaet Hamburg, FB Informatik >klindwor@informatik.uni-hamburg.de Vogt-Koelln-Str.30, D-22527 Hamburg > Phone: +49 40 54715-501, Fax: -397 Das Datenbuch gibt es bei SEI (Sonepar Electronique International), in Deutschland sind das die Firmen Elbatex, Jermyn, OmniRay und Eljapex. Die Adresse der Elbatex ist: Elbatex GmbH Herrenpfad Sued 4 41334 Nettetal 02157/819-0 02157/819-100 (FAX) SEI ist auch uebers netz erreichbar: http://www.sei-europe.com:8008/ (ist allerdings noch im Aufbau) Das Orca-Datenbuch muesste inzwischen verfuegbar sein, ich habe mein Exemplar Mitte Januar bestellt, die Lieferung ist fuer KW20 angekuendigt. Andreas Graevinghoff angra@cs.uni-sb.deArticle: 1144
> I am looking for a tool that will "automatically" > create a constraint (.CST) file for a Xilinx 4013 FPGA Design. > I am using the Viewlogic ProSeries / Xilinx XACT tools. I have a few tools that might be useful. You can get them via anonymous ftp at esesrv0.fnal.gov /pub/xilinx xfunc.exe Extends workview to use equation text on viewdraw schematics. Text is compiled into gates automatically. xdis.exe Disassmble X4000 LCA files into CLB equation text. ncd2eq.exe Disassemble a Neocad NCD file to equations. fanout.exe Print list of signal dependancies global.exe Fix XNF files to allow global signals blk.exe Print map of X4000 CLB outputs long.exe Print map of X4000 Long line usage pinout.exe Print X3000 or X4000 Pinouts and list pins. (includes configuration pins) ncd2prf.exe Create a skeleton placement file for neocad. unaka.exe Undo the function of Xilinx AKA file. These have been tested and documented pretty well. There are 2 test schematics for testing the xfunc program with NeoCad and Xilinx software.Article: 1145
In-circuit programmability, too. Anyone got a number for lattice in the US. (503) 681-0118 Also, both Marshall (http://www.marshall.com/) and Insight Electronics (http://www.memec.com) have Lattice info on their web pages. I might point out that you can buy the Lattice parts and design kits from Digikey (800-344-4539). -- Roger Williams Coelacanth Engineering | Numeric stability is probably not all Middleborough, Mass | that important when you're guessing...Article: 1146
Is it possible via FPGA's to copy a particular logic chip; provided you already have this chip. Mapping the chip to be copied is the first difficulty. To be more specific this is an old commodore business machine's chip that is no longer available at feasible prices and is purely logical. njachimi@uiuc.eduArticle: 1147
I have an 800 number for their hot line (taken from integrated system design magazine) 1-800-327-8245 , fax 503-681-3037 ask for info packet 624 starter kit including sw,samples, and isp cable is $99 apparently.Article: 1148
In article <D81qKL.Fs0@westminster.ac.uk>, seamang@westminster.ac.uk (Graham Seaman) says: > >Hi, > >Can anyone enlighten me about trends in prices in (largeish) FPGAs? >I naively assumed 'volumes are increasing - prices will go down' >and put off buying some for a while - now I find the price has >gone up! Are they behaving like DRAMs with artificial shortages >inflating prices, are the trends very specific to each manufacturer, >or what? Is it possible to make any predictions about (low-quantity) >pricing? > >Thanks >Graham > >-- >-------------------------------------------------------------------- >Graham Seaman, School of Computer Science, >University of Westminster, 115 New Cavendish St. London W1M 8JS >email: seamang@wmin.ac.uk www: http://www.wmin.ac.uk/~seamang Hi Graham, It seems that we frequent the same news groups. To your question, the price of fpga's seems to depend on the packaging technology,all others factors being equal, i.e density and functionality. Recently I have been researching in the different devices available from different manufacturers, the prices seemed generally inline, but the trend is definitely downwards. I have contacted Xilinx, Actel more recently Altera, admittedly I was after RAD (radiation hard versions), but for prototyping we are using just standard commercial devices. Typically, an ACT 1020 100 pin plastic quad flat pack cost £12.00, whilst a ceramic version of the same device cost £80.00. By far the greatest costs incurred is the device programmer and the programming software. The compromise here seems to be between propriorty device programmers and software against industry standard equaivalents which allow much greater flexibility. I hope the above is of some help, what are you up to ? Herbert Larbie (ex Msc student - Digital systems and instrumentation) Forgive the typosArticle: 1149
I have to create a 16bit adder in xilinx. The adder has to be connected with a T805. The T805 writes two numbers to the FPGA. So I use two registers (FDCE16) to store the numbers. The sum is stored in a third register. If the FPGA receives the second number, then the sum must be stored in the third register. Now, the problem is that all the registers use the same clock (the t805 uses 'notmems0' as a clock) So at the rising edge, the second number is sent to the ADD16 but in the mean time the sum must be stored in the third register. But the ADD16 needs some time to calculate. Anyone has ome suggestions to solve this ? Thanx in advance.
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Compare FPGA features and resources
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