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Xilinx has a Web-site at: http://www.xilinx.com/ Somewhere inside their web-pages there is a reference to a support email-address (I haven't tried it though): hotline@xilinx.com --Torbjørn-- -- ---- Torbjorn Bakke (tb@vingmed.no) Tel: +47 33 04 21 32Article: 1076
In article <D7KLvG.5t4@nntpa.cb.att.com>, pn@anuxt.mv.att.com says... > >In article <3ngr7o$5fb@news.uncc.edu>, >Terry E. Koontz <tkoontz@uncc.edu> wrote: >> >>Viewlogic recently add ViewTest to their Powerview product line. >> >>ViewTest is based on Sunrise 2.0 software (their words) >> >>Does anyone have an address and telephone number for Sunrise. >> >>Terry Koontz >>UNCC >> >>tkoontz@uncc.edu > > >If I am not mistaken, ViewLogic has not continued with the addition >of ViewTest. I was initially making it part of their package, >however, there were many difficulties with the intergration. So >they were moving back to the stand alone Sunrise package. >(ViewLogic purchased Sunrise as it did many other co.s) > >Tony > Sunrise recently moved in with Viewlogic at their Fremont Ca. plant. The number there is (510) 440-1000. You can also try Jean Pierre Braun at: jp@srtest.com The current TESTGEN rev. is 2.1 Good luck GideonArticle: 1077
In article pii@distort.demon.co.uk, herb@case373.demon (Herbert Larbie) writes: >23/4/95 > >I thunking about checking out the Lattice low-cost starter kit isp-sk, could >anyone who has been using it relay their experience to me please. > >Thanks in advance. > >Herbert Larbie > I bought that kit some weeks ago. Although I didn't run a design yet, I implemented and compiled two designs to see how it works. It supports isp devices 1016 and 2032 which are not very large (sigh..). 1016 is similar to AMDs MACH210 but has better routing capabilities. Don't try isp*** if you have different tristate signals in your design, it has no individual output enables, only blockwise. The software does not optimize your partitioning.... it will take some time to get used to it. I reached > 90% useage after careful manual optimization, quite nice. The package comes with complete documentation including download code, which covers the ispGAL22v10 also. If you plan a real design, better consider the 1016 to have only 64 registers not the 96 mentioned in the manual. The 32 IO registers are of limited use only. At the time it's the only package for real low-cost designs, for you don't need a programmer for these chips. aku --- -------------------------------------------------------- Andreas Kugel Chair for Computer Science V Phone:(49)621-292-5755 University of Mannheim Fax:(49)621-292-5756 A5 D-68131 Mannheim Germany e-mail:kugel@mp-sun1.informatik.uni-mannheim.de --------------------------------------------------------Article: 1078
In article <3mt85v$kru@news.csie.nctu.edu.tw>, Chuang Hsien-Ho <eea80593@maddux.EE.NCTU.edu.tw> wrote: >Hi: > >I want translate SIS's output(blif/slif/eqn...) to XNF format. >Does anyone has the translator? Or any other sugesstion to me? >Thanks a lot! > >-- >=============================== >Hsien-Ho Chuang >eea80593@yankees.ee.nctu.edu.tw >=============================== There is a program that was developed at UCSC a while back. I have to ask around if it's shareware or not. I'll let you know. -- ============================================================================== To accomplish great things, we must not only act but also dream, not only plan but also believe. Anatole FranceArticle: 1079
I just returned from the FCCM conference (FPGAs for Custom Computing Machines) and was interested in the many different opinions on the future and direction of custom computing machines (ccms or fccms). I noticed a wide spectrum of opinion on the question "How much performance is necessary to justify a FPGA based custom computing machine?". I would like to paraphrase a number of opinions I heard from the various attendees. I would appreciate any feedback anyone has on the same question. Opinion #1: Any speed-up over workstations/PC's using FPGA based computing machines is sufficient to justify the machine. Don't apologize for speedups of only 20x. Hardware algorithms that speed up an inner loop by factors of 2-20 are satisfactory. Opinion #2: Only substantial performance improvements can justify the use of an FPGA based computing machine. FPGAs operate at a clock rate 10x slower than the processors used today (so they need at least 10x in parallelism to make up the difference). In addition, FPGA systems can cost 10x more than the host it was intended to replace (need another 10x to justify the cost). If you consider the extra development time, the margins are even greater. These systems must provide 100-1000x speed-up to justify their use. Opinion #3: Performance/cost is the metric, not just brute performance. If I can replace a $10 million of performance X with an FPGA based machine costing $10 thousand of performance 1/5 X, my performance/cost has improved by a factor of 200. If I can achieve substantial performance/cost benefits (100-1000x), I can justify the machine. Any other opinions? -- Michael J. Wirthlin Brigham Young University - Electrical Engineering Department Reconfigurable Logic Laboratory (801) 378-7206Article: 1080
Hi, I must design a digital conference chip. But I have no idea about this chip. This chip use to mix several PCM signals together. I know that, the PCM code is nonlinear. So the first step to do a conference is to convert this nonlinear PCM code into linear digital signal system and sum the whole time slot that need to join a conference together. Then convert this signal back to PCM code and put it back to the specific time slot. I will use FPGA as my target to implement this design. Could anyone suggest me in the following questions ? 1. I know that PCM is nonlinear digital system so we must convert it back to linear digital signal before we can do anything on it. From 8 bits of PCM code must be convert to 14 bits of linear digital signal. The easy solution is to use ROM to convert this signal, but I would like to know that is there any other way to do this job ? And dose it appropriate for targetting at FPGA ? 2. When we have many time slot want to join a conference, we must attenuate all signal before summing it up. so the question is how can I attenuate this linear digital signal ? I think this should not as easy as just divide it with number of conferece time slot. Am I correct ? Any comment or pointer is very appreciate. Thank you for your concern. Best Regards, Wichai TangArticle: 1081
In article <3ngggb$4um@mother.usf.edu>, harihara@sunburn.eng.usf.edu (Shankar Hariharan (EE)) writes: |> hi, |> I am doing a research on the studying the advantages of implementing application specfic archtectures on FPGA's. I would like to hear ur view point on this issue. Any pointers in this direction would be greatly appreciated. |> |> I promise to post the summary of the reply after compilation. |> |> H.Shankar. |> -- | I can give some advantages that I feel are important. This also could be seen as an answer to Mike's question about how much performance is enough. The big advantage I see for FPGAs is the ability to amortize the silicon costs over several problems/architectures. Thus, in my area of interest (DSP), one might decide to build a coprocessor type of board based on reconfigurable logic that can be used for several different types of high-speed signal processing. For example, the board may at one time be used to filter some images at one point and a few minutes later be used to perform a high speed FFT. (I pick these two examples since I am most familiar with them. I have implemented both on FPGAs and obtained good performance) Thus, the same hardware can be used to achieve good performance on two separate operations. I can justify the hardware and even the development cost since the only way I could get similar performance would be to use ASICs. Thus, for me the justification is simply if I can get the performance I desire using FPGAs and I cannot get it using programmable processors (such as DSP processors), then the only choice I have is the FPGA or the ASIC. I choose the FPGA since I for most operations cannot justify the ASIC. Also, the ASIC implementation would require too many chips to perform all of the operations I desire to implement and hence it is too costly and complex. The other advantage I did not mention that is often cited as a great advantage to a reconfigurable approach is that of dynamic reconfiguration or the ability to reconfigure a system while it is operating. This is usefull since one can implement at one time exactly what is needed and nothing more. This is usefull in many cases. As an example, for the FFT a basic butterfly element can be reused over multiple columns of the FFT if one desires. The only thing that must change from one column to the next is the addressing. ASICs have been built that have this capability. They allow flexible addressing to handle the data appropriately in each column of the FFT for which that butterfly element is being used. I submit that an advantage an FPGA implementation could have here is the ability to simply reconfigure the necessary addressing logic. Thus, the logic would be smaller and due to its special-purpose nature it could be faster. In this case it may not really be a critical path anyways so the point may be a minor one but it does bring up what I think is a major advantage of the FPGA. That is, even though they are slower than ASICs in straight comparisons, implementations using them can still be faster since one can make them more special purpose through the use of reconfiguration. Now for the problems. Right now I think FPGA systems are very usefull in many areas as a reconfigurable computing resource but they are also many problems. In particular, development time is way to costly. In my latest implementation of an FPGA based system the VHDL code for the system took me about 4 hours to write. (It was even correct! :)). However, due to the difficulty in seeing what was happening with the FPGA board I was using it took me several days to write the software interface and get it working correctly. Thus, most of the time was spent on debug of something other than the actual hardware. This is of course typical of many systems of this type but it could be different. I think that before reconfigurable logic can become truly mainstream much, much work must be done on the tool side. Ideally a reconfigurable resource could be debugged as if it was software (somewhat like what is available on Splash-2). This ability would greatly cut development costs. Also, I believe that the devices could still use more routing. I read with great interest about HP's new Teramac computer that is a routing rich device. It really is frustrating when one is using a FPGA/PLD device and finds that what should be easily implemented in the logic (30% utilization) cannot be due to routing constraints imposed by the pinouts. This in my opinion should be something a user should have to consider until one reaches at least 90% utilization. As a final note, I believe that reconfigurable logic is becoming ever more usefull. There are some exciting devices coming out from several manufacturers that I see as greatly improving the utility of the reconfigurable device (especially in my interest area of DSP!). - Just my thoughts Russell Petersen petersr@fpga.ee.byu.edu Brigham Young University Reconfigurable Logic LaboratoryArticle: 1082
> Does anyone have an address and telephone number for Sunrise. >From their web page, 510-440-1000 http://www.viewlogic.com/sunrise/srover.html or just start from http://www.viewlogic.com/ and go down. --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 1083
Does anyone have any technical details about the forthcoming FLEX10000 device. I have heard that the device contains a logic array (similar to the FLEX 8000 device) and an embedded hardwired array which contains useful mega-functions; for example: SRAM, ROM, FIFO's and dual-port SRAM Multipliers ALU's Sequencers 8086, Z80, 6502 FIR filters, convolvers, wavegenerators Surely something like this will blow other FPGA's out of the scene. Iain ;) idr@ee.ed.ac.uk http://www.ee.ed.ac.uk/~idrArticle: 1084
Hi, Does anyone know of, or can anyone suggest, a simple compression (s/w PC) and decompression (Altera FLEX8000 devices) algo that i could use. I am interested in coding byte streams to increase my through put to an FPGA interface (RIPP10 - supplied by Altera) from a PC. Cheers, Iain idr@ee.ed.ac.uk http://www.ee.ed.ac.uk/~idrArticle: 1085
> "How much performance is necessary to justify a FPGA > based custom computing machine?" I think 10-20X performance speed-up, for a few thousand, (by focusing on the inner loop of algorithms) is marketable. The key is support for multiple applications. Anyone remember the Futurenet simulation card? Cranked up simulation for about $10K. The problem with this, and most other accelerators is that they serve(d) a single application. On the other hand, if it could speed up logic simulation, transistor level simulation, placement and routing, etc. this would be more interesting (and justifiable) for engineering applications. If you expect non-engineers to purchase a hardware accelerator, likewise it had better have multiple applications. Otherwise people will spend their $$ on a faster computer that speeds up everything they do. So really, I think that alliances with software vendors is the key to make end users bite. Software vendors in turn will want standards so that if one hardware vendor flops they protect their investment. Making a card with a few FPGAs on it seems trivial compared to this effort. Perhaps Microsoft will "bless" us with a standard for PC accelerators as a way to compete with Unix? They are trying to get EDA vendors to switch. In the engineering world, if you can't get Xilinx or Altera to speed up FPGA place & route with such an engine, I doubt you will convince anyone else to go first. Engineering applications have two other complications, 1) the need to support both PC & Unix and 2) software vendors may prefer to develop software that uses multiple processors on a network instead. Multi-media is also an interesting possibility. Multiple applications that could use more horsepower, and just PCs to worry about. Of course the price would need to be low. Good luck! --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 1086
Hi there! I was wondering if I can get the data regarding the market position (Annual Revenue) of major FPGA/CPLD suppliers like : Xilinx, Altera, Actel, Lattice etc. Thought this will be the most appropriate group. Thanks... Best Regards, --RuchirArticle: 1087
This is a multi-part message in MIME format. ---------------------------------195971426010166 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=iso-8859-1 idr@ee.ed.ac.uk (Iain Rankin) wrote: >Does anyone have any technical details about the forthcoming >FLEX10000 device. > Try looking at Altera's web site. They have some info. about the 10k series part there. http://www.altera.com/ ---------------------------------195971426010166 Content-Transfer-Encoding: 7bit Content-Type: ---------------------------------195971426010166--Article: 1088
idr@ee.ed.ac.uk (Iain Rankin) wrote:
>Does anyone have any technical details about the forthcoming
>FLEX10000 device.
>
Look at Altera's web site. They have info. on the 10k series part
there.
http://www.altera.com/
___________________________ -----
Russell Petersen || BYU ||
Brigham Young University || ||
Reconfigurable Hardware Lab -----
petersr@fpga.ee.byu.edu ---------
voice: (801) 378-7206 | - - |
---------
WEB: http://splish.ee.byu.edu/~petersr/russ.html
------------------------------------------------
Article: 1089
>>>>> On Wed, 26 Apr 1995 08:03:50 GMT, idr@ee.ed.ac.uk (Iain Rankin) said:
I> Does anyone have any technical details about the forthcoming
I> FLEX10000 device.
I> I have heard that the device contains a logic array (similar to the
I> FLEX 8000 device) and an embedded hardwired array which contains
I> useful mega-functions; for example:
I> SRAM, ROM, FIFO's and dual-port SRAM
The "hard-wired" array is a RAM that can be configured to be any of a:
258x8, 512x4, 1024x2, 2048x1. So, it is a very flexible memory but
it is not an 8086 or Z80, etc. The idea of the megafunction is
that you can use the RAM as lookup tables, etc.
I> Multipliers
I> ALU's
I> Sequencers
I> 8086, Z80, 6502
I> FIR filters, convolvers, wavegenerators
The rest of this stuff is library modules that are being developed
that will likely consume most of the FPGA. As I understand it,
the 8086 was one the designs that was used to test the design.
The 10k part is a very interesting part. The availability of
reasonably sized memories *on-chip* will make for much more
interesting designs.
--
Brad L. Hutchings (801) 378-2667 Assistant Professor
Brigham Young University - Electrical Eng. Dept. - 459 CB - Provo, UT 84602
Reconfigurable Logic Laboratory
Article: 1090In article <3niupl$cs4@trumpet.uni-mannheim.de> kugel@mp-sun6.informatik.uni-mannheim.de writes: >Don't try isp*** if you have different tristate signals in your design, it has no >individual output enables, only blockwise. Isn't it amazing how common this brain damage is? Altera is very limited in this regard also in their 7000 series parts. You'd think a output enable product term wouldn't be *that* expensive. -- Question Authority, but never shoot back.Article: 1091
In reference to fpgas and pci bus. Xilinx about a month ago came out with a series of app notes about fpgas. There were a few that discussed pci interfaces in detail and their implementation in their fpga's. Call your xilinx rep for a set. Tony pn@anuxt.att.comArticle: 1092
XILINX ANNOUNCES LAWSUIT AGAINST ALTERA WILL PROCEED FIRST Source: PR News Wire via DowVision Date: Apr 25, 1995 Time: 7:46 am SAN JOSE, Calif., April 25 /PRNewswire/ -- Xilinx, Inc., (Nasdaq: XLNX) today provided an update of its pending patent litigation with Altera Corp. (Nasdaq: ALTR). At a recent hearing the judge ruled that the Xilinx suit against Altera would be tried first and that proceedings in the Altera suit against Xilinx would be stayed. Xilinx sued Altera in June 1993 for infringing certain Xilinx patents. In response to the Xilinx suit, Altera filed its own suit against Xilinx for patent infringement. In July 1993 Xilinx asked the court to stop sales of the Altera FLEX family of devices pending a trial. That matter was referred to a special master appointed by the court. Based on the findings of the special master the court said "Xilinx has demonstrated that it is likely to succeed at trial on the issues of validity and infringement of Carter [patent] claim one [against Altera's FLEX product]." However, the court declined to issue the preliminary injunction to stop sales pending a trial on the basis that continued sales of the FLEX products were not causing Xilinx irreparable harm in the marketplace. Both suits were then consolidated before federal judge Robert P. Aguilar in San Jose, Calif. At a recent hearing Judge Aguilar ruled that the Xilinx suit against Altera would be tried first and that proceedings in the Altera suit against Xilinx would be stayed. The judge also appointed a new special master to make factual findings in the case. "We are pleased that the court has agreed to move ahead with the Xilinx suit first and we are quite confident that the court, with the assistance of the special master, will conclude that the Altera FLEX and MAX product family infringe our patents," said Chuck Fox, vice-president of Product Marketing of Xilinx. Xilinx also commented on last week's additional suit filed by Altera against the Xilinx XC5000 family which was filed in Delaware instead of California. Xilinx said the suit has no merit and is merely a reaction to the court's decision to stay the current Altera litigation against Xilinx. "This is a blatant case of forum shopping where Altera is searching for a way to avoid the California court's decision," said Mr. Fox. "The XC5000 family is the first programmable logic family specifically developed as a cost-effective, high volume production alternative to mask programmed gate arrays. The XC5000 has been very well received by customers. It will significantly strengthen our #1 position in the programmable logic market." DowVision on the Internet. Brought to you by Dow Jones in collaboration with WAIS Incorporated.Article: 1093
idr@ee.ed.ac.uk (Iain Rankin) wrote: >Does anyone have any technical details about the forthcoming >FLEX10000 device. > I have a copy of the slides from a press briefing. What in particular do you wish to know ? Cheers, T.H.Article: 1094
Niranjan Cooray (niranjan@vlsi45) wrote: > In article <bjrosen-2204951601120001@bjrosen.tiac.net>, bjrosen@aol.com (Joshua Rosen) writes: > |>In which package is Berkeley's SIS tool located. I can't find it in the > |>Octtools package, is it there or somewhere else? > |> > |>Thanks > |> > Berkeley SIS tool is available for anonymous ftp from: > ftp://ic.eecs.berkeley.edu/pub/Sis > It does'nt come with the octtools pkg, but having the octtool pkg when you > compile SIS, will give you added features in SIS. > Hope this helps. > -- Niranjan > ------------------------------------------------------------------------------ > Niranjan Cooray E-mail (Internet): niranjan@nuvlsi.coe.neu.edu > ECE Department niranjan@splinter.coe.neu.edu > Northeastern University > Boston, MA 02115 > HREF="http://www.ece.neu.edu/personal/niranjan/niranjan.html" > ------------------------------------------------------------------------------Article: 1095
In Article <D7pHAy.4u1@bbc.co.uk> matthew@rd.bbc.co.uk (Matthew Marks) writes: >Wichai Tang (fengwct@ku.ac.th) wrote: >: Hi, >: 1. I know that PCM is nonlinear digital system so we must convert >: it back to linear digital signal before we can do anything on it. From 8 >: bits of PCM code must be convert to 14 bits of linear digital signal. The >: easy solution is to use ROM to convert this signal, but I would like to >: know that is there any other way to do this job ? And dose it appropriate >: for targetting at FPGA ? > >If you use a Xilinx chip (and no doubt many other types as well) you can >store the look-up tables in the same ROM as the configuration, so no extra >chips needed. > >: 2. When we have many time slot want to join a conference, we must >: attenuate all signal before summing it up. so the question is how can I >: attenuate this linear digital signal ? I think this should not as easy as >: just divide it with number of conferece time slot. Am I correct ? > >As you are not worried about quantising distortion ;-) you won't have to >worry about adding digital dither, so, yes, you just divide the signals >by an appropriate amount and add them. Dividing by a power of 2 is very >easy of course - just shift the bits. > If you can afford the larger accumulator, add the signals first then scale the result (a simple way of doing this is to just take the 14 msbs of the result). Your quantizing noise will be lower by adding first. A better soultion than simply taking the 14 msbs is to set up a pseudo AGC to track the average magnitude of the result over a fixed time period and use that result to select which 14 bits to take from the accumulator. The selector can include logic to realize saturating arithmetic so that the signal clips if it exceeds the range of the 14 selected bits rather than getting the 2's comp wrap around. I've used the AGC and saturating arithmetic method for some radar signal processing work. The hardware is fairly simple and can be made very fast. The AGC value could also be determined as a function of the number of participants in the conference. -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 email randraka@ids.net The Andraka Consulting Group is a digital hardware design firm specializing in obtaining the maximum performance from FPGAs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate, troubleshoot, and improve existing designs. Please call or write for a free brochure.Article: 1096
Wichai Tang (fengwct@ku.ac.th) wrote: : Hi, : 1. I know that PCM is nonlinear digital system so we must convert : it back to linear digital signal before we can do anything on it. From 8 : bits of PCM code must be convert to 14 bits of linear digital signal. The : easy solution is to use ROM to convert this signal, but I would like to : know that is there any other way to do this job ? And dose it appropriate : for targetting at FPGA ? If you use a Xilinx chip (and no doubt many other types as well) you can store the look-up tables in the same ROM as the configuration, so no extra chips needed. : 2. When we have many time slot want to join a conference, we must : attenuate all signal before summing it up. so the question is how can I : attenuate this linear digital signal ? I think this should not as easy as : just divide it with number of conferece time slot. Am I correct ? As you are not worried about quantising distortion ;-) you won't have to worry about adding digital dither, so, yes, you just divide the signals by an appropriate amount and add them. Dividing by a power of 2 is very easy of course - just shift the bits. Matthew matthew@rd.bbc.co.uk My opinions, not Auntie'sArticle: 1097
In article <HUTCH.95Apr26122452@timp.byu.edu>
hutch@timp.byu.edu "Brad Hutchings" writes:
> The rest of this stuff is library modules that are being developed
> that will likely consume most of the FPGA. As I understand it,
> the 8086 was one the designs that was used to test the design.
>
> The 10k part is a very interesting part. The availability of
> reasonably sized memories *on-chip* will make for much more
> interesting designs.
I was at a Lattice seminar recently and we were told that they will
be incorporating on-chip RAM soon in their ispLSI devices.
Leon
--
Leon Heller, G1HSM | "Do not adjust your mind, there is
E-mail leon@lfheller.demon.co.uk | a fault in reality": on a wall
Phone: +44 (0)1734 266679 | many years ago in Oxford.
Article: 1098Terry E. Koontz (tkoontz@uncc.edu) wrote: : Viewlogic recently add ViewTest to their Powerview product line. : ViewTest is based on Sunrise 2.0 software (their words) : Does anyone have an address and telephone number for Sunrise. : Terry Koontz : UNCC : tkoontz@uncc.edu Sunrise Corp Headquarters 2730 San Tomas Exp. Suite 200 Santa Clara, CA. 95051 408-980-7600 408-980-7630 fax Info_request@srtest.comArticle: 1099
Hi Netters,
My subject says it all. I have been using Viewsynthesis to analyze
my VHDL programs and I can use XBLOX libraries in Viewsynthesis
by making special procedure calls. Is there a similar way to do
this in Synopsys tools? If there is, could you explain how I can do it?
An example of my VHDL code written for Viewsynthesis:
-------------------------------------------------------------------------------
-- Data Register & Counter
-------------------------------------------------------------------------------
data_clk_en <= load_data OR inc_data;
xb_counter(D_IN => d_in, ASYNC_CTRL => reset, CLOCK => clk,
LOAD => load_data, CLK_EN => data_clk_en,
Q_OUT => dout, ATTR => "STYLE=BINARY");
Thanks a lot.
Koray Oner
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