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I know this sounds kind of brave, but I heard that some FPGA vendors will give away Viewlogic design software that was customized for their FPGA's. I know some of the vendors are actel, altera, xilinx and a few others. This is their way of enticing designers to produce designs that will use their products. Anyone know anything about this? Thanks Ronald GoodsteinArticle: 876
I think the point is that you can use the $5K 8050M for protoype. Once the design is ready for production you can replace it instantly with four 81188 chips. The aptix chip gets replaced by fixed traces on the circuit board. The resulting part cost is then pretty cheap. It would also serve well to just replace the part with an ASIC if that were the goal.Article: 877
They may give away "vendor specific" design kits, but who would want one? Vendor specific also means "locked into a vendor". I would prefer to use a generic design entry library like LPM.Article: 878
rongood@world.std.com (Ronald E Goodstein) writes: >I know this sounds kind of brave, but I heard that some FPGA vendors >will give away Viewlogic design software that was customized for their >FPGA's. I know some of the vendors are actel, altera, xilinx and a few >others. This is their way of enticing designers to produce designs that >will use their products. Anyone know anything about this? >Thanks >Ronald Goodstein I have worked professionally (in Australia) for some years with Xilinx parts, and I have *never* known any free software. In fact, the high cost of the development tools is one of the great downs to an otherwise excellent product. I sometimes wonder if Xilinx make their buck from selling silicon or selling software!!! If you know of a source of free Xilinx tools (or toolset components, eg ViewLogic), *please* publish same. Xilinx should reward you for aiding their chip sales... -- David R. Brooks <daveb@perth.DIALix.oz.au> Tel/fax. +61 9 434 4280Article: 879
In article <3kfjkb$fim@newsbf02.news.aol.com>, Gnuge writes: > They may give away "vendor specific" design kits, but who would want one? I would. Vender independent software with enough filters to make use of the independence, costs thousands of dollars. I don't have that. And I'm not being cheap. I have already spent about $2000 on tools. I expect to spend twice that in the comming year. This is fairly insane by hobbyist standards and I still I can't fit in a VHDL compiler without buying a vender specific one. > Vendor specific also means "locked into a vendor". I would prefer to use > a generic design entry library like LPM. So would I, so long as I didn't have to pay for it. ---- Eric Edwards: Bang= cello.qnet.com!wolf359!eric Domain= eric@exile.org Remember the home hobbyist computer: Born 1975, died April 29, 1994Article: 880
In article <D5n9J2.2DD@world.std.com> rongood@world.std.com (Ronald E Goodstein) writes: >I know this sounds kind of brave, but I heard that some FPGA vendors >will give away Viewlogic design software that was customized for their >FPGA's. I know some of the vendors are actel, altera, xilinx and a few >others. This is their way of enticing designers to produce designs that >will use their products. Anyone know anything about this? > >Thanks > >Ronald Goodstein > Yes, but ONLY for educational purposes. They make it as a formal donation for tax purposes. We have Altera and Atmel here at UMASS. Hope this helps, Mircea -- Mircea R. Stan | "Without immortality the whole world would UMass, ECE Dept. | be nonsense, all of creation an absurdity." Amherst, MA 01003 | Karl F. GaussArticle: 881
In article <3kijj0$hh3@risky.ecs.umass.edu>, mstan@hades.ecs.umass.edu (Mircea R Stan) wrote: > In article <D5n9J2.2DD@world.std.com> rongood@world.std.com (Ronald E Goodstein) writes: > >I know this sounds kind of brave, but I heard that some FPGA vendors > >will give away Viewlogic design software that was customized for their > >FPGA's. I know some of the vendors are actel, altera, xilinx and a few > >others. This is their way of enticing designers to produce designs that > >will use their products. Anyone know anything about this? > > > Yes, but ONLY for educational purposes. They make it as a formal > donation for tax purposes. We have Altera and Atmel here at UMASS. > Hope this helps, When you say for "educational purposes" do you mean to institutions only, or to faculty and students as well? -- damir smitlener | damir@mindspring.com | smitty@optica.mirc.gatech.edu |Article: 882
I'm looking for references to implementations of hardware accelerators for volume rendering algorithms (or other computationally intensive graphics algorithm) based on FPGA's. Thanks in advance, -Arrigo BenedettiArticle: 883
We are currently looking for a good schematic capture package to replace our aging futurenet system from Data I/O. We are looking for something that will help us move to include PLD, CPLD & EPLD designs on-line. Any personal experiences out there for making the same transition ? Thanks in advance.Article: 884
> Has anybody out there successfully gotten the built in boundary scan (1149.1) in > the Xilinx 4000 series part to work? Were you able to simulate it? > > We are trying to synthesize with Exemplar to Xilinx designs. This works fairly > well, but when we hit boundary scan things fell apart. We can't simulate it. > > Neither LMC nor VBAK seem to want to deal with this issue. When we asked Xilinx > about this they said "Boundary scan can not be simulated". > > Any hints or suggestions on how to do this would be appreciated. if you entered your design from Synopsys you could then use their test insertion tools, and simulate the synopsys model, don't know how you would hand the xilinx delays though. Are you just looking for the functional simulation of the boundry scan? rich -- ************************************************************************** Richard Wieler rwieler@ee.umanitoba.ca University of Manitoba 204 474-7360 phone Software and Systems Development Group 204 261-4639 fax Winnipeg, Manitoba Canada http://www.ee.umanitoba.ca/~rwieler/richard.html ***************************************************************************Article: 885
In article <3kijj0$hh3@risky.ecs.umass.edu>, Mircea R Stan <mstan@hades.ecs.umass.edu> wrote: >In article <D5n9J2.2DD@world.std.com> rongood@world.std.com (Ronald E Goodstein) writes: >>I know this sounds kind of brave, but I heard that some FPGA vendors >>will give away Viewlogic design software that was customized for their >>FPGA's. I know some of the vendors are actel, altera, xilinx and a few >>others. This is their way of enticing designers to produce designs that >>will use their products. Anyone know anything about this? >> [...snip...] I remember when (way back when 1985-6) I bought our first FPGA kits that they came with [FutureNet?? (Actel)] and [OrCad?? (Xilinx)]. These days, I believe you are right; most vendors will bundle their PC kits with Viewlogic or OrCad for the price of the kit. The kits are not cheap though (although we've been through this before)... Regards, Mark -- /* Mark A. Indovina, Principal Staff Engineer mark_indovina@pts.mot.com */ /* MOTOROLA Strategic Semiconductor Operation, IC Technology Laboratory */ /* Mail Stop 63, 1500 Gateway Boulevard, Boynton Beach, FL 33436-8292 USA */ /* phone: 1-407-739-2379, fax: 1-407-739-3904 ...just speaking for me! */Article: 886
withrods@esvx17.es.dupont.com (dana s withrow) wrote: > We are currently looking for a good schematic capture package to replace our >aging futurenet system from Data I/O. We are looking for something that will >help us move to include PLD, CPLD & EPLD designs on-line. Any personal >experiences out there for making the same transition ? Not me, I'm still using Futurenet!!!!<g> Seriously, though we are looking for a new package. I don't like the concept of Orcad with the symbols not stored in the schematic. Viewlogic has a similar problem, but at least you can copy the directories associated with the project and everything will come along with it. So this is the direction I'm leaning. How 'bout you?Article: 887
If you have been designing FPGA's under Windows and live in Silicon Valley, then I have a wonderful opportunity for you. I am looking for an Applications Engineer to pioneer a new product line that is better than Viewlogic! Interested? Send me email at van@avcom.comArticle: 888
In <BENEDETT.95Mar20152030@caliban.dsi.unimo.it>
benedett@caliban.dsi.unimo.it (Arrigo Benedetti) writes:
>I'm looking for references to implementations of hardware accelerators for
volume
>rendering algorithms (or other computationally intensive graphics
algorithm)
>based on FPGA's.
I suspect this is not the volume rendering you mean, but maybe you'll find
it interesting anyway, a kind of software/hardware practice and
experience, if you will.
A while back, I did a design for a Gouraud shaded Z-buffered rendering
accelerator, whose datapath is compiled into a Xilinx XC4003A. Sure, it's
probably the most well understood graphics rendering problem, and my
implementation is simple at best (e.g. no blending, no textures), but I
wanted to see how far one could get, at home, on a hobbyist scale.
The inner loop (one scan line) of this simple polygon rendering algorithm
is:
// interpolate left to right, in (r,g,b) and z, and update
// pixels for which z is closer than zbuf[x]:
... set up fixed point z, dz, r, dr, g, dg, b, db ...
for (x = xleft; x < xright; x++) {
if (z < zbuf[x]) { // Z-buffer check
zbuf[x] = z; // update Z-buffer
buf[x] = pixel(r,g,b); // update image
}
// advance interpolants
z += dz; r += dr; g += dg; b += db;
}
When attached to 32-bits of DRAM or VRAM, and assuming a 16-bit Z-buffer,
this design required three passes, fast page mode streaming over memory, to
render a span of pixels across one scan line of a polygon. That is, I
implement the above as three passes :-
bit closer[];
// Pass 1: (check two Z-values per iteration)
// initialize z0, z1, dz0, dz1
for (x = xleft; x < xright; x += 2) {
closer[x] = (z0 < zbuf[x]);
closer[x+1] = (z1 < zbuf[x+1]);
z0 += dz0; z1 += dz1;
}
// Pass 2: (update up to two Z-values per iteration)
// reinitialize z0, z1, dz0, dz1
for (x = xleft; x < xright; x += 2) {
if (closer[x]) zbuf[x] = z0;
if (closer[x+1]) zbuf[x+1] = z1;
z0 += dz0; z1 += dz1;
}
// Pass 3: (update zero or one pixel value per iteration)
// initialize r, g, b, dr, dg, db
for (x = xleft; x < xright; x++) {
if (closer[x]) buf[x] = pixel(r,g,b);
r += dr; g += dg; b += db;
}
.. in hardware, in each case doing one loop iteration per clock (50 ns
clock).
((I separated passes 1 and 2 because I thought it would be easier to do
separate read and write passes on the Z-buffer memory, pipelined, rather
than one pass with lots of back to back read/modify/write traffic.))
Amortized cost: 100 ns/pixel, several times faster than an R4000 software
approach, even assuming packing several 8.8 bit fixed point interpolants
per 64-bit register.
Besides address sequencing and DRAM/VRAM control, the hardware to do the
above is only two 24-bit accumulators (for the 16.8 bit fixed point
interpolations of z0 and z1, and reused for 'r' and 'g' interpolation), one
16-bit accumulator (for the 8.8 bit fixed point interpolation of 'b'), and
two 16-bit magnitude comparators (for comparing zbuf[i] and zbuf[i+1] with
z0 and z1), plus a 64-by-2 bit SRAM to buffer closer/farther values (wider
polygons would be divided into abutting narrow ones). All of which fits
nicely in a "3000-gate" XC4003A.
((An "accumulator" in Xilinx-speak is an adder whose output is captured in
a register "sum", and whose inputs are sum and another register "delta", so
that "sum += delta" is formed each clock.))
I also considered using 16-bits/pixel (565 RGB) and adding error
distribution "dithering" to propagate the error at each pixel to later
pixels on the same line. This would require another adder at each
accumulator.
In my first couple of nights using ViewLogic, XBLOX, and XACT
1.4-something, I was able to design and compile the datapath of the above.
Unfortunately at that point I got stuck, trying to determine how to
interface an R3081 and then an R4000 to the FPGA, and so never did get the
darn rendering engine built. (The R4000 bus protocols are nontrivial,
especially when trying to interface to an FPGA with its own, nontrivial
input setup/hold times and output delays.) Now, when time permits, I am
designing a 32-bit RISC in the left half of an XC4010, and I hope to use
the right half for a rendering accelerator as described above. Here
"interpolate" (one iteration of one of the above passes) will be a machine
instruction.
Jan Gray
Redmond, WA
Article: 889
withrods@esvx17.es.dupont.com (dana s withrow) wrote:
>We are currently looking for a good schematic capture package to replace our
>aging futurenet system from Data I/O. We are looking for something that will
>help us move to include PLD, CPLD & EPLD designs on-line. Any personal
>experiences out there for making the same transition ?
Capilano's DesignWorks product is both a schematic capture and a
simulator. Multiple fpga libraries are now being assembled for it.
In addition it includes a FutureNet schematic reader so that your investment
in old schematics is not lost.
You can check out a demo at
ftp: ftp.wimsey.com in /pub/Capilano
or
phone: 604-522-6200
Don.
Article: 890I run a small UK only mail list of FPGA users that are interested in receiving infrequent Emails of information on AT&T FPGAs, predominantly ORCA but possibly some 3000 series. The mails are commercial but I try to limit information to what would be of genuine interest to Design Engineers. If you do not know the ORCA architecture it is a high end, fast, high density product competing along with Xilinx 4000/5000 & Altera Flex 8000/9000 to give an idea of positioning. If you are based in the UK and would like to be added to this mailing list please let me know. Please name your organisation, business & principal interests if possible as I may have other information from time to time that is not appropriate for bulk mailing. Declaration of Interest ----------------------- I work for a UK Distributor of AT&T, Bytech Electronics Ltd., but please don't hold them responsible for any errors on my part! Regards, Ian Packer.Article: 891
benedett@caliban.dsi.unimo.it (Arrigo Benedetti) wrote: > > I'm looking for references to implementations of hardware accelerators for volume > rendering algorithms (or other computationally intensive graphics algorithm) > based on FPGA's. > > Thanks in advance, > > -Arrigo Benedetti For accelerated volume rendering I suggest contacting Octree at 408 257-9013. Talk to Bruce Edwards (bruce@octree.com) or Don Meagher (dm@octree.com). Don and Bruce have about fifteen years of experience (each, I think) in volume rendering. For volume visualization (I don't know if it's related) contact Todd Cook at tac@ece.rutgers.edu. nickArticle: 892
I am looking to perform a (252,128) BCH error-detection and correction coding and decoding function in an Actel ACT 2 FPGA for a communications device. The brute-force method of calculating the BCH parity field for transmission and checking it upon receipt will use LOTS of logic. Is anyone aware of any tricks I can use (or where to look in the literature to find them) to minimize logic usage when doing BCH coding/decoding? I'm able to trade-off increased processing time in order to reduce logic, if that helps. Replies via email to fcostantini@carib.vf.mmc.com would be great. Thanks in advance for your help. ===================================================================== Frank Costantini fcostantini@carib.vf.mmc.com Please note that the above does not necessarily reflect the views of my employer. =====================================================================Article: 893
REGISTRATION AND HOTEL INFORMATION
IEEE Symposium on FPGAs for Custom Computing Machines
April 19-21, 1995
Marriott at Napa Valley, Napa, California
(formerly the Sheraton at Napa Valley, site of FCCM'94)
3425 Solano, Napa, California 94558
707-253-7433, 707-258-1320 (fax)
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All rates are U. S. dollars. Checks must be drawn on a U.S. bank
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c/o Ken Pocek, Intel, Mailstop RN6-18, 2200 Mission College Blvd.,
Santa Clara, CA 95052 (USA).
Article: 894I have had a few requests to post the List of FPGA-Based Computing Machines to this group. Since it is fairly large (over 40K), I'll save bandwidth and post the URL. It may be found off of my homepage at "http://www.utexas.edu/~guccione/". I also have some related bibliographies there that may be of interest. For those without WWW access, there is an email server called Agora that should permit you to get a copy of this list. Send email to "agora@mail.w3.org", with no subject, and the line: send http://www.utexas.edu/~guccione/HW_list.html in the body. A copy should be sent to you via email. For more information on the Agora service, send a message with "help" in the body. And of couse, any additions or corrections to the list are appreciated. -- Steve -- 3/22/95Article: 895
Just thought I would post the URL for the Reconfigurable Logic Lab at
Brigham Young University. It has all of standard stuff: papers,
bibliographies (with abstracts), Splash-II tutorials, oh, and some
perfectly awful pictures of the people that work in the group :-).
Hope you find it useful.
http://splish.ee.byu.edu
--
Brad L. Hutchings (801) 378-2667 Assistant Professor
Brigham Young University - Electrical Eng. Dept. - 459 CB - Provo, UT 84602
Reconfigurable Logic Laboratory
Article: 896This isn't a mainline FPGA problem, but somebody might have a good suggestion. What sort of chips do people use to implement old fashioned uCode machines? I'm thinking about the type of thing you build with a wide ROM, a register to hold the instruction, another register to hold the PC, and a PAL or such for the branch logic in the bottom bits of the PC. The main reason that I say "uCode" is that I'm interested in a large number of states rather than the relatively simple state machines that you build out of gates and FFs. I want to "write the code" as though it were a software problem rather than drawing circles and arrows. The Altera EPS448 is an interesting chip for that sort of machine. It combines the ROM and registers and branch logic in a single chip. You get 8 branch bits in and 16 instruction bit out in a PLCC28. (You are SOL if you need more uCode space.) The PC (ROM address) is burried inside the chip. Anybody know any modern chips like it? Any FPGAs good at that sort of thing?Article: 897
I would like to get data on the sizes of past ( since their launch) and present FPGAs in terms of Gate and Pin Counts. Also I would also like to know the gate capacities of past & present FPGA based Hardware Emulators. Any help in this regard would be greatly appreciated. Send replies to : ukhan@microelec.mirc. gatech.edu ********************************************************** Ubaid R. Khan khan@ee.gatech.edu Electrical & Computer Engineering (404)-853-9924/25 Georgia Institute of Technology (404)-892-5962 (H) Atlanta, GA 30332 **********************************************************Article: 898
Hi! Is there a FAQ available? Thank you in advance! FranzArticle: 899
Hi! I have the problem to implement a 24-Bit integer division into the Xilinx 4000 series. I currently use a dumb compare-operands, subtract and shift operands procedure, but it needs an ugly state-machine for control. Is there anything more effective? (maybe a "bit-serial-divider"?) Thanks in advance for your replies, Hermann-Josef Hebbelmann -- +---------------------------------------------------------------------------+ | Hermann-Josef Hebbelmann | eMail: inhjh@asterix.rz.tu-clausthal.de/\ | | Spiegelthaler Str.10 | /\ / \| | D-38678 Clausthal-Zellerfeld | / \/ | | Tel. 05323/83882 | / | +---------------------------------------------------------------------------+
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