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In article <3jqfis$a4o@vanbc.wimsey.com> rob@vanbc.wimsey.com (Rob Semenoff) writes: >I presume vendors are increasing FPGA density by going >for bigger dies and smaller feature size. > >Are any trying to get more logic into a package for >less money by interconnecting dies in a package >in some programmable, or customer-specified way ? > >-rob Yes. Altera has (or will have) a product that includes 4 of their larger FLEX familiy devices together with a programmable interconnect chip. I don't know if it is cheaper or more expensive that buying the 5 chips separately. Philip FreidinArticle: 851
AT&T have done some application notes on DSP functions for their ORCA family of FPGA including async., half & fully pipelined multipliers which give reasonable results. If anyone in the UK wants details let me know otherwise try your local AT&T Microelectronics office or Disti. Regards, Ian. (ipacker@bloggs.win-uk.net)Article: 852
Below is the preliminary program for FCCM '95. For the web-wise it's also available through: http://www.super.org:8000/FPGA/caf.html See you in Napa! -jeff FCCM'95 Program IEEE Symposium on FPGAs for Custom Computing Machines Napa Valley, CA April 19-21, 1995 Co-Chairs Kenneth L. Pocek Peter M. Athanas Intel Virginia Polytechnic Institute Mail Stop RN6-18 Bradley Dept. of Electrical Eng. 2200 Mission College Blvd 340 Whittemore Hall Santa Clara, CA 95052 Blacksburg, VA 24061-0111 (408)765-6705 voice (703)231-7010 voice (408)765-5165 fax (703)231-3362 fax kpocek@sc.intel.com athanas@vt.edu Organizing Committee Jeffrey Arnold, IDA SRC Fred Furtek, Atmel Corp. Duncan Buell, IDA SRC Brad Hutchings, Brigham Young Univ. Pak Chan, UC Santa Cruz Tom Kean, Xilinx (UK) Apostolos Dollas, Tech. Univ. Crete Wayne Luk, Imperial College (UK) Wednesday April 19, 1995 Session 1: Custom Computing Platforms A FCCM for Dataflow (Spreadsheet) Programs A. Lew, R. Halverson University of Hawaii at Manoa MORPPH: A MOdular and Reprogrammable Real-time Processing Hardware T. Drayer, W. King, J. Tront, R. Conners Virginia Tech Architecture of a FPGA-based Coprocessor: The PAR-1 Javier Moran, Eduardo Juarez Martinez, Sadot Alexandres Fernandez, Juan Meneses Chaus Technical University of Madrid Session 2: Custom Computing Platforms Teramac - Configurable Custom Computing R. Amerson, R. Carter, B. Culbertson, P. Kuekes, G. Snider HP Labs Common Processor Element Packaging B. Box, J. Nieznanski Lockheed Sanders Enable++: A Second Generation FPGA Processor H. Hogl, A. Kugel, J. Ludvig, R. Manner, K. Noffz, R. Zoz University Mannheim (Germany) Lunch Session 3: Signal Transport Design and Implementation of a Multicomputer Interconnection Using FPGAs Chun-Chao Yeh, Chu-Hsing Wu, Jie-Yong Juang National Taiwan University Routability Improvement Using Dynamic Interconnect Architecture J. Li, C.K. Cheng UC San Diego Reconfigurable Real-time Signal Transport System Using Custom FPGAs K. Hayashi, T. Miyazaki, K. Shirakawa, K. Yamada, N. Ohta NTT Optical Network Systems Laboratory Session 4: Run-time Reconfiguration Design Methodologies for Partially Reconfigured Systems J. Hadley, B. Hutchings Brigham Young University Issues in Wireless Video Coding using Run-time Reconfiguration FPGAs C. Jones, J. Oswald, B. Schoner, J. Villasenor UCLA Run Time Reconfiguration of FPGA for Scanning Genomic Databases E. Lemoine, D. Merceron University Montpellier II (France) A Dynamic Instruction Set Computer M. Wirthlin, B. Hutchings Brigham Young University Thursday April 20, 1995 Session 5: Applications 1 Emulating Static Faults Using a Xilinx Based Emulator R. Wieler, Z. Zhang, R. McLeod University of Manitoba Acceleration of Template-Based Ray Casting for Volume Visulization Using FPGAs M. Dao, T. Cook, D. Silver Rutgers University Flexible Image Acquisition using Reconfigurable Hardware Mark Shand Digital Equipment Corp. Session 6: Compiler Issues The Transmogrifier C Hardware Description Language and Compiler for FPGAs David Galloway University of Toronto Architectural Descriptions for FPGA Circuits Satnam Singh University of Glasgow Quantitative Analysis of Floating Point Arithmetic on FPGA-based Custom Computing Machines N. Shirazi, A. Walters, P. Athanas Virginia Tech Lunch Session 7: Compiler Issues A Declarative Approach to Incremental Custom Computing W. Luk Imperial College of Science, Technology, and Medicine A C++ compiler for FPGA custom execution units synthesis C. Iseli, E. Sanchez Laboratoire de Systemes Logiques Implementing a Genetic Algorithm on a Parallel Custom Computing Machine N. Sitkoff, M. Wazlowski, A. Smith, H. Silverman Brown University Session 8: Applications 2 Rapid Prototyping of a RISC Architectur for Implemention in FPGAs Russell Meier Iowa State University Implementation of a Parallel VLSI Linear Convolution Architecture Using the EVC1s H. Chow, S. Casselman, H. Alnuweiri University of British Columbia Convolution on Splash 2 N. Ratha, A. Jain, D. Rover Michigan State University Implementing Hidden Markov Modelling and Fuzzy Controllers in FPGAs Herman Schmit, D. Thomas Carnegie Mellon University Friday April 21, 1995 Commercial Custom Computing Machines, Software, and DevicesArticle: 853
You may want to have a look at "A Cell Set for Self-Timed Design using Actel FPGAs" by Erik Brunvand of the University of Utah. The document reference number is UUCS-91-013. Order info. is available at ftp.cs.utah.edu. Cost is very low. JLGArticle: 854
I have Protel, and they send me promo stuff. The Australian newsletter recently announced that Adv Schematic can link to Xilinx (ie they have a library and an XNF extractor), for $A500. ($A=$US0.73 approx) David le ComteArticle: 855
AT&T ORCA They have 4 FF/Latches per macrocell sharing the same clock which can be inverted, clock enable is supported on FFs. Theoretically you could have a different clock for each macrocell as any input can be used for clocks. The FFs can use sync or async preset & clear, clock enable & async global reset. The FFs/latches can be used independantly of LUT logic. A handy feature of the latches/FF is the capability to act as flow through mux. So fairly flexible.Article: 856
I would like to propose a newsgroup for Programmable Logic Device (PLD) users (suggested name news:biz.programmable-logic). It would be an on-line discussion group for all topics related to PLD's: Applications, Performance Benchmarking, EDA/CAD tools, Logic Synthesis issues, Device Testing, Quality & Reliability, New Product Announcements, User Questions, Help, etc. Semiconductor vendors such as Actel, Altera, AMD, Atmel, ATT Microelectronics, Cypress, Lattice, QuickLogic, Texas Instruments, & Xilinx would be very happy to hear from real users who express their difficulties & successes in using PLD's of all types - PAL/GAL, EPLD, CPLD, & FPGA's. The newsgroup postings would be an "inside track" to the marketing & product planning departments of these companies. PREP (A PLD benchmarking trade organization) would be the organizing body for most of the on-line activities. A key question: Should the newsgroup be moderated? The orientation of this newsgroup would complement URL:news:comp.arch.fpga in that it would allow some commercial traffic & marketing announcements. While serving the user should be the focus for both, proper netiquette demands separation. Ideally the biz group would focus on all types of programmable logic as well as related issues such as EDA/CAD tools. Email me at: <mailto:Nick.Schmitz@amd.com> if you're interested or post a response to URL: news:biz.marketplace.discussionArticle: 857
Hi, I have been working on Field Programmable MCMs for the last three years in a research group at UC Santa Cruz under the direction of Wayne Dai. We published papers describing our work at last years FCCM in Napa, the 1995 Multichip Module Conference, and at the recent (1995) Fpga symposium. Our first generation FPMCM was successfully demonstrated at the ARPA Electronic Packaging and Interconnect meeting in early March. There are four major FPMCM efforts that I am aware of. 1) The Altera effort combines for "12.5K gate" FPLDs in individual ceramic ball grid arrays onto a multilayer ceramic substrate with a single Aptix FPIC. The FPIC provides the ability to route from any FPLD pin to any other. Although it has been claimed that this approach is not really MCM, it does provide a unified capability within a single module. I suppose you can call it wahtever you want. Advantages of the ceramic approach include full testability of components, 100% reworkability, and efficient thermal management. Disadvantages include large size and weight, high cost, and inability to get enough IO to the chips. 2) Several years ago (1991?) Abbas El Gamal's group at Stanford first proposed FPMCMs at the MCM conference and FPGA workshop. They recently publihed a paper on FPMCM partitioning for their Frame architecture. The basic idea is to add interconnect resources to the pad frame of chips and then interconnect them witha fixed wiring pattern. To the best of my knowledge, they have not built anything yet. 3) National Semiconductor is working on a FCMCM using thier fine grain CLAy FPGAs. They combine four large Clay-31 parts on a single multilayer ceramic substrate made by IBM. The device is currently being employed as part of a satellite comunications system where the reconfigurability of the FCMCM is used to time-multiplex the hardware between send and receive modes, saving area in the sattelite. NSC is the first to actually redesign thier die to take advantage of the interconnect density of FPMCM and their architecture provides almost seamless interconnections between chips. 4) My group at UC Santa Cruz has developed a 25K~40K gate FPMCM using 12 Xilinx 3042s and a single Aptix FPIC on a silicon substrate. The entire device measures about 3cm square. Our experiemental architecture uses FPIC for most inter-device connections, though some direct connections are provided. We are currently developing image filtering and compression applications for this system. Our effort is aimed at using the high interconnect density of the silicon substrate and the high IO counts achievable with area-IO to deliver seamless integration between chips. Large FPLDs can then be partitioned into several chips, lowering the cost of the silicon. We are currently developing a 200K gate FPMCM with the next generation of CMOS FPGAs. Details of our work are available through WWW at http://www.cse.ucsc.edu/~joel All of these efforts demonstrate that MCM technology has considerable advantages for field programmable systems. Unfortunately, they also demonstrate that there are numerous challenges (bare die test, packaging cost, architecture) that impede efforts to deliver real FPMCMs for reasonable amounts of money. As the MCM infrastructure becomes more mature, these problems shoul be solved, and FPMCMs may become a reality. Please feel free to contact me with any questions.Article: 858
Wrong mailaddress ??? Mail error was: 550 <Nick>... User unknown --- returned mail follows --- To: <Nick.Schmitz@amd.com>, Nick, Schmitz Subject: Re: <--> Proposed Newsgroup for Programmable Log That's my comment: I'd be very interested in a PLD + tools newsgroup Cheers --- -------------------------------------------------------- Andreas Kugel Chair for Computer Science V Phone:(49)621-292-5755 University of Mannheim Fax:(49)621-292-5756 A5 D-68131 Mannheim Germany e-mail:kugel@mp-sun1.informatik.uni-mannheim.de --------------------------------------------------------Article: 859
In article <fliptronD5DDEr.Juz@netcom.com>, fliptron@netcom.com (Philip Freidin) writes: >In article <3jqfis$a4o@vanbc.wimsey.com> rob@vanbc.wimsey.com (Rob Semenoff) writes: >>I presume vendors are increasing FPGA density by going >>for bigger dies and smaller feature size. >> >>Are any trying to get more logic into a package for >>less money by interconnecting dies in a package >>in some programmable, or customer-specified way ? >> >>-rob > >Yes. Altera has (or will have) a product that includes 4 of their larger >FLEX familiy devices together with a programmable interconnect chip. >I don't know if it is cheaper or more expensive that buying the 5 chips >separately. > >Philip Freidin > Altera told us that this device is targeting the ASIC prototype market and is priced accordingly ($5,000 each) :-)Article: 860
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Has anyone experienced adverse effects when using the tie unused inputs in makebits? It seems that this option can add an arbitrary delay to any net which has not been flagged as critical. Even after ppr has been run and the given timing constraints met, makebits can come along and add arbitrary delays. In a routing for an XC4010, makebits added 30ns to one of our nets which caused the design to fail even though the xact tools claimed that timing constraints had been met. If anyone has experienced this - please let me know what you did to overcome the problem (we are currently running without the tie option). Emma -- =============================================================================== Emma Mowat R&D Telecomms Systems Division Hewlett-Packard Ltd. South Queensferry Email : emma@hpsqf.sqf.hp.com EH30 9TG Phone : +44 31 331 7857 SCOTLAND FAX : +44 31 331 7987 ===============================================================================Article: 862
In article <3k4lst$sa9@amdint.amd.com> Nick.Schmitz@amd.com writes: "I would like to propose a newsgroup for Programmable Logic "Device (PLD) users There is one, and this is it. Although comp.arch.fpga really serves those who wish to discuss PLDs and FPGAs as a computer architecture, there was very little traffic until it was "adopted" by those of us who want to discuss PLDs and FPGAs in general. We should really propose something like sci.electronics.pld. But in practice, here we are. " "(suggested name news:biz.programmable-logic). " "It would be an on-line discussion group for all topics "related to PLD's: Applications, Performance Benchmarking, "EDA/CAD tools, Logic Synthesis issues, Device Testing, "Quality & Reliability, New Product Announcements, User "Questions, Help, etc. Again, that's precisely what happens in comp.arch.fpga. If we ever get around to giving the group its proper name, you should write the new charter! " "Semiconductor vendors such as Actel, Altera AMD, Atmel, "ATT Microelectronics, Cypress, Lattice, QuickLogic, Texas "Instruments, & Xilinx would be very happy to hear from "real users who express their difficulties & successes in "using PLD's of all types - PAL/GAL, EPLD, CPLD, & FPGA's. "The newsgroup postings would be an "inside track" to the "marketing & product planning departments of these "companies. " "PREP (A PLD benchmarking trade organization) would be the "organizing body for most of the on-line activities. A key ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ "question: Should the newsgroup be moderated? " Aaargh! The whole point of Usenet IMHO is that, while for good reason a small minority of groups are moderated, none of them has someone *organizing* them. Who wants to be told what to discuss? " "The orientation of this newsgroup would complement "URL:news:comp.arch.fpga in that it would allow some "commercial traffic & marketing announcements. While "serving the user should be the focus for both, proper "netiquette demands separation. Ideally the biz group would ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Who says? "focus on all types of programmable logic as well as "related issues such as EDA/CAD tools. " Over the last year, there have been a number of discussions on this, and the consensus is that the group *positively encourages* the device and tool vendors to speak. Even short product announcements are OK, only blatant, non-informative, or long-winded advertising is not wanted. " "Email me at: " "<mailto:Nick.Schmitz@amd.com> " "if you're interested or post a response to " "URL: news:biz.marketplace.discussion Many of the users of this group would not look in a biz. hierarchy group (and some would not be able to get it at all). Please spend a little time reading the group, and try making some postings in it. If you still think the group's in the wrong place, then let's get a proposal together to start sci.electronics.pld Until recently, this group has struggled, with only a handful of postings a week. Please become more familiar with what goes on here (and with Usenet as a whole) before trying to split it. Now that would be good netiquette :-) -- David PashleyArticle: 863
>we want to separate it into several chips such as 2 of xc4005. >How can we do ? Can we use PPR program to do that for us ? PPR DOES NOT do design partitioning into multiple FPGAs >Or we must cut the circuit down into 2 circuits ourself ? Yes, you will have to partition yourself. I heard that NeoCad has multi-fpga partitioning tools, you may try that if you have access to it. Good luck. KhalidArticle: 864
Cliveden Technical Recruitment specialises in the supply of ASIC/FPGA/DSP design engineers on a contract basis. We currently have several clients throughout the UK and Europe seeking qualified engineers for longterm contracts. See the latest vacancies on the WWW: http://www.cityscape.co.uk/users/ci87/index.html Email: ci87@cityscape.co.uk M BurgessArticle: 865
> I am not leaving my e-mail address because of the flames and revocation
> of my account for having posted this.
Translation: I knew in advance this was wrong, and I know I'm posting
for profit in groups that have nothing to do with this, so
I've done it anonymously to try and get away with it anyway.
> ############# Personal ad placement service #############
I see the return address in the header has been mangled. Is
there any way to reach the admin of the machine this came from?
Chuck Corley
chuckc@sr.hp.com
Article: 866In <3jqfis$a4o@vanbc.wimsey.com> rob@vanbc.wimsey.com (Rob Semenoff) writes: > >I presume vendors are increasing FPGA density by going >for bigger dies and smaller feature size. > >Are any trying to get more logic into a package for >less money by interconnecting dies in a package >in some programmable, or customer-specified way ? > >-rob > Altera currently has an MCM "device" called the EPF8050M. It is basically 4 EPF81188 devices (~12,000 gates each) interconnected by an Aptix FPIC. The Aptix device then connects to a 560 pin PGA package.Article: 867
David le Comte (davelec@extro.ucc.su.OZ.AU) wrote: : I have Protel, and they send me promo stuff. The Australian : newsletter recently announced that Adv Schematic can link to : Xilinx (ie they have a library and an XNF extractor), for : $A500. ($A=$US0.73 approx) : David le Comte Yeah, with caveats. There's NO info supplied with the software, and it requires hand-editing of the resultant XNF file so it'll work properly. Given a choice, I'd stick with OrCad SDT 3.12 (the ancient version) if at all possible. And forget using any of your old OrCad schematics with the new Protel stuff, as the graphical parts are different. Most of a converted OrCad schematic will require redrawing from scratch (grumble).Article: 868
testArticle: 869
Hi, Could anyone give me info. on the interface between synopsys and XACT tools?. What I mean by interface is, that synopsys generates .sxnf files and XACT accepts only .xnf files. Also, are there any synopsys target and link libraries that must be used when synthesizing in synopsys when targetting Xilinx FPGAs? -JatanArticle: 870
IST opens new office in Santa Clara, CA. Phone 408-982-2557 FAX 408-982-2558Article: 871
I just wanted to give the engineers out there a heads up about the upcoming
SNUG '95 Design Contest. For those new to SNUG, it stands for the SyNopsys
Users Group and it's a Synopsys customer to customer get together. Although
it's financially underwritten by Synopsys, Inc. -- no salespeople or sales
pitches are allowed nor tolerated at this once a year meeting; it's for
users to share their success/horror stories with other users in hopes of
developing a better understanding of how to use Synopsys and other related
EDA tools.
The Design Contest we're having this year at SNUG '95 is something of an
experiment. (We've never done it before.) As the guy running & judging
it, I (John Cooley) would like to point out what's going to happen.
Designers will be given 1 1/2 hours to create a very simple design using
Verilog or VHDL and the winning team/person will be the one who creates
the fastest possible design. The winning person/team will get $1000.
In the event of a tie, the smallest design will win.
Here's the specifics for the contest:
- We'll have 4 SUN's and 2 HP's for designers to use.
- We'll have Cadence's Verilog-XL and Turbo-Verilog plus
Chronologic's VCS simulators on the machines for the
Verilog userss to choose from.
- We'll have Synopsys's VSS and Cadence Leapfrog for the
VHDL oriented designers. (Model Tech bowed out of offering
their VHDL for this contest.)
- All Synopsys synthesis tools for Verilog & VHDL will be there.
- We'll have LSI 300K gate level libraries for everything
as the technology everyone's designing in.
- Seva Technologies, Inc. will be providing a Verilog and a VHDL
test environment that designers can use to confirm the
functionality of their source code.
- Plain vanilla EMACS, "vi", textedit and whatever editors
that come with SUN's & HP's will be used. No loading of
tapes or templates (i.e. for EMACS) will be allowed. Everything
must be typed in via a keyboard.
- It's important to be realistic with what you'll be asked to do.
With 1 1/2 hours, I'm not going to say: "Please design a complete
386 clone & synthesize it to gates NOW!"
Time slots and organizing issues:
- There will be three time slots designers can sign up to be in on
Thursday: 10:00-11:30 (session 1), 1:15-2:45 (session 2), and
3:00-4:30 (session 3). This means that there will be 18 available
"slots" for contestants to be in.
- Although SNUG '95 is going to be free form as far as what people
can go, see & do, preference will be given to those who SIGN UP
EARLY for one of the 18 possible slots in the Design Contest. At
most, I'd like to see design teams that are no more than 3-4 people.
Because we're restricted by slots, it's important that contestants
Darla (the SNUG '95 registrar) what languages they can design in
plus what preference of sessions they have. We may have to make
teams of designers (which won't hurt because there's a lot to do
in just 1 1/2 hours.)
To register for SNUG '95 and/or the Design Contest contact Darla Marmon
at (800) 344-7684 or "darlam@synopsys.com"
The winning person/team will be announced Thursday at the closing of
SNUG '95. (Plus I'll post who won, what they had to design, their source
code, Synopsys scripts and results in the following week's ESNUG.)
SNUG's in 5 days and OVI's in 9 days -- see you there!
- John Cooley
SNUG '95 Design Contest Judge
(and Full Time ASIC/FPGA Design Consultant)
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3196 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 872
Has anybody out there successfully gotten the built in boundary scan (1149.1) in
the Xilinx 4000 series part to work? Were you able to simulate it?
We are trying to synthesize with Exemplar to Xilinx designs. This works fairly
well, but when we hit boundary scan things fell apart. We can't simulate it.
Neither LMC nor VBAK seem to want to deal with this issue. When we asked Xilinx
about this they said "Boundary scan can not be simulated".
Any hints or suggestions on how to do this would be appreciated.
---
David Bishop
INTERNET: bishop@utica.ge.com | The opinions voiced are mine
US MAIL: 7129 E Carter Rd, Rome NY 13440 | and not my company's.
PHYSICAL: 43.150N 75.414E 650' |
Article: 873In article fd5@mozz.unh.edu, pss1@hopper.unh.edu (Paul S Secinaro) writes: > lemieux@eecg.toronto.edu (Guy Gerard Lemieux) writes: > >Altera has a device called the 8050M. it is a multichip module > >containing 4 FLEX 81188 FPGAs (1188 flip flops, 1008 4-input LUTs) > >and an Aptix FPIC (FP interconnect chip). i think they claim > >50,000 gate capacity. it costs $5k US. > > Is this really a multichip module? Last time I glanced at the > brochure, it looked more like a small motherboard with four > normally-packaged '1188's and the Aptix chip soldered on, with some > pins on the bottom, probably with all the I/O pad and pin-to-pin > delays that implies (especially when passing through the Aptix). >From reading the data sheet: The Altera parts are just ball grid arrays, but the Aptix part is a "bump" mounted die on the bottom, which pretty much makes it an MCM. Also, the Aptix is a passive device, and will probably add only about 4ns delay. > Also, I was at an Altera workshop a few months ago and the spin that > they put on this device was that it was mainly intended for fast > gate-array prototyping, not production use. At $5k/part, a better way of putting it is "it is mainly -marketed- for fast gate-array prototyping, not production use." If you want to put the part into a high-volume product, I am sure that Altera will support you all the way. Your product is going to be pretty expensive. I haven't used the part, and don't know much about it other than what I read in the data sheet. -tomArticle: 874
Altera has automatic multi-part partitioning for its 7K and 8K parts. The same design can be used without changing it to retarget and try partitions in each of the families.
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