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In article <1995Feb9.125827@wcsub.ctstateu.edu>, belanger002@wcsub.ctstateu.edu writes: > TI calls the product "ASSET. > From the OEM price book, the card appears to cost abour $500, > and the software, $3500. > Boy, was I ever off! I was looking at the wrong page. TI part # ASSET-AIT-PC ASSET Interconnect Test Product, $14,995.00 Double Ouch! Gerry BelangerArticle: 701
neal@ctd.comsat.com (Neal Becker) writes: >octtools is part of ptolemy. Try ftp.ptolemy.berkeley.edu. Yes, >ptolemy has been ported to Linux! No, *parts* of octtools are part of Ptolemy; the Oct database stuff and the Vem editor are shipped with Ptolemy but the CAD tools aren't. Also, the site name is ptolemy.eecs.berkeley.edu. See the WWW page http://ptolemy.eecs.berkeley.edu/ for more on Ptolemy. There's also a newsgroup: comp.soft-sys.ptolemy -- -- Joe Buck <jbuck@synopsys.com> (not speaking for Synopsys, Inc) Phone: +1 415 694 1729Article: 702
>>Does anyone know of an inexpensive method for accessing the boundary scan >>capabilities of an FPGA? I have found several devices to do this, but so >>far the boundary scan capabilities have all been add ons to extremely >>expensive test equipment. All we need is some kind of device (PC card and >>cable?) to interface with the IEEE1149.1 standard TAP, and some software to >>drive it. The Altera FLEXlogic FPGAs are programmed through a JTAG port. All they do is hook the TCK, TMS, and TDI pins to the pins of a PC port. The TDO pin hooks to one of the status lines of the printer port. Then it's a relatively simple matter of pulsing the TCK line with the appropriate values on the TMS and TDI lines to make the receiving device obey JTAG commands. I assume you could do the same with any device that has JTAG capabilities. -- || Dave Van den Bout || || Xess Corporation ||Article: 703
In article <3h5s7sINNc3r@salmon.wv.tek.com> weedk@salmon.wv.tek.com (Kirk A Weedman) writes: >Anyone know where I can get a Verilog description >for SCSI design? > > Kirk weedk@pogo.wv.tek.com Mee too! Any primer on Verilog models of SCSI protocols/components/the lot would be received with gratitude! Frank Ieromnimon, PACE Project, dept. of Computer Science, University of Essex.Article: 704
I think you're thinking about the Asset system, which TI sold off to another company, and I have their literature around here somewhere. You might want to see Proceedings of the International Test Conf. 1992, Baltimore, MD Sept. 20-24 pgs. 84-90 "Design Verification of a High Density Computer Using IEEE 1149.1" by Wayne T. Daniel, Texas Instruments 6500 Chase Oaks Blfd. M/S 8407 Plano, TX 75023. In that paper, the strategy uses Asset to scan through their design. Randy B.Article: 705
Hello. I need to Manchester decode a 5Mbit per second serial bit stream.
I was wondering if it would be practical to implement a digital
phase-locked loop inside an XC4008 Xilinx chip? This way, I could
recover the clock signal without any external circuitry.
Does this sound like a workable idea? Any idea how many CLB's/gates/etc.
it would take, given that the Xilinx chip has access to a 40MHz system
clock? (Ok, I'm dreaming now) Does anyone have working logic that does
this?
Regards,
Jeff
--
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Jeff Collins jwcollin@engr.ucdavis.edu
Intelligent Manufacturing Systems/ collinsj@ece.ucdavis.edu
Mechatronics Lab, 1065 Bainer Hall collinsj@cs.ucdavis.edu
University of California, Davis jwcollins@ucdavis.edu
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Article: 706
Altera just announced that it's giving out free PCI design kits (which are
essentially generic templates that users can customize to their specific
PCI oriented design) that target its MAX 7000, MAX 9000, FLEX 8000 and
FLEXlogic device families. Note: this is not a drop-in PCI interface but
something an Altera customer can use as a good start towards putting a
PCI compliant interface in their FPGA design.
Right now this PCI kit is written in Altera HDL (AHDL -- which is somewhat
like VHDL) and it's fully supported in Altera's MAX+PLUS II proprietary
synthesis tool. (I'm told that non-AHDL oriented designers can also import
Verilog, EDIF & VHDL into the MAX+PLUS II design environment.)
To get the free Altera PCI design kit, call (800) 525-8372 or (408) 894-7144.
The PCI Local Bus spec can be purchased from the PCI Special Interest Group
for $25.00 plus shipping at (800) 433-5177 or (503) 797-4207.
- John Cooley
part time EDA Consumer Advocate
full time ASIC & FPGA Contract Designer
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3196 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 707
In article <D3nHH4.EqD@acsu.buffalo.edu> crouse@acsu.buffalo.edu (Daniel R. Crouse) writes:
>Does anyone know of an inexpensive method for accessing the boundary scan
>capabilities of an FPGA? I have found several devices to do this, but so
>far the boundary scan capabilities have all been add ons to extremely
>expensive test equipment. All we need is some kind of device (PC card and
>cable?) to interface with the IEEE1149.1 standard TAP, and some software to
>drive it.
Try for instance (Europe):
JTAG Technologies BV tel: +31-40-785104
P.O.Box 1542 fax: +31-40-785739
5602 BM Eindhoven
The Netherlands
Or (USA):
Corelis Inc. tel: (310) 926-6727
12607 Hidden Creek Way fax: (310) 404-6196
Cerritos, CA 90701
USA
They sell a small device to plug into the Centronix port of your PC, together
with software. If you need VXI-interface, they have that as well.
You may also buy a getting started kit for Boundary Scan, if that is needed.
We bought one of these testers this winter, but I have not yet had time to
play with it.
Good luck,
Bjorn BL.
______________________________________________________________________
s-mail: e-mail:
| | | Bjorn B. Larsen, Ph. D. bjoernb@elektro.tih.no
|__ |__ | Sor-Trondelag College
| \| \| Gunnerus gate 1
|__/|__/|_ N-7005 TRONDHEIM tel: +47 - 7389 6288
NORWAY fax: +47 - 7389 6286
______________________________________________________________________
Article: 708Does anybody have an idea on how to evaluate the time to integrate in a macrocell or fpga :a small 16bit, 65kwords, dma, i/o interface, float unit running at 18Mhz. Is it possible to do that if my company would pay 100k to 150k in r/d? Any CommentsArticle: 709
followup-to: comp,arch.fpga
Hi,
I'm currently working on the design of a video RAMDAC
evaluation/demonstration board, and would like some comments
and/or help on an idea I have. The board is like this:
--------------------------------
| VRAMr |
PC | _____ |-
PARALLEL O ------ V |RAM| | -> RGB/sync out
INTERFACE O |FPGA| R |DAC| |-
---> O ------ A ----- |
| XT M |
| AL b VRAMg |
|______________________________|
The FPGA can be programed via the pc printer port.
The RAMDAC is a fast part (220MHz), so there have to be two
ways to display an image,
1. A true color image downloaded to the VRAMS
(works up to 30MHz dot clock officaly, but will work
to 50-60MHz (most of the time) if the supply voltage is
changed slightly),
2. For the fast pixel rates, via pattern generation on the FPGA.
(grids, rams cross hatch etc.)
The FPGA also handles the SYNC generation, and the control interface
to the RAMDAC.
However, I was wondering if it is possable to use the FPGA to
generate a fractal image, in *real time*, to display via the
RAMDAC. I know that such a task is maths intensive, but:
1. The FPGA has 5000 internal gates.
2. It can run at 250Mhz internaly
3. A low resolution image will do (say 160x100).
4. A low limit on zooming into the fractal will do.
5. A lowish video frame rate will do (<50Hz)
That gives about 160x100x50=800K pixels/sec to calculate.
=~300 clock cycles per pixel
Can a point on the Mandel set (or any other fractal)
be calculated in such a time (in hardware)?
I would like to be able to pan and zoom the image, via the
parallel interface, but that should be trivial once the
calculation routine works.
So if any good Fractal experts/ALU designers/FPGA experts
find this idea interesting and/or have any ideas,
please *email* me at the address below, since
my NEWS access is slow, so I may not be able to read all
the messages in all the groups that this was posted to.
If there is interest in the topic, I will sumarise and
email/post the results to interested parties/newsgroups.
Thanks,
Ciaran King.
Ciaran King cking@accutron.ie /\
Accutron Ltd. - Product R&D / \
* Process monitoring/control / <--\-
* Embedded systems design / \
* Data acquisition systems /___/\___\
Article: 710I caught some discussion about sources for JTAG S/W. Anyway, AT&T offer something they call "Tapdance" that runs on DOS & SunOS. I don't know anything about it but the phone number is: 1-800-462-8146. The datasheet I found also had a contact name of Scott Davidson sd@ohm.att.com They also produce a Boundary-Scan Master Evaluation Kit for the PC which includes H/W & S/W to turn a PC into a tester. They also produce a Boundary Scan Master I.C. part no. 497AA.Article: 711
Did a PLL and Manchester Decode in an Altera EPLD, worked out great. Altera actually had alot of it defined in one of thier applications notes. You can call Altera and they will send them to you. Good Luck. ---- J. Scott DicksonArticle: 712
Hello, I have synthecized some combinational designs with 5 input and only 1 output with FPGA Compiler from Synopsys, but they are made with more than one CLB in Xilinx. Definitly, for a 5 to 1 combinational logic, only one CLB (XC4000) is enough. What is happening? M.R.Movahedin P.S.:a sample vhdl code follows: result: 3 XC4000 CLBs without any timing constraints ! --********************************************************************* library ieee; use ieee.std_logic_1164.all; entity ctrl2 is port(a,b:in std_logic; z:out std_logic; ctrl:in std_logic_vector(2 downto 0)); end ctrl2; architecture rtl of ctrl2 is begin z<= a and b when ctrl="000" else a or b when ctrl="100" else a nand b when ctrl="001" else a nor b when ctrl="101" else a xor b when ctrl="010" else not(a xor b)when ctrl="111" else a and not b when ctrl="011" else a or not b when ctrl="110" else '-'; end rtl; --*********************************************************************Article: 713
!! To all users interested in DSP Products !! A new html catalog is available for the user community on DSPnet. You can see processors, boards and software as well as companies with DSP related products. (Over 700 Products listed) Access is free !! URL: http://www.dspnet.com or telnet to dspnet.com -- DSPnet, Inc. Voice: (617) 642-1600 49 River Street FAX: (617) 899-4449 Waltham, MA 02154 E-mail: dspadmin@dspnet.comArticle: 714
M. Movahedin (movahed@tumlis.lis.e-technik.tu-muenchen.de) wrote:
: Hello,
: I have synthecized some combinational designs with 5 input and only 1 output
: with FPGA Compiler from Synopsys, but they are made with more than one CLB in
: Xilinx. Definitly, for a 5 to 1 combinational logic, only one CLB (XC4000) is
: enough.
: What is happening?
i
This might be a stupid question, but are you sure it's reporting CLB's
and not function generators? I'd expect to see three function generators for
a function of five inputs.
If you are in douby have a look at the XNF file, the format is pretty
straightforward.
Regards,
Aedan Coffey.
--
=================================================================
Aedan Coffey, Toucan Technology, Technology Centre, Mervue, Galway,
Ireland. Phone +353-91-757223/770007
Email: coffey@toucan.ie
Designers of Electronic Systems and ASICs.
Article: 715
PRELIMINARY ADVANCED PROGRAM
**************************************************
* *
* FIFTH GREAT LAKES SYMPOSIUM ON VLSI *
* MARCH 16 - 18, 1995, *
* BUFFALO MARRIOTT, BUFFALO, NEW YORK, USA *
**************************************************
CO-SPONSORED BY:
IEEE COMPUTER SOCIETY
TECHNICAL COMMITTEE ON VLSI
IEEE CIRCUITS AND SYSTEMS SOCIETY
STATE UNIVERSITY OF NEW YORK AT BUFFALO
IN COOPERATION WITH ACM SIGDA
GENERAL CHAIR : S. Chakravarty, University at Buffalo
PROGRAM CHAIRS: R. Sridhar & S. J. Upadhyaya, University at Buffalo
PROGRAM COMMITTEE:
Jacob A. Abraham University of Texas at Austin
Vishwani D. Agrawal AT&T Bell Laboratories
C. Anagnostopoulos Eastman Kodak Co
Jason Cong University of California at Los Angeles
Warren Debany Griffiss AFB
M.I. Elmasry University of Waterloo
Eby Friedman University of Rochester
Dwight Hill Synopsys
Rajiv Jain University of Wisconsin-Madison
Bozena Kaminska University of Montreal
S. M. Kang University of Illinois at Urbana-Champaign
John Oldfield Syracuse University
C. A. Papachristou Case Western Reserve University
C.A.T. Salama University of Toronto
Edwin Hsing-Mean Sha University of Notre Dame
Naveed Sherwani Western Michigan University
S. Verdonckt-Vandebroek Xerox Corporation
LOCAL ARRANGEMENTS: Victor Demjanenko, University at Buffalo
STEERING COMMITTEE: Naveed Sherwani, Western Michigan University
PROGRAM SCHEDULE:
MARCH 16, 1995 THURSDAY
-----------------------
------------------------------------------------------------------
8:00 - 9:00 AM Continental Breakfast
------------------------------------------------------------------
9:00 - 9:30 AM OPENING REMARKS
************************************************************************
9:30 - 10:30 AM ** KEYNOTE ADDRESS **
21ST CENTURY GIGASCALE INTEGRATION
JAMES D. MEINDL, Joseph M. Pettit Chair Professor of Microelectronics
Georgia Institute of Technology
************************************************************************
-----------------------------------------------------------------
10:30 - 11:00 AM Coffee Break
-----------------------------------------------------------------
1A: 11:00 - 12:30 PM
SESSION 1A: SYNTHESIS I
Timing-Driven Circuit Implementation
D. Karayiannis and S. Tragoudas
Southern Illinois University
Optimization Using Implicit Techniques for Industrial Designs
F. Poirot, R. Roane and G. Tarroux
Compass Design Automation, France
Optimal Technology Mapping for Single Output Cells
U. Hinsberger and R. Kolla
Universitat Wurzburg, Germany
1B: 11:00 - 12:30 PM
SESSION 1B: ANALOG VLSI
A Time-Differential Equation Approach to Analog Design Automation
M. L. Manwaring and D. J. Klein
Washington State University
A New Approach for Modeling and Optimization of Analog Systems
E. Penn and L. Schelovanov
University of New Haven
A Scalable Analog Architecture for Neural Networks with On-Chip
Learning and Refreshing
B. A. Alhalabi and M. Bayoumi
University of Southwestern Louisiana
-----------------------------------------------------------------
12:30 - 2:00 PM Lunch Break
-----------------------------------------------------------------
2A: 2:00 - 3:30 PM
SESSION 2A: PHYSICAL DESIGN I
Bus Minimization and Scheduling of Multi-Chip Systems
M. Sheliga and E. Sha
University of Notre Dame
Thumbnail Rectilinear Steiner Trees
J. L. Ganley and J. P. Cohoon
University of Virginia
A Two-Stage Simulated Annealing Methodology
J. M. Varanelli and J. P. Cohoon
University of Virginia
Wiring Space Optimization in Slicing Floorplans
J. T. Mowchenko and Y. Yang
University of Alberta
2B: 2:00 - 3:30 PM
SESSION 2B: LOW POWER DESIGN
Estimating Worst-Case Power Consumption of CMOS Circuits Modeled
as Symbolic Neural Networks
E. Macii and M. Poncino
Politecnico di Torino, Italy
Design and Analysis of a Low Power Energy-Recovery Adder
N. Tzartzanis and W. C. Athas
University of Southern California - ISI
Coding a Terminated Bus for Low Power
M. R. Stan and W. P. Burleson
University of Massachusetts
Circuit/Architecture for Low-Power High-Performance 32bit Adder
I. S. Abu-Khater, A. Bellaouar, M. I. Elmasry and R. H. Yan
University of Waterloo
-----------------------------------------------------------------
3:30 - 4:00 PM Coffee Break
-----------------------------------------------------------------
3A: 4:00 - 5:30 PM
SESSION 3A: SYNTHESIS II
Symbolic Execution of Data Paths
C. Monahan and F. Brewer
University of California, Santa Barbara
Specification and Synthesis of Bounded Indirection
K. Rath, M. E. Tuna and S. D. Johnson
Indiana University
Synthesis of SEU - Tolerant Sequential Circuits using Concurrent
Error Correction
H. Hollander, B. S. Carlson and T. D. Bennett
SUNY at Stony Brook
Scheduling Conditional Data-Flow Graphs with Resource Sharing
J. Siddhiwala and L.-F. Chao
Iowa State University
3B: 4:00 - 5:30 PM
SESSION 3B: VERIFICATION
Automated Verification of Temporal Properties Specified as State
Machines in VHDL
Y. V. Hoskote, J. A. Abraham and D. S. Fussell
University of Texas at Austin
Partitioning Transition Relations Effeciently and Automatically
Z. Zhou, X. Song, F. Corella, E. Cerny and M. Langevin
University of Montreal
Using Symbolic Rademacher-Walsh Spectral Transforms to Evaluate
the Correlation between Boolean Functions
E. Macii and M. Poncino
Politecnico di Torino, Italy
PANEL 5:45 - 7:00 PM
PANEL DISCUSSION:
Low Power vs High Speed: Can you have both?
Moderator: Eby G. Friedman, University of Rochester
Panelists: James D. Meindl, Georgia Institute of Technology
William C. Athas, University of Southern California/ISI
Tom Wik, AT\&T Bell Laboratories, Allentown, PA.
-----------------------------------------------------------------
7:30 - 9:00 PM Conference Banquet
-----------------------------------------------------------------
MARCH 17, 1995, FRIDAY
----------------------
------------------------------------------------------------------
8:00 - 9:00 AM Continental Breakfast
------------------------------------------------------------------
4A: 9:00 - 10:30 AM
SESSION 4A: PHYSICAL DESIGN II
An Efficient Building Block Layout Methodology for Compaction Placement
N. G. Bourbakis and M. Mortazavi
SUNY Binghamton
Performance Driven Standard-cell Placement Using the Genetic Algorithm
S. M. Sait, H. Youssef, K. Nassar and M. S. T. Benten
King Fahd Univ. of Petroleum & Minerals, Saudi Arabia
An Efficient Heuristic Approach on Minimizing the Number of
Feedthrough Cells in Standard Cell Placement
J.-T. Yan
National Chiao Tung University, Taiwan
Priority Driven Channel Pin Assignment
I. Peters
Humboldt-University of Berlin, Germany
4B: 9:00 - 10:30 AM
SESSION 4B: ARCHITECTURE AND DESIGN I
A Systolic Algorithm and Architecture for Image Thinning
N. Ranganathan and K. Doreswamy
University of South Florida
Analysis and Verification of Locally Clocked Circuits with the
Concurrency Workbench
G. Baulch, D. Hemmendinger and C. Traver
Union College
Automatic Rapid Prototyping of Semi-Custom VLSI Circuits using FPGAs
J.-T. Yoo, K. F. Smith and E. Brunvand
University of Utah
A Local Clocking Approach for Self-timed Datapath Designs
S.-J. Kim and R. Sridhar
SUNY at Buffalo
-----------------------------------------------------------------
10:30 - 11:00 AM Coffee Break
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5A: 11:00 - 12:30 PM
SESSION 5A: SYNTHESIS III
A Soft Computing Approach to Hardware Software Codesign
V. Catania, N. Fiorito, M. Malgeri and M. Russo
Universita di Catania, Catania
Technology Mapping Algorithms for Sequential Circuits Using LUT
Based FPGAs
S. Habib and Q. Xu
City University of New York
Modeling of Communication Protocols in VHDL
A. Assi and B. Kaminska
Ecole Polytechnique, Montreal
Using EDIF for Software Generation
M. J. van der Westhuizen, R. G. Harley and D. C. Levy
University of Natal, South Africa
5B: 11:00 - 12:30 PM
SESSION 5B: TESTING
A Protocol Extraction Strategy for Control Point Insertion in
Design for Test of Transition Signaling Circuits
H. F. Li and P. N. Lam
Concordia University, Montreal
Statistical Estimation of Delay Fault Detectabilities and Fault Grading
Z. Zhang, B. McLeod and G. E. Bridges
University of Manitoba, Winnipeg
Test Application Time Reduction for Scan Based Sequential Circuits
H. Zheng, K. K. Saluja and R. Jain
University of Wisconsin-Madison
Pseudo-Random Behavioral ATPG
A-L. Courbis and J. F. Santucci
Parc Scientifique G. Besse, France
-----------------------------------------------------------------
12:30 - 2:00 PM Luncheon
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6A: 2:00 - 3:30 PM
SESSION 6A: PHYSICAL DESIGN III
Fast Algorithm for Performance-oriented Steiner Routing
M. Borah, R. M. Owens and M. J. Irwin
Pennsylvania State University
On Locally Optimal Breaking of Nondisjoint Cyclic Vertical
Constraints in VLSI Channel Routing
A. D. Johnson
University of Toledo
OPRON: A New Approach to Planar OTC Routing
S. Danda, S. Madhwapathy, N. A. Sherwani and A. Sureka
Western Michigan University
Parallel Hierarchical Global Routing for General Cell Layout
S. Khanna, S. Gao and K. Thulasiraman
Concordia University, Montreal
6B: 2:00 - 3:30 PM
SESSION 6B: ASYNCHRONOUS CIRCUITS
Improving Self-Timed Pipeline Ring Performance Through the
Addition of Buffer Loops
H. Zhao, N. M. Sabine and E. Sha
University of Notre Dame
Scan Testing of Asynchronous Sequential Circuits
O. A. Petlin and S. B. Furber
University of Manchester, UK
A New Look at the Conditions for the Synthesis of Speed-Independent
Circuits
E. Pastor, J. Cortadella and O. Roig
Universitat Politecnica de Catalunya, Spain
-----------------------------------------------------------------
3:30 - 4:00 PM Coffee Break
-----------------------------------------------------------------
7A: 4:00 - 5:30 PM
SESSION 7A: VLSI EDUCATION
Design and Manufacture of a 2K Transistor Pwell CMOS Gate Array
in a student run factory at RIT
C. Kraaijenvanger, H. Enschede and L. Fuller
Rochester Institute of Technology
Using a Reconfigurable Field Programmable Gate Array to
Demonstrate Boundary Scan with Built in Self Test
H. J. Pottinger and C.-Y. Lin
University of Missouri - Rolla
Linking Fabrication and Parametric Testing to VLSI Design Courses
R. Pearson
Rochester Institute of Technology
A Personal Computer Based VLSI Design Curriculum
W. B. Leigh
Alfred University
7B: 4:00 - 5:30 PM
SESSION 7B: ARCHITECTURE AND DESIGN II
A Scalable Shared Buffer ATM Switch Architecture
A. Agrawal, A. Raju, S. Varadarajan and M. Bayoumi
University of Southwestern Louisiana
ATM Burst Traffic Generator
P. P. Chu
Cleveland State University
A Universal Formalization of the Effects of Threshold Voltages for
Discrete Switch-Level Circuit Models
W. Korver
University of Surrey, UK
MARCH 18, 1995 SATURDAY
-----------------------
T1: 9:00 AM - 11:00 AM
TUTORIAL 1: Issues in Multichip Modules
P.R. MUKUND, Rochester Institute of Technology
This tutorial will address the following issues pertaining to MCMs.
Electronic packaging constraints, Multichip module technology,
Choices and trade-offs, Electrical/system considerations, Thermal
considerations and Testing considerations.
T2: 9:00 AM - 11:00 AM
TUTORIAL 2: Issues in IDDQ Testing
J. H. PATEL, University of Illinois at Urbana-Champaigne &
S. Chakravarty, SUNY at Buffalo
This tutorial will address the basic concept of Iddq testing,
test generation, fault simulation and diagnosis.
-----------------------------------------------------------------
11:00 - 11:30 PM Break
-----------------------------------------------------------------
11:30 AM - 12:30 PM
Facilities Tour
Registration Table Open: 8:00 AM - 5:00 PM Thursday
8:00 AM - 5:00 PM Friday
IEEE 1995 FIFTH GREAT LAKES SYMPOSIUM ON VLSI
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Article: 716
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Article: 717In article 4vv@barnacle.iol.ie, coffey@iol.ie (Aedan Coffey) writes: > M. Movahedin (movahed@tumlis.lis.e-technik.tu-muenchen.de) wrote: > : Hello, > > : I have synthecized some combinational designs with 5 input and only 1 output > : with FPGA Compiler from Synopsys, but they are made with more than one CLB in > : Xilinx. Definitly, for a 5 to 1 combinational logic, only one CLB (XC4000) is > : enough. > : What is happening? > i > This might be a stupid question, but are you sure it's reporting CLB's > and not function generators? I'd expect to see three function generators for > a function of five inputs. YES, I am sure. definitly, for a 5 in/1 out combinational logic we need only 2 F or G function generators and one H function generator , which can be implemented in only one CLB. for more information, you can see XC4000 data books at page 2-9. Movahedin > > If you are in douby have a look at the XNF file, the format is pretty > straightforward. > > Regards, > > Aedan Coffey. > > -- > ================================================================= > Aedan Coffey, Toucan Technology, Technology Centre, Mervue, Galway, > Ireland. Phone +353-91-757223/770007 > Email: coffey@toucan.ie > Designers of Electronic Systems and ASICs.Article: 718
I've been looking for technical info about fpgas (electrical characteristics, timing, pwr diss., packaging, etc.).Does anybody can suggest me where to find the right databooks? Or at least a way to get info from manufacturers? I'd appreciate any reply. Manuel JimenezArticle: 719
In <3htibu$4vv@barnacle.iol.ie> coffey@iol.ie (Aedan Coffey) writes: >M. Movahedin (movahed@tumlis.lis.e-technik.tu-muenchen.de) wrote: >: Hello, >: I have synthecized some combinational designs with 5 input and only 1 output >: with FPGA Compiler from Synopsys, but they are made with more than one CLB in >: Xilinx. Definitly, for a 5 to 1 combinational logic, only one CLB (XC4000) is >: enough. >: What is happening? >i If your using Xilinx PPR tool and the FPGA is no full, the router may partition the design into multiple CLBs although it could fit into one. Check the report file for occupied CLBs and packed CLBs. Occupied CLBs are those containing some logic. Packed CLBs are the number of CLBs that the design could be sqeezed into. David LanzaArticle: 720
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - /
_] [_ An Independant Critique of Two New Synopsys Tools
by John Cooley, the ESNUG guy
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
[ Tuesday, Feb. 7th, Synopsys held a big press event where it announced
that they were entering into the Verilog/VHDL source level tool market.
For what it's worth, I founded and run from my sheep farm the E-mail
Synopsys Users Group (ESNUG), a completely independant grassroots user's
group with 3200 members. (So independent, in fact, that Synopsys's
lawyers tried to shut me down when I started ESNUG some 3 1/2 years
ago -- but that's another story.) I make my living as an autonomous
ASIC & FPGA design consultant helping EDA users with their tools.
- John Cooley, the ESNUG guy ]
A quickie summary of what Synopsys announced at the press event is that they're
trying to push designers out of the gate tweaking stage and into higher level
approaches. That is, they're interested moving designers into doing things
like consider the effects of test, power, and physical design characteristics
at the source level *prior* to synthesis. The two major products that are
the foundation of this new approach are "DesignSource" and "HDL Advisor."
Synopsys's DesignSource
-----------------------
Essentially, DesignSource is a block diagram schematic editor with the design
database management idea thrown in of having the ability to associate HDL
source code with synthesis scripts, Verilog/VHDL simulation test beds and
their resulting outputs in one "database". It has bells & whistles thrown in
like a hierarchy browser, a rather simple Verilog/VHDL template generator, a
block-level connectivity checker, a VHDL-specific "attribute" speadsheet
editor and the ability to fire up simulation & synthesis scripts as a front
end to VSS & Design Compiler. The Block Editor automatically propagates VHDL
information like names, types & attributes to Synopsys's VSS simulator.
In reviewing DesignSource I couldn't help but feel like I was some sort of
art critic at a cocktail party who was given the challenge to identify where
every part of a certain new montage came from. That is, with DesignSource, I
wasn't looking at anything new but something more like a potpourri of ideas
and parts of other tools that had been kicking around for some time in the
EDA community. It just sang out Cadence Composer!, Mentor Design Architect!,
ViewLogic ViewDraw!, Summit Design!, Escalade!, parts of Intergraph's tool
offerings! and even the old Racal-Redac's Visula schematic editor!
The Synopsys Verilog/VHDL template generator seemed rather primitive at best.
Based on what was entered in the graphical Block Editor, for VHDL it threw
down a simple piece of empty boiler plate ENTITY/ARCHITECTURE; for Verilog it
spits out an empty module and its associated input/output statements -- the
user is then left on his own with the "vi" editor to fill in these empty
pieces of boiler plate with his sophisticated codings of state machines, data
paths, controllers, etc. (My question is: "If our user can't create this
initial no-brainer type of boiler plate in ten minutes on his own, how can he
be trusted with coding the rest of the design?") For designers interested
in something a little more involved in writing VHDL, I'd suggest you take a
look at Summit Design's "Insight" -- it's best described as interacting with
a living, breathing VHDL Language Reference Manual -- a hog wild VHDL syntax
thingy. For Verilog, Cadence reports having a similar language sensitive
editor in its Verilog-XL Design Environment with an additional waveform
viewer and Verilog debugger thrown in. For the super-cheap user you can
even look into the free GNU-EMACS editor with Verilog/VHDL specific settings.
The carefully-manage-all-your-ASIC-design's-associated-files concept is as
old as UNIX software is. For many a year, ASIC designers have been using
*free* UNIX utilities like SCCS and RCS to keep track of various revisions
of their source Verilog/VHDL files, their synthesis scripts and the changes
in their Verilog/VHDL testbenches for their designs. (SCCS and RCS design
database management is characterized by designers checking in and checking
out various associated design files. Synopsys's DesignSource doesn't have
check in/check out; it just associates various design files together.)
I freely admit that block editors in themselves, regardless of who's selling
them, just don't impress me. I personally just don't see beaucoup value-add
here for what little they do and how much they cost.
A quick comparison of pricing on UNIX tools that are somehow similar:
Tool Price Comments
------------ ------- ---------------------------------------
GNU EMACS, "vi" & No user hand holding. Clever people
SCCS or RCS *free* save lots $$$ here; idiots lose $$$ here.
Mentor Graphics Only works with Mentor specific VHDL
Design Architect $9,900 and no Verilog (yet)
Cadence Verilog-XL Waveform viewer, results analyzer,
Design Environment $7,500 language sensitive editor & debugger
Cadence Leapfrog VHDL Same as above. "Free" when you purchase
Design Environment "free" their Leapfrog VHDL at $20,000.
Cadence Composer $14,500 Overpriced schematic block editing w/dbase
Concept $12,500 mngmnt. -- very similar to DesignSource
Synopsys Overpriced (like Cadence Composer & Concept)
DesignSource $17,000 for what it does. Should be $4K to $7K.
For those EDA users interested in shelling out $12,500 to $17,000 per engineer
at your site for cheesy Verilog/VHDL templates and revision control software,
please immediately phone me, John Cooley, at (508) 429-4357 and I'll easily
beat their price by 50%! (I really *am* an independent ASIC & FPGA design
consultant, you know!) Mind you, it is a REAL and BIG problem for designers
if they're not up to working with file management & revision control -- then
I'd STRONGLY recommend getting something like Synopsys's DesignSource as a
fairly light-weight full-source control environment because you'll lose
significant time & energy & money & sleep without it... but I'd still haggle
like crazy with the salesman to not pay $17,000 for it! :^)
(I know I'll catch hell for this but it's true!)
Synopsys's HDL Advisor
----------------------
Inasmuch as I reserve the right to publicaly yawn at DesignSource because it
seemed to be an overpriced Cadence Composer copycat product for Synopsys -- I
also reserve the right to publicaly applaud Synopsys for creating a unique,
new, interesting & useful type of tool with its HDL Advisor. It's HOT!
One of the early questions that I had when first taking an in-depth look
at HDL Advisor was: "Is this just warmed over, productized Source-To-Gates?"
(Source-To-Gates was a feature that offered Synopsys customers a very crude
correlation between a group of gates from synthesis and where in the source
Verilog/VHDL it sort of thought it came from. Source-To-Gates didn't
work very well because synthesis would add & remove gates all the time to
fit some timing or area constraint.) HDL Advisor turned out to much more
of a true analysis tool focused on the *before* synthesis problem of coding
one's Verilog/VHDL design. Here's what I saw in Synopsys's HDL Advisor:
* - HDL Browser:
- the "home" window that lets you examine your source Verilog/VHDL and how
various specific lines of source code relates to graphics/reports you
generate in other windows. The Hot Cursor & Selection Inspector (described
later) play a significant role here, too.
At the pre-synthesis point you can keep track of timing via the number of
logic levels your source Verilog/VHDL would create, a rough area estimate
under the component count heading and your source Verilog/VHDL related
connectivity issues like fan-in and fan-out. Note: it's *before* synthesis.
At the post-synthesis point you get to keep track of area, power, timing
violations in relation to the constraints you gave the design, and
connectivity issues like fan-in, fan-out & capacitance.
* - Histogram & Profiler:
- two graphics packages that display the pre- and post- synthesis data
decribed above in an intelligent & useful manner for the ASIC designer.
Let's say I'm interested in timing issues for my pre-synthesis Verilog
source code. (Since there's no real timing info at the pre-synthesis
phase, the next best thing that correlates to timing is the number of
logic levels my piece of Verilog would have if mapped to gates.) I'd
fire up the Histogram to show me the distribution of pre-synthesis
logic levels in my design. Click on a specific Histogram bin and, voila!,
the list of specific design data points in that bin are listed with the HDL
Browser showing the associated source Verilog code highlighted. (Profiler
works in a similar manner but as a single verticle bar broken into
segments showing percentages. It's useful, for example, for tracking how
much area various parts of your source Verilog/VHDL results in.)
* - Path Browser & Logic Inspector:
Once I've identified an interesting issue with my Verilog source (like
losts of high fan-out points discovered from looking at the Histogram
for fan-out) I can chase these problem children through my Verilog
*source* by using the Path Browser which explores pure connectivity. If
I was curious down to the gate level, I fire up Logic Inspector to
see a Boolean gate level representation of what I'm interested in. (All
the time, every point I touch in these explorations is cross referenced
and highlighted in the *source* in HDL Browser.) Also, If I'm interested
in chasing something like post-synthesis capacitance, I can use Path
Browser & Logic Inspector in a similar manner.
* - Hot Cursor & Selection Inspector:
These two properties run throughout all of the windows in HDL Advisor.
Essentially, a hot cursor tells the user quickie information without
having to "click" on anything. Just wander the cursor over something
and it'll tell you a useful snippet like a module name in a particular
part displayed in Profiler or the Boolean expression at a specific point
seen in Logic Inspector. Selection Inspector is a follow-up window
that spews out as much info as is known about a point if it's "clicked"
by the cursor -- stuff like: name, fan-in, fan-out, logic levels, area,
hierarchy path, timing slack, power -- whatever it knows at the time!
With its focus on getting feedback to the designer while he's writing his
Verilog/VHDL source code, HDL Advisor helps circumvent the dreaded Synthesis
Iteration Hell. That is, there are a lot of ASIC design teams that first
write their Verilog/VHDL, spend months verifying its functionality with reams
of regressions and then take this golden source code to synthesis. If the
golden code runs into problems designers will literally spend weeks/months
chasing down all sorts of settings and switches for Design Compiler to avoid
having to change their errant source Verilog/VHDL. HDL Advisor promotes
better coding styles for synthesis *while* the source code is being written.
A few of the old time Synopsys customer may say: "Sounds like a good tool
for beginners. I don't need it because I already know what does & doesn't
get you in trouble for Synopsys." -- but they're missing a crucial point.
It's one thing to know that "nets with high fan-outs are bad news"; it's
another to know exactly which nets fit in that category in *your* specific
design before synthesizing. That is, HDL Advisor lets you ask meaningful
questions on large & complex hunks of Verilog/VHDL source code like:
- where are the longest paths? what modules do they go through?
- what are the fan-ins and fan-outs at this point? where do they lead?
- how does the timing slack or capacitance relate back to the source?
- what's the boolean equation here in the design?
Instead of burning up brain cells trying to figure out how your code (or
worst yet, some source code you "inherited") will be digested by the
Synthesis Monster, this tool lets you quickly know where the hot spots are
and where hot spots aren't in your code.
I *strongly* recommend checking out Synopsys's HDL Advisor because it lets
you check out your design even before simulate (much less synthesize) it!
Summary
-------
DesignSource is a Synopsys version of Cadence's Composer -- neither product
I'd personally buy with their hefty asking prices ($17K & $14K) for what
little these block-schematic-editors-with-revision-control-thrown-in tools
do. You can get free rev control using UNIX's SCCS/RCS and the wimpy coding
templates created by the block schematic editors can be made by hand in
ten minutes with "vi". Mind you, if you're not disciplined enough to handle
file management & revision control on your own, IMMEDIATELY BUY DesignSource
because you'll lose significant time & energy & money & sleep without it.
On the other hand, Synopsys HDL Advisor is definitely an interesting new type
of tool altogether. I'd recommend giving it a look-see if you're a newbie
designer or an old pro. HDL Advisor lets you quickly know where the hot spots
are and where hot spots aren't in your Verilog/VHDL source code -- even
before you simulate (much less synthesize) the design! Check it out!
Overall, I think most Synopsys customers enjoyed the big press announcement
get together because it told them through acts (not lip service) that
Synopsys really is serious about getting open customer input in front of
the trade press, industry analysts and financial people. Although there
weren't hundreds of customers there cheering & shouting "Encore! Bravissimo!"
when the event was done, I do think they *liked* the idea of being invited
to the *big* press announcements.
- John Cooley
part-time EDA Consumer Advocate
full-time contract ASIC & FPGA designer
P.S. I'd like to hear from readers what they think about getting in-depth
critical reviews like this. They're a lot of work. Are they worth it?
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3196 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 721In article <3hfv31$8p@seralph9.essex.ac.uk> ierof@csc2.essex.ac.uk (Ieromnimon F) writes: >From: ierof@csc2.essex.ac.uk (Ieromnimon F) >Subject: Re: VERILOG >Date: 10 Feb 1995 15:00:48 GMT >In article <3h5s7sINNc3r@salmon.wv.tek.com> weedk@salmon.wv.tek.com (Kirk A Weedman) writes: >>Anyone know where I can get a Verilog description >>for SCSI design? >> >> Kirk weedk@pogo.wv.tek.com >Mee too! Any primer on Verilog models of SCSI protocols/components/the lot would >be received with gratitude! >Frank Ieromnimon, >PACE Project, >dept. of Computer Science, >University of Essex. Try talking to the guys at NCR in colorado springs ,CO, they have the 53C80 etc implementable as a standard cell, so my guess would be they have some version of verilog / VHDL perhaps available for it Wassail, KenArticle: 722
cking@accutron.ie writes :-
>Hi,
> I'm currently working on the design of a video RAMDAC
>evaluation/demonstration board, and would like some comments
>and/or help on an idea I have. The board is like this:
etc. etc...
> 1. The FPGA has 5000 internal gates.
> 2. It can run at 250Mhz internaly
^^^^^^
250MHz ! Are you sure about this, sounds like a toggle frequency to me, in which case
would I not expect your design to run at this speed.
Please correct me if I am wrong and let me know who is making such a device.
Cheers,
T.H. (trev@wg.icl.co.uk)
Article: 723Hello, I would like to know something diffrent among them? I was always cunfused by them all. In my previous impression, they are: PAL: programmable AND, fixed OR PLD: programmable AND, programmable OR PLA: ???????????? AND, ???????????? OR GAL=PLD ?? Please correct the above, Thanks in advance! JasonArticle: 724
In article <3i02ch$d85@msunews.cl.msu.edu> jimenez2@oscar.egr.msu.edu (Manuel Alejandro Jimenez-Cede) writes: >I've been looking for technical info about >fpgas (electrical characteristics, timing, pwr diss., packaging, etc.).Does anybody can suggest me where to find the right databooks? >Or at least a way to get info from manufacturers? > Yeah, CALL them. Go to your University library and look in any of the technical magazines: EDN, Electronic Design, Computer Design, EE Times, ASIC & EDA, etc. You'll find dozens of addresses and phone numbers for Xilinx, Altera, Atmel, AT&T, Cypress, Quicklogic, etc. Hope this helps, Mircea >I'd appreciate any reply. > >Manuel Jimenez > -- Mircea R. Stan | "Without immortality the whole world would UMass, ECE Dept. | be nonsense, all of creation an absurdity." Amherst, MA 01003 | Karl F. Gauss
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