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Announcement / First Call for Contributions
GI/ITG-Workshop on
"V L S I A r c h i t e c t u r e s"
(Architekturen für hochintegrierte Schaltungen)
July 17 - July 18, 1995
Vienna, AUSTRIA
Organizer: Institut für Technische Informatik, TU Wien
GI/ITG Fachgruppe "Architekturen für hochintegrierte Schaltkreise"
Architectures for data processing and data transfer are highly
influenced by the possibilities of VLSI technology. The fourth
workshop of this series will discuss hot topics in the area of very
large scale integration and its effect on processor and system
architecture with special emphasis on "Architectures for the
Information Highway"
The workshop includes an open discussion section on
"Architectures for the Information Highway"
The GI/ITG SIG on VLSI invites submissions on the following topics:
* architectures for the Information Highway
(short discussion statements)
* telecommunication
(integrating telecommunication and computers; special
architectures for telecommunication; ATMs, switches, and
hardware protocols)
* architectures for heterogeneous systems
(I/O nodes, computational nodes, communications nodes; scalar,
heterogeneous multicomputers)
* reconfigurable processor arrays
(reconfigurable bus systems, polymorphous processor arrays)
* microprocessor architectures
(beyond RISC, super scalar, VLIW, transport-triggered
architectures, novel memory architectures, reducing memory
latency, improving code density)
* FPGA-based processors
(reconfigurable instruction set (extensions), application-specific
co-processors, architecture simulation and prototyping)
* asynchronous systems
(self-timed, delay-independent systems)
* neural computing
(novel concepts for associative memories and computers;
artificial neural networks and their hardware implementation)
Deadlines:
Extended Abstract April 24, 1995
Notification of Acceptance May 29, 1995
Final Papers June 26, 1995
Further information is available by sending e-mail to:
vlsi-conf@vlsivie.tuwien.ac.at
or via WWW at
http://www.vlsivie.tuwien.ac.at/vlsi-conf.html
-------------------------------------------------------
Send contributions to:
Herbert Grünbacher
Institut für Technische Informatik
Technische Universität Wien
Treitlstraße 3/182-2
A-1040 Vienna
Austria
Tel +43 (1) 588 01-8150
Fax +43 (1) 586 96 97
eMail gruenbacher@vlsivie.tuwien.ac.at
-------------------------------------------------------
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Article: 676Milan Vasilko (mvasilko@bournemouth.ac.uk) wrote: : Hello ! : I wonder if anyone has any information about: : - commercially available "on-fly" reprogrammable devices, i.e. devices : which can be programmed during their operation (or better part of the : chip can be reprogrammed while another parts are still operational). : I am interested in any type of device FPGA, PLD etc. : (I am only aware of AT6000 family from Atmel) AT&T's ORCA FPGAs do allow this. The reprogrammability is essentially unconstrained, except for a few I/O pads. The 40,000 gates FPGA, ATT2C40 gives you a fair amount of user gate capacity to play with. The restriction on a few pads is also not a big problem, since there are about 360 potential user I/Os depending on the package. I think, you can call 1-800-EASY-FPGA (with in USA?) for information. : - any research activities on-going in this area I would be interested to know about the candidate applications for this feature. Regards, Satwant.Article: 677
> >Hi, > > I was wondering how people are dealing with the following situation or >similar situations. > > I am using Viewlogic's Prosynthesis to target an XC4000 Xilinx FPGA >from a VHDL-based design. The VHDL has been written, the logic gates >have been synthesized, and the resulting logic has been simulated. >The simulation looks good, and I am now about to use the XACT 5.0 tools >to go through the PPR process. > > However, since the synthesis tools, only use basic parts of the >XC4000 library (i.e. AND, NAND, NOR, OR gates and FDCE (flip flops), etc), >the FPGA targetting appears extremely inefficient. I created a >"top-level" which consisted of hierarchical elements which totalled about >4000 "cells" (gates and flip flops). I used the "estimate" option on >the PPR, and I targeted a 4013 FPGA. The estimate was that >95% of the function generators were needed to be used. > > My understanding is that the only way around this poor use of resources >is to instantiate the library parts in the VHDL code. That is, >XC4000 adders, multiplexers, etc. that would map to the FPGA more >efficently could be explicitly used. This seems to >take a away from the whole point of the VHDL design in the first place! >I would have just used a schematic capture approach instead! > > Please tell me if there are any solutions to this dilemma. Is this >inefficient use of FPGA resources just a consequence of a high-level >design approach (i.e. VHDL) that must be endured? > >Thanks, > > Ed > I'd say that you've discovered the cost of designing using a high level input. Using text based entry (ie. VHDL) buys you portability (provided the structural definitions remain generic...hence the basic set of gate functions), a shortened design cycle and self documentation. These advantages, however carry the cost of lower performance, less efficient use of the hardware resources and more expensive tools. The trade-off between the ease of design using the high level tools and the control over the design afforded by 'handcrafting' the design is analogous to the differences between high level languages and assembly coding seen in the software world. As the hardware becomes faster, bigger and cheaper, it becomes more attractive to accept the loss in efficiency in order to get the product to market faster. The bottom line is there is no free lunch. Since you seem to want both, about the best you can do is to let the synthesis do the less critical portions of the design and handcraft the parts you need to squeeze more out of. The handcrafting can be in the form of careful detailed structural HDL coding as you suggest (can be done by instantiating a macro), or in the form of schematic entry. In very critical applications (size or performance) you may need to resort to an entirely handcrafted design. Some may argue that the synthesis could produce a higher level solution to take advantage of a particular architecture. The problem here is that you lose portability of the code (which in reality is not that horrible, since most engineers have a part in mind before they begin the design) and more importantly the synthesis tool becomes unique to the target architecture. Those tools are expensive enough without having a unique tool for each device. Finally, the coarse granuarity and limited routing in the FPGA make a poor target for synthesis. Increasing complexity of the basic synthesis elements makes the synthesis harder to do, and can result in a less efficient design (the FPGA tools do a decent job mapping gate level logic to the cells, but do a poor job partitioning larger functions). As with software, I expect we will see better optimizers for 'gateware' in the future. These will help to close, but will not eliminate the performance and efficiency gap between automated and handcrafted designs. In the mean time, let the tools do what they can and tailor the design where you need to. After all, if the tools did everything, what would you, the engineer do? -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 email randraka@ids.net The Andraka Consulting Group is a digital hardware design firm specializing in obtaining maximum performance from FPGAs. Services include complete design, development, simulation and integration of these devices and the surrounding circuits. We also evaluate, troubleshoot and improve existing FPGA and board level designs. Call or write for a brochure.Article: 678
Anyone know of an ftp site where I can get the BLIF language spec? As well, is there a BLIF to VHDL conversion utility available?Article: 679
#******************************************************************#
CALL FOR PAPERS, TUTORIALS, & WORKSHOPS
(http://asic.union.edu for a postscript version)
>***********************<
> DEADLINE MARCH 3, 1995<
>***********************<
# ##### ### ##### ### ##### #######
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Eighth Annual
APPLICATION SPECIFIC INTEGRATED CIRCUIT
Conference and Exhibit 1995
"Implementing the Information Superhighway
with Emerging Technologies"
Stouffer Renaissance Hotel
Austin, Texas
September 18-22
CALL FOR PAPERS, TUTORIALS, & WORKSHOPS
Technical Papers, Tutorials, and Workshop Proposals are solicited in
the following areas:
ASIC Applications: Wireless Communications, PC/WS and Peripherals,
Multimedia, Networking, Image Processing, Data
Communications, Storage Technologies, Graphics,
Digital Signal Processing
Technologies: Digital, Analog, Mixed Signal, CMOS, BiCMOS, ECL,
GaAs
CAD Tools: Design Capture, Layout, Test, Synthesis,
Modeling, Simulation
Architectures: PLDs, Gate Arrays, Cell Based ICs, Full Custom ICs
Evolving Research: Research in Methodologies, Tools, Technologies &
Architectures
Design Methodologies: System Design, Top-down, Graphical, HDLs
Manufacturing: Process, Testability, Packaging
Workshops: Four or eight hour technical workshops covering ASIC design
knowledge and skills. Proposals to form these workshops for either
introductory or advanced levels are invited. ASIC industry as well as
universities are encouraged to submit proposals. Contact the Workshop
Chair (see end of this message for address/phone/fax/email).
______________________________________________________________________
INSTRUCTIONS TO AUTHORS
Authors of papers, tutorials, and workshops are asked to submit 15
copies of a review package that consists of a 500 word summary and
a title page. The title page should include the technical area from
above, the title, a 50 word abstract, the authors names as well as
an indication of the primary contact author with a COMPLETE mailing
address, telephone number and TELEX/FAX/Email. The summary should
clearly state: 1) title of the paper; 2) the purpose of the work;
3) the major contributions to the art; and 4) the specific results
and their significance.
IMPORTANT DATES
Summaries and Proposals due: March 3, 1995
Notification of Acceptance: April 14, 1995
Final Camera Ready Manuscript due: June 2, 1995
SEND REVIEW PACKAGE TO
Lynne M. Engelbrecht
ASIC Conference Coordinator
1806 Lyell Avenue
Rochester, NY 14606
Phone: (716) 254-2350
Fax: (716) 254-2237
CONFERENCE INFORMATION
http://asic.union.edu
Proceedings, and the Advance Program
Airline Discounts, Exhibits, Technical Sessions,
Schedule, Registration, Hotel Sites,
ASIC'94 Chair's Report and Photos and ASIC '94 Information
CONFERENCE CHAIR TECHNICAL CHAIR WORKSHOP CHAIR
William A. Cook Richard A. Hull P. R. Mukund
Eastman Kodak Co. Xerox Corp. RIT
Rochester, NY 14650 Webster, NY 14580 Rochester, NY 14623
Phone: (716) 477-5119 Phone: (716) 422-0281 Phone: (716) 475-2174
Fax: (716) 477-4947 Fax: (716) 422-9237 Fax: (716) 475-5845
bcook@kodak.com rah.wbst102a@xerox.com mukund@cs.rit.edu
EXHIBIT CO-CHAIRS
Kerry Van Iseghem Kenneth W. Hsu
LSI Logic Corporation RIT
Victor, NY 14564 Rochester, NY 14623
Phone: (716) 223-8820 Phone: (716) 475-2655
Fax: (716) 223-8822 Fax: (716) 475-5041
kerryv@lsil.com kwheec@ritvax.isc.rit.edu
Sponsored by the IEEE Rochester Section
in cooperation with the Solid State Circuits Council
and the IEEE Austin Section
#******************************************************************#
Article: 680In article <sugiura-2801951543420001@tcp-ip.or.jp>, sugiura@tcp-ip.or.jp (Akinori Sugiura) writes: > The Cypress Warp2 VHDL compiler supports 22v10 devices. The entity code for > 24-pin devices exist, however there is no entity code for 28-pin devices. > > - Does anybody know if it is possible to use 28-pin 22v10 in Warp2? > - Does anybody have any idea for fitting designs into 28-pin 22v10 in Warp2? > > I would appreciate any help. Disclaimer: I have installed, but not yet used the Warp2. I examined the device data file, and found some data on the 22v10. In appears that the 24pin dip and 28pin plcc data is there. The 24pin data appears to be associated with a ".D" code. The 28 pin with a ".J" code. One might infer that the ".D" is the default. You might try appending a ".J" to the entity code. This is pure guesswork on my part. > -- > Akinori Sugiura > Email: sugiura@tcp-ip.or.jp Email bounced, hence this followup. Gerry Belanger, Sr Engr, Cognitronics Corp gerryb@cogn.comArticle: 681
In Article <3gomon$691@jazzmin.vnet.net> devb@jazzmin.vnet.net (David Van den Bout) writes: >In article <22093.9502011123@bmth.ac.uk>, >Milan Vasilko <mvasilko@bournemouth.ac.uk> wrote: >->- commercially available "on-fly" reprogrammable devices, i.e. devices >-> which can be programmed during their operation (or better part of the >-> chip can be reprogrammed while another parts are still operational). >-> I am interested in any type of device FPGA, PLD etc. >The Altera FLEXlogic 8160 has this feature in a more limited sense than >the Atmel part: half of the 8160 can be reprogrammed while the other >half is running. National Semiconductor has their CLAy 31 and CLAy 10 devices which are similar to the Atmel part. Both of these share a lineage from the Concurrent Logic design, so they are quite similar. I believe the partial reconfigurability of this part is protected by a patent, so I don't think you'll see other FPGA's with that property. The other RAM based parts like the Xilinx can be reconfigured, but will not hold the current state during a reprogramming cycle. One group I am aware of is using Xilinx and an external state memory to get around the problem. There is research going on into applications for reconfigurable logic. However, in order to avoid a possible conflict of interest on my part, I suggest you look into the proceedings of the various FPGA conferences. FCCM comes to mind (IEEE symposium on FPGAs for Custom Computing Machines, this year in Napa, CA in April), or you may want to attend the International Workshop on Field Programmable Logic and Applications which will be held in the UK (Oxford, beginning 29 August). -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 email randraka@ids.net The Andraka Consulting Group is a digital hardware design firm specializing in obtaining the maximum performance from FPGAs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate, troubleshoot and improve existing designs. Please call or write for a brochure. **** We have Atmel, NSC, and Xilinx FPGA design experience ****Article: 682
It's on ic.berkeley.edu's /pub/sis.tar.gz, a tool inside SIS-1.2 called blif2vst just what you want. Zhang YangArticle: 683
In article <sugiura-2801951543420001@tcp-ip.or.jp>, sugiura@tcp-ip.or.jp (Akinori Sugiura) writes: > The Cypress Warp2 VHDL compiler supports 22v10 devices. The entity code for > 24-pin devices exist, however there is no entity code for 28-pin devices. > Depending on the programmer you are using, it may not matter. Many programmers can convert the 24 pin test vectors to 28 pin (the fusemap is identical). T.H.Article: 684
I am looking for feedback from others who may have used the Altera
(formerly Intel) Flex 8160 FPGA, with or without success. I am debugging
a board containing a chain of three of the 8160 devices (labeled Intel
SBFX8160-10), and a single KUFX780-10. I am using PENGN to program the
chips, which reports success witht the -v (verify) option. I can even
read back the JEDEC fuse maps from the programmed chips, and successfully
compare with the source files; in other words, the chips program OK.
Each chip gets two clocks, 20 MHz and 60 MHz (for the 8160, both clocks go
to both halves of the device; i.e., four clock pins total per chip). If
I download a simple design with a toggling flip-flop connected to an output
pin, clocked with the 60 MHz clock, I get the following results:
KUFX780: as expected, the output is a 30 MHz square wave.
SBFX8160: all three chips, identically, output a 10 MHz square wave.
(appear to be using the 20 MHz clock)
If I change the PDS to use the 20 MHz clock, I still get 10 MHz out.
If I stop using the MPIN construct, and individually assign in turn
each of the four clock inputs, I still get 10 MHz out.
This problem surfaced in a more complex design, when I determined that
some of the flip-flops seemed to be using the wrong clock, but others
were OK. I was actually able to change the pattern of this problem
simply by reassigning the pin location of certain buried nodes.
By the way, the clock input at the pin is definitely 60 MHz.
I am just waiting for this to turn out to be something stupid, but I
am at a loss as to what that might be. Altera has not come up with any
solutions.
These devices, purchased from Intel, were some of the first units shipped
last year. Has anyone successfully used chips with these same markings?
Thanks in advance for any ideas.
--Scott Bierly (bierly@era.com)
--
+-------------------------------+-------------------------------------+
| Scott Bierly | Engineering Research Associates |
| email: bierly@era.com | Vienna, VA |
+-------------------------------+-------------------------------------+
Article: 685Anyone know where I can get a Verilog description for SCSI design? Kirk weedk@pogo.wv.tek.comArticle: 686
Excuse me for interrupting if I am in the wrong newsgroup, but I thought fpga might have something to do with the International Function Point Users Group. Since it does not appear to be such a group, could anybody please direct me to a newsgroup that discusses it? Thanks, DaveArticle: 687
list help quitArticle: 688
octtools is part of ptolemy. Try ftp.ptolemy.berkeley.edu. Yes, ptolemy has been ported to Linux!Article: 689
I have to fit 4 universal synchronous receiver/transmetter such as com2601 controler by state machine and 4 ports ram: ACT3 is big enough.... Regard's DanielArticle: 690
I would like to know if there is a executable to convert
the waveform file (*.hst) created by PLDshell Plus/PLDasm
(after simulation) to PS (postscript) format. I did find a
hst2ps.C code in one of the sites, but its a buggy version.
Is there any other utility which can do this for me??
Thanks
Shakuntala
------------------------ ------------------------
e-mail: sanjanai@carlserver.carl.ua.edu
: sanjanai@buster.eng.ua.edu
------------------------ ------------------------
Article: 691Does anyone know of an inexpensive method for accessing the boundary scan capabilities of an FPGA? I have found several devices to do this, but so far the boundary scan capabilities have all been add ons to extremely expensive test equipment. All we need is some kind of device (PC card and cable?) to interface with the IEEE1149.1 standard TAP, and some software to drive it. Thanks Dan Crouse -- Daniel R Crouse II crouse@eng.buffalo.edu "Though we live in trying times- We're the ones who have to try" Neil PeartArticle: 692
Argh, mail bounced! Re: 28-pin numbers Fake it. Do the pin mappings on your own from 28 to 24, and just use the 24-pin package numbers instead. The JEDEC files are the same, so for the 22v10 device it does not care what package it is in. If and when Warp2 does ever support the 28-pin package of your choice, then you can switch the design file pins. Cheers, --R. Vireday Formerly of the Intel PLD Business UnitArticle: 693
Milan Vasilko (mvasilko@bournemouth.ac.uk) wrote:
: Hello !
G'Day
: I wonder if anyone has any information about:
: - commercially available "on-fly" reprogrammable devices, i.e. devices
: - any research activities on-going in this area
Altera have some in the pipeline. Talk to your local rep about the 9000
series and other ICR (In Circit Reconfigurable) parts.
--
_--_|\ |
/ \ Ian Mackereth | His .sig bore this strange device:
\_.--._/ |
v | "Excelsior!"
Article: 694I have to implement 4 usrt(universal synchronous RX/TX) in act2 (actel) will it fit? regard's danielArticle: 695
>Does anyone know of an inexpensive method for accessing the boundary scan >capabilities of an FPGA? I have found several devices to do this, but so >far the boundary scan capabilities have all been add ons to extremely >expensive test equipment. All we need is some kind of device (PC card and >cable?) to interface with the IEEE1149.1 standard TAP, and some software to >drive it. > Texas Instruments used to sell a card that plugged into a PC. They had PC based software for manipulating the scan strings as well. good luck, Charles F. Shelor SHELOR ENGINEERING VHDL Training, Consulting, and models 3308 Hollow Creek Rd (817) 467-9367 Arlington, TX 76017-5346 cfshelor@acm.orgArticle: 696
R E G I S T R A T I O N
C A L L F O R P A R T I C I P A T I O N
02/01/95
IEEE Workshop on FPGAs for Custom Computing Machines
April 19-21, 1995
Marriott Inn at Napa Valley, Napa, California
====================================================================
02/01/95
This symposium is sponsored by the IEEE Computer Society and the
Technical Committee on Computer Architecture. A proceedings will be
published (after the workshop) by the IEEE Computer Society and should
be available by mid-summer. Past FCCM proceedings are available from
the IEEE Computer Society, Computer Society Press.
A limited number of copies will also be available for sale at FCCM 95.
CoChairs: Peter Athanas Ken Pocek
Virginia Tech Intel
Dept. of Elec. Engineering Mail Stop RN6-18
340 Whittemore Hall 2200 Mission College Blvd.
Blacksburg, Virginia Santa Clara, CA 95052
703-231-7010 408-765-6705
703-231-3362 (fax) 408-765-5165 (fax)
athanas@vt.edu kpocek@sc.intel.com
ORGANIZING COMMITTEE:
Jeffrey Arnold, SRC
Duncan Buell, SRC
Pak Chan, UC Santa Cruz
Apostolos Dollas, Technical Univ. of Crete
Frederick Furtek, Atmel
Brad Hutchings, Brigham Young Univ.
Tom Kean, Xilinx
Wayne Luk, Imperial College of London
Further information can be obtained from either of the co-chairs.
Registrations including payment should be submitted to Ken Pocek.
Room accommodations should be made directly with the hotel.
=====================================================================
02/1/95
REGISTRATION AND HOTEL INFORMATION
IEEE Symposium on FPGAs for Custom Computing Machines, April 19-21, 1995
Marriott at Napa Valley, Napa, California
3425 Solano, Napa, California 94558
707-253-7433, 707-258-1320 (fax)
Accommodations should be made directly with the hotel.
PLEASE TYPE OR PRINT
Name ___________________________________________________________
Address ___________________________________________________________
___________________________________________________________
___________________________________________________________
Email ___________________________________________________________
Phone ____________________________ Fax ________________________
Active IEEE Member Number (Y/N)? ___ Member No: _________________
Registration Fee (see table below): $_____________________________
Credit Card Payers:
Card Holder's Name _____________________________________________
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Signature _____________________________________________
(Credit card payment cannot be made by email--a signature is required)
Student registrants:
I certify that I am a registered student at _______________________
(signed) __________________________________________________________
University address:________________________________________________
The registration fee schedule is as follows. The deadline for
preregistration is March 24, 1995. Regular (nonstudent)
registration includes a copy of the proceedings and lunch on
Wednesday and Thursday, April 19 and 20.
Preregistration Onsite Registration
IEEE Members 190 230
Non-Members 250 300
Students 90 110
All rates are U. S. dollars. Checks must be drawn on a U.S. bank
and should be made payable to IEEE FCCM Symposium. Checks and
registration forms should be mailed to IEEE FCCM Symposium,
c/o Ken Pocek, Intel, Mailstop RN6-18, 2200 Mission College Blvd.,
Santa Clara, CA 95052 (USA).
Article: 697Kirk A Weedman (weedk@salmon.wv.tek.com) wrote: : Anyone know where I can get a Verilog description : for SCSI design? Not on this newsgroup! -- Paul Menchini | email: mench@mench.com | "Se tu sarai solo, Menchini & Associates | voice: 919-990-9506 | tu sarai tutto tuo." 2 Davis Dr./POB 13036 | pager: 800-306-8494 | -- Leonardo Da Vinci RTP, NC 27709-3036 | fax: 919-990-9507 |Article: 698
Hi folks,
As a part of a larger project, I have developed a C++ to netlist
compiler. The main goal is to be able to emulate the generated
hardware by compiling the source code with a regular C++ compiler.
The targeted hardware is mainly FPGA chips.
I actually compiled code all the way into Xilinx chips. And they
run. I think this compiler might be of some interest to other
researchers, so I decided to make it freely available under a GPL type
of licensing.
At the current time, the compiler:
- is written in C++. Can be compiled by g++ 2.6.3.
- needs the LEDA 3.1 library (available by anonymous ftp).
- will directly generate ViewLogic WIR files and the associated
symbols. It should be easy to add some code to have it generate
netlists of different format.
The target (FPGA) architecture is described directly in the source
code, preferably in an included file. Thus it should be extremely easy
to generate netlists for different FPGA architectures. A partial
description of the XC4000 family is provided in the sources.
This is still beta quality code. The documentation is very sparse.
How to get it:
ftp://lslsun5.epfl.ch/pub/nlc-0.6.tar.gz
then look at the README file for terse explanations on how to build...
I'll also put a compiled binary version for sparc, Solaris 2.3 (sorry,
this is all I have access to...)
There is a Majordomo mailing list for discussion about nlc. To be
added to the list, send a message containing the line
subscribe nlc
to majordomo@lslsun.epfl.ch. The subject is irrelevant.
If some folk manage to compile nlc for some other platform, they can upload
the binary on lslsun5 and tell the list...
Take care,
Christian Iseli
--
Christian Iseli
LSL-DI-EPFL
Lausanne, Switzerland
Article: 699
In article <3hb3u5INNhdi@sun004.cpdsc.COM>, cshelor@cpdsc.com (Charles Shelor) writes:
> Texas Instruments used to sell a card that plugged into a PC. They had
> PC based software for manipulating the scan strings as well.
>
TI calls the product "ASSET.
>From the OEM price book, the card appears to cost abour $500,
and the software, $3500.
Ouch!
Gerry Belanger
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