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In article <3fd7g5$jm1@news.tv.tek.com> bobe@soul.tv.tek.com (Bob Elkind) writes: #To be more clear on the subject, the ASIC vendor does *not* want simulation #files. The ASIC vendor wants fault test patterns to verify that the devices #were built correctly. # #Simulation is what the designer does in the privacy of his/her "home" to #verify that the *design* is correct. Fault testing is done by the foundry #to verify that the parts are *built* correctly. By definition, any parts #that correctly pass the test pattern you give the foundry are good enough #for you to buy, whether or not they work in your circuit. # #In sum, fault pattern generation and simulation pattern generation are very #different problems. Sorry, but they are not two independent problems. I come from an ASIC background and test vectors given to the vendor are more often than not the monitored outputs and the input driving from a functional simulation. That is the results your simulation are what the vendor gets to test chips. If you have scan then this is not the case and you would have the results from an ATPG run to give to the vendor. Now to answer the original questions. The problem the original person was having is one that is common if conversions from FPGA to ASIC where the orignial design engineer did not think he would ever go to an ASIC and where an FPGA can usually be pulled out of a board if it was programmed wrong or failed an ASIC usually can't or on the same token if you don't have test paterns you can't identify bad parts before you get them. For test the circuit has to be predictable this usually means having an async. reset to set all flop in the design to a known state before the simulation/test program starts to run. If you are migrating from FPGA to ASIC it would make sense to do a little redesign and add resets to the flop that don't have them if the will affect the power on state and initial simulation results. The other option you have is if there is a pattern that will put the chip into a deterministic state you run that pattern first without checking the output. Once you can determin the state of the chip you check the output. But you have to have a fixed number of vectors to do that. Kent -- /* "There is no king who has not had a slave among his ancestors and */ /* no slave that has not had a king among his." ---- Helen Keller */ /* Kent L. Shephard ----- K. L. Shephard Consulting */Article: 626
In article <3fnavg$bt@paperboy.ids.net> randraka@ids.net writes: # #Clearly, one need not add resets to the logic to make the circuit simulatable. #What is required is some way of initializing the subject Flops to 1's and 0's. #One way to do this in Viewlogic is to use the assign and release statements to #force the flops for one clock cycle as I detailed in my previous post. You can #assign any initial value to any number of the flops using this technique. In #fact, you can assign a random initial state using the waveform command. In #this case your command file would contain: He needs to be able to repeat this result in a testor. This is fine for simulation but it does nothing for the person's real problem of a print on change file that you can use for real vectors to test the part. His only alternative when moving to an ASIC is to provide a reset for internal states that are observable at outputs. If you can't get the chip to a deterministice state after x number of cycles then the device is not testable and you won't know if your devices are failing due to a process problem or something else. The objective is to test the parts and simulation in viewlogic is one way to get the vectors to do so. # #v init <list of flops to be initialized> #wfm init 0=rand #c #r init # #This assigns the list of flops to a vector for convenience, assigns a random #start value, runs it for one clock cycle (assuming you've already set up your #clocks), then releases the init vector allowing the circuit to take over. But it does nothing for a real part which is what he eventually wants to test. Kent -- /* "There is no king who has not had a slave among his ancestors and */ /* no slave that has not had a king among his." ---- Helen Keller */ /* Kent L. Shephard ----- K. L. Shephard Consulting */Article: 627
arin@rapid.fi.uib.no (Arin Kjempenes) writes: >I'm building a PCI target, and I'm looking for sourcecode >on how to implement it a CPLD. >I'm using ALTERA so AHDL code would be great, >but I'll appreciate other languages as well. Contact the Altera Literature Department, fax +1 408 944 0952, and ask for their "PCI packet". It was described in their November 1994 "Altera News & Views" newsleter. Graeme Gill.Article: 628
Charles Shelor <cshelor@cpdsc.com> writes: >>Sure, just create a <design>.ctr file in the directory in which your >>design lives, and put the information in there. For example: >> >>MAX_LOAD 1000 CLOCK >>MAX_LOAD 4 RESET >> >>or whatever. >> >>Good Luck. >> >Wouldn't this be much easier if synthesis vendors would use VHDL attributes >for this type of information? Placement constraints, timing constraints, >loading constraints, ... could all be managed in a device independent manner. >This information would also remain with the source code where it would be >a visible reminder of the constraints during the design and later the >maintenance of the circuit. > >Charles F. Shelor AMEN..... YOu can get quite a bit of the way there with some of your own atributes and an awk (or perl etc) program or 2. It would be better of course if it was an integral part of the tool. Quick survey how many of you have writen a utility in under 1 hour that the tool vendor said was not possible/planned/or"any day now". I would bet that the results will show that a lot of users are still doing a lot of work that they have already paid for....Article: 629
In Article <D2rL8r.5I4@infoserv.com> kent@infoserv.com writes: >In article <3fnavg$bt@paperboy.ids.net> randraka@ids.net writes: ># >#Clearly, one need not add resets to the logic to make the circuit simulatable. >#What is required is some way of initializing the subject Flops to 1's and 0's. >#One way to do this in Viewlogic is to use the assign and release statements to >#force the flops for one clock cycle as I detailed in my previous post. You >can >#assign any initial value to any number of the flops using this technique. In >#fact, you can assign a random initial state using the waveform command. In >#this case your command file would contain: > >He needs to be able to repeat this result in a testor. I couldn't agree more. I am always careful to make sure the circuit reaches a known state after some known number of clocks both for testability (which applies to automated board level testing as well as to ASICs) and easier simulation (a known state allows use of VHDL testbenches as well as automatically checking outputs at given times). Both cases require a known state at a specific time to work. My point in my earlier post was that without a starting state, the simulator can't advance to a known state without somehow forcing an initial condition. That condition can be forced either by a hardware reset if it is available, or by forcing an initial vector by some method similar to the one I proposed. In the actual hardware, the initial state is known internally, even though it may not be predictable. A good design will allow the hardware to get to a predictable state after some known sequence of vectors is applied. This sequence may or may not include a master reset. In high performance FPGA designs, the asynchronous reset can be dangerous if care is not taken to ensure the setup and hold times for reset to clock at each flip - flop are met. This generally means the externally applied reset pulse needs to be synchronous with the clock(s). If not, the likelihood of a violation increases as the clock frequency increases. A violation can result in a state other than the intended state. For this reason, I do not normally recommend the use of the async sets/resets in FPGA designs. -Ray Andraka the Andraka Consulting Group 'the high performance FPGA design specialist' 401/884-7930 FAX 401/884-7950 email randraka@ids.netArticle: 630
For what its worth I would say that all your flip flops and latches should have a reset or preset. Not only does it make simulation much easier, should you ever wish to translate it into an ASIC then the test program will certainly need some way of getting the circuit into a known state. OK it uses a bit more silicon area but so what? Unless you pushing right up to the limit on utilisation it doesn't matter. If you are near the limit you should be considering a larger device in any case because as sure as night follows day the specification will change at the last minute and you will have to pack even more in. Then again perhaps I am a cynic. Mike Forster Perkin Elmer Ltd UKArticle: 631
Hi. This is not an appropriate forum for this question, so my apologies in advance. I am, however, not aware of any appropriate news group. We are urgently looking for XC4005H-5PQ240C chips (5, in particular). We have been stiffed by our suppliers, so the matter is now extremely urgent. Does anyone know of any source which would have these in stock - anywhere in the world? Thanks for any replies. Ken.Article: 632
In <3fj72r$gs3@due.uninett.no> arin@rapid.fi.uib.no (Arin Kjempenes) writes: > >I'm building a PCI target, and I'm looking for sourcecode >on how to implement it a CPLD. > >I'm using ALTERA so AHDL code would be great, >but I'll appreciate other languages as well. > >I have made a target myself but I'm not pleased with >the configuration-register soultion, so any tips >(sourcecode) are welcome. > >(I'm using few of the configurationregisters so I want >to implement them inside the PLD.) > >I've got AP-396 from INTEL, which contains sourcecode >(PALASM2) for both master and target, but they are >using an external configuration-registers. > > >-- >Arin Morten Kjempenes Phone: +47-55-212712 >Fysisk institutt +47-55-291802,277 >Universitetet i Bergen Fax: +47-55-318334 >Allegt. 55 E-mail: >N-5007 Bergen Arin.Kjempenes@fi.uib.no > > Arin, Altera does have AHDL macrofunctions available for both the FLEX8000 and MAX7000 families. You can call USA 408.894.7144 for the literature packet with a disk. Your local distributer may already have these. Try N.C. ScandComp Norway A/S Aslakveien 20 F 0753 Oslo 7 Norway TEL 2-500650 Contact me if you have any problems. I have copies I can send if neccesary. Good Luck Derek PalmerArticle: 633
I trust this posting is appropriate as I have worked exclusively with fpgas since 1985. Since founding HighGate Design several years ago, and hundreds of fpga designs later, I have decided to leave HighGate. I now work with TRG, a digital design consulting group. My new info. is: Rocky Awalt The Rockland Group P. O. Box 368 Garden Valley, CA 95633 voice 916-622-7935 fax 916-622-7637 e-mail rockland@ix.netcom.com Thank you, RockyArticle: 634
A while ago, someone posted some information about common Xilinx failures here. Here's my $0.02: We've had a fair number of Xilinx part fail due to SCR latchup. The problem is not due to having I/O pins driven by parts using different power supplies, but instead from the power supply recovering from a brief short to ground. What happens usually is an engineer is probing parts on a board, and accidentally bridges +5V to ground. Then one or more parts (often on other boards in the system) die. In one instance the part's case actually cracked. Have others had similar problems? Has anyone come up with a solid protection against this? Also, does anyone have any of the original failure information posted here? Other things related: all of the boards in the system have at least 100uF on the +5v. We are using XC4000 series. Thanks! email: rpadula@megatest.comArticle: 635
>From: wolf@aur.alcatel.com (William J. Wolf)
>Newsgroups: comp.arch.fpga
>Subject: NeoCAD Experience
>Date: 19 Jan 1995 16:58:25 GMT
>Organization: Alcatel Network Systems, Raleigh, NC.
>Lines: 45
>Message-ID: <3fm5nh$sdc@aurns1.aur.alcatel.com>
>Reply-To: wolf@aur.alcatel.com
>NNTP-Posting-Host: aurs79.aur.alcatel.com
>
>When NeoCAD first started selling, they pushed their tool as a better
>place and route tool for Xilinx. Faster, higher utilization, etc.
>And it could retarget to other vendors. Obviously, vendor independence
>is attractive for lots of reasons. I'll take that as a given - please
>don't get into that for this thread.
>
NeoCAD tools were initially recognized for their ability to
deliver higher utilization and performance on Xilinx FPGAs than
the vendor-supplied, XACT software. Today, NeoCAD tools are
still employed to ensure the highest levels of utilization and
performance on Xilinx designs, but also to design AT&T ORCA
FPGAs, Motorola MPA FPGAs and most recently, Actel and Texas
Instruments FPGAs. NeoCAD has a product, The FPGA Evaluator,
which enables the designer to implement their actual design in
any of our supported vendors’ devices to determine the best
technology, device family and specific device for their design.
>Since Xilinx has significantly improved their place and route tools over
>the last few years, I am currious whether NeoCAD produces better results
>if you are just concerned with placing and routing Xilinx devices.
>
>Does anyone have benchmarks for the latest Xilinx versus the latest NeoCAD
>software releases?
>
>Perchance a breakdown of 3000 and 4000 families?
Xilinx has done a very good job with their last release of
software. The latest version of Xilinx XACT shows improvement
in many areas. However, NeoCAD still provides performance
advantages on the XC3000 and XC4000 devices we support.
There have been benchmarks published by each company that show
each tool performing well on a set of benchmarks. Recently, a
set of benchmark designs was run through FPGA Foundry in Europe
by a Xilinx representative. The NeoCAD tool provides varying,
user-selectable, levels of effort and for these benchmarks, the
highest level was not chosen. As a result, the benchmark does
not indicate the best results both tools could produce, as do
all benchmarks we run internally.
NeoCAD has its own set of benchmark data in which a Xilinx
expert ran the Xilinx XACT software, and then the NeoCAD
software. We are happy to provide the benchmarks results to
anyone interested. However, NeoCAD maintains that the best way
to determine which tool is best suited for your FPGA design
needs is to evaluate the tools on your design, using your
design methodology. Only then can you determine which tool is
best for you. NeoCAD makes this easy with our FPGA Evaluator
(more on this below).
>Is NeoCAD keeping up with the proliferation of Xilinx products? What kind
>of lag is there for support of new devices and families? Which families
>are currently supported? Does it support X-blocks?
NeoCAD has continued a strong commitment to supporting Xilinx
FPGAs since our initial support of the XC3000 in 1991. In some
cases, we delivered final customer software before Xilinx.
This was true with the XC3195 and the XC4013. We have kept
current with all Xilinx mainstream devices to date. We do not
currently support the XC4000H or the XC4025, but we are
investigating providing support for the XC4025 in the near
future. What level of interest is there for this device?
NeoCAD does support XBLOX and RPMs.
>Are there synthesis issues? To optimize designs it is important to link
>verilog/vhdl synthesis with placement and routing. Do these links exist?
>Is timing information passed directly or must the user enter it twice?
Effective synthesis of FPGAs requires both architecture specific logic
optimization and technology mapping, and a timing constraint interface
between synthesis and layout. NeoCAD has made considerable investment
in both areas, and provides solutions with leading synthesis suppliers
Synopsys, Mentor Graphics (AutoLogic), Exemplar, and IST.
Logic optimization / technology mapping requires the synthesis tool to
understand the basic building blocks of the target architecture (e.g.
CLBs for Xilinx, PFUs, for AT&T ORCA). Significant progress is being
made toward this through a combination of algorithmic improvements
developed by various synthesis suppliers and target specific libraries
developed by NeoCAD and its silicon vendor partners.
A timing constraint interface between synthesis and layout is also needed
due to the non-deterministic timing of FPGA architectures. A link which
interprets constraints used during synthesis and automatically applies them
to layout can significantly reduce design iterations by ensuring both
tools are working to the same goals. NeoCAD was the first FPGA
implementation tool supplier to provide such a link, initially
with Synopsys FPGA Compiler and Design Compiler (High Level
Design Link).
Current availability of libraries and timing interfaces from NeoCAD and its
partners varies by synthesis vendor. Please contact NeoCAD for up to date
information.
>
>In general, is there anything you especially like or dislike about NeoCAD tools?
I'll leave this to our customers...
>
>
>What is the latest update on CAE vendors like Cadence, Mentor, Viewlogic
>working with NeoCAD. Are they reselling NeoCAD, developing their own FPGA
>place and route tools, both, or doing nothing? (Anyone from Cadence, Mentor,
>Viewlogic, etc. care to post the official line on this?)
NeoCAD provides complete CAE integration support (Capture, Simulation) with
Viewlogic and Mentor Graphics. Intergraph recently completed
the integration of FPGA Foundry into their VeriBest design
environment. In addition, NeoCAD offers a Verilog back
annotation solution, and will introduce a VITAL compliant VHDL interface
this year. Additional integration kits with vendors such as
Cadence (Concept), and Orcad are also being planned - please
contact NeoCAD for up to date information. Any EDIF or FPGA
vendor netlist format targeted to one of our supported
libraries can be used as the input file to FPGA Foundry. This
currently includes XNF, ADL, EDIF/LPM, and ViewLogic WIR
formats and libraries.
NeoCAD's recommends the LPM 2 0 standard (Library of
Parameterized Modules) for vendor-independent design capture,
and we have created special optimizations (including hard
macros) to best implement designs captured with LPM in all FPGA
architectures we support. Several CAE suppliers are developing
LPM interfaces from their capture and synthesis environments,
which will result in a rapid expansion of design input options
for the NeoCAD design environment. Furthermore, several FPGA
silicon suppliers are also working on LPM compliant module
generation technology and libraries (e.g. AT&T, Actel), which
will further complement NeoCAD design flows and options.
Mentor Graphics currently OEMs and re-sells NeoCAD products. Viewlogic
offers an environment which attempts to integrate vendor specific tools
into a complete packaged solution. Inconsistencies between the vendor
tools in terms of both functionality and library / constraint formats
have significantly limited Viewlogic's ability to offer a viable multi-vendor
solution. Cadence announced almost two years ago plans to
develop and market FPGA place and route software. They have
yet to bring this product to market, and appear to have backed
away from their plans.
>Finally, how good is NeoCAD support for the latest Actel devices? About
>a year ago, I heard that Actel was worried about NeoCAD cutting into
>their CAD revenue and was not working with them.
NeoCAD's initial support of the Actel technology will be the
ACT2 family. As with other supported vendors, we have a strong
committment to the Actel technology and will ensure that our
customers have access to their latest advancements. We also
strive to support the silicon road maps of all supported
vendors, as this is in the best interest of our mutual
customers. Although Actel did not participate in NeoCAD's
initial development process, they have taken a refreshingly
positive position to our support of their technology. Dennis
Nye, Actel's Vice President of Marketing, made the following
statement in the January 16, 1995 issue of EE Times:
"If new users come from NeoCAD's installed base, that's great.
It provides another class of user that can get access to Actel
devices.... If it does a good job and we see a growing demand,
we'll look to formalize some kind of support for the tool."
We look forward to increasing the number of designers who have
access to Actel's technology and the possibility of a formal
relationship in the future.
NeoCAD's support of Actel FPGAs also includes support of the
Texas Instruments TPC12 device family, which is the second
source for this technology. The NeoCAD Actel /Texas
Instruments support will provide the same functionality
provided for all supported vendors with the following benefits:
Timing-driven place and route
A fully functional graphical editor which supports manual
placement, routing and timing analysis.
Automatic buffer insertion
Overall design process and performance benefits
Support of Actel technology in NeoCAD's FPGA Evaluator.
NeoCAD's FPGA Evaluator enables assisted device selection by
allowing designers to try their design across any NeoCAD
supported vendor enabling the selection of the optimal device
for their specific design. A special promotional configuration
of the FPGA Evaluator is available for a limited time for of
$99 U.S. A press release on FPGA Evaluator is also attached.
>Since NeoCAD is well represented in this group, I presume they will respond,
>which is appropriate. I hope we will also hear lots of direct user feedback.
NeoCAD was founded in November of 1990 to address the need for
high-performance FPGA design tools. NeoCAD is the only company
focused exclusively on providing device-independent FPGA
implementation tools. NeoCAD's flagship product, FPGA Foundry,
is a device-independent FPGA design system providing timing
driven place and route, 100% back-annotation, graphical editing
and timing analysis, and integration into leading design
methodologies, all within a single design environment. FPGA
Foundry supports Actel, AT&T, Motorola, Texas Instruments and
Xilinx FPGAs.
NeoCAD currently is the exclusive provider of software for the
new Motorola MPA family of FPGAs and the preferred software for
the AT&T High Speed 3000 and ORCA families of FPGAs.
I hope that this answers most of the questions on NeoCAD.
NeoCAD also has responded to the market with a new FPGA Foundry
product series. This allows the designer to only purchase the
level of functionality and device density they need, while
supporting the ability to upgrade as required. PC prices begin
at $995 U.S. list. NeoCAD's new, low-cost Access system
provides support for all vendor's devices under 3K gates
(approximate), timing-driven place and route, an EDA vendor
integration kit for $2,995. This configuration has been very
attractive to new users of FPGAs.
We look forward to your comments and future interest in NeoCAD.
For more information on NeoCAD or its products, please email to
fpga@neocad.com, or call 1-800-888-FPGA.
Kenn Perry
VP of Marketing
NeoCAD, Inc.
kenn@neocad.com
==============================================================
NeoCAD ANNOUNCES PRODUCT PROVIDING ASSISTED FPGA DEVICE
SELECTION
The FPGA Evaluator allows users to choose the best FPGA
before implementing a design
Boulder, CO, June 1, 1993 -- NeoCAD, Inc., the only company
providing an open design environment for field programmable
gate arrays (FPGAs), today announced the FPGA Evaluator, a
design tool for assisted FPGA device selection. As the only
supplier of high performance, vendor independent FPGA
solutions, NeoCAD is in a unique position to provide a
consistent and comprehensive solution for FPGA evaluation.
With the FPGA Evaluator, users can for the first time assess
the viability of multiple FPGA device alternatives for their
specific application before committing to a device. The
decision on which device is best suited to a design can now
be made without detailed tool or architectural knowledge.
According to Kenn Perry, vice president of marketing at
NeoCAD, "A large number of potential FPGA users have held
back from using these devices due to their uncertainty about
FPGA technology and design methods. The FPGA Evaluator will
help grow the FPGA market by allowing designers to
objectively evaluate the merits of this technology and
identify the most appropriate devices for their designs."
----------------------------------------------------
The FPGA Evaluator takes the risk out of FPGA device
selection
----------------------------------------------------
The FPGA Evaluator is the only solution for multi-
vendor device evaluation within a single implementation
tool, eliminating the need for designers to be knowledgeable
of the differences between vendor supplied tools. The FPGA
Evaluator utilizes NeoCAD’s leading edge technology,
including physical mapping and optimization, timing and
frequency-driven place and route and graphical design
analysis to provide the information required to make
informed device selections. Users can enter their designs
through FPGA vendor native netlist formats or through
NeoLPM, NeoCAD’s Library for Parameterized Modules (LPM)
compliant library. LPM is especially ideal for new FPGA
users, providing a means to create designs that are easily
implemented in a variety of FPGAs. Once the design is
entered, an evaluation process manager assists users through
three key stages of device selection: identification of
device candidates, speed grade options and precision device
assessment.
---------------------------------------------------------
FPGA Evaluator versions for both new and experienced FPGA
users
---------------------------------------------------------
FPGA Evaluator is available in two configurations. The
first configuration enables users to identify device and
speed grade candidates for their designs based on
architectural resource utilization and component delays.
This configuration is a stand-alone product and includes the
evaluation process manager, physical optimization and
mapping technology for all FPGA Foundry supported vendors,
as well as NeoLPM for new design entry. This version of the
FPGA Evaluator is ideal for the new or inexperienced FPGA
user, providing an easy to use tool to investigate the
viability of FPGA technology for a given design application
and learn about the relative merits of various FPGA
architectures.
The second configuration adds the technology required
to enable a third, more detailed, stage of the FPGA
evaluation process: precision device assessment. This step
utilizes timing and frequency-driven placement and routing
of a design to provide timing information based on
interconnect delays. Graphical design analysis capabilities
add the ability for the user to quickly identify critical
timing areas in their design and explore options for
resolving them. This version of FPGA Evaluator is
beneficial for experienced FPGA users, providing an ongoing
ability to assess FPGA options prior to committing to a
specific device, or as an upgrade for new users.
NeoCAD was founded in November 1990 to address the
need for high-performance design tools for programmable
technologies. NeoCAD is the only company providing
device-independent implementation tools to support the
growing number of unique FPGA architectures. NeoCAD is
headquartered at 2585 Central Avenue, Boulder, Colorado
80301. 303/442-9121.
==============================================================
Article: 636
Hi:
I just heard that FPGAs of Xilinx 5000 series have newly been announced
in Taiwan. Can somebody tell me the new features of this architecture,
especially, for its combinational logic part (Look-up Table configuration) of
the CLB? Thanks for your any reply.
--
==========================================================================
Juinn Dar Huang
Institute of Electronics
National Chiao Tung University
m8111590@yankees.ee.nctu.edu.tw
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Article: 637I am posting this for Lois Cartier of Xilinx : Don: I take pride in being too honest to make a good marketing type, although some people have doubtless called me even worse things. I also did not write the article to which you refer, but I have to admit that I read it before publication and did not spot the errors. (You have permission to call me dimwitted.) It certainly appears that we made some mistakes, although I don't think we made quite as many as you think. And they were definitely not deliberate, although with the things that go on in advert- ising these days I can't blame you for making that assumption. Before I begin, I would like to make a very important general point. Each ORCA PFU is roughly the equivalent of two XC4000 CLBs with the input pins bolted together and with shared outputs. This organization makes some functions easier to implement and others more difficult. But you can't fairly make one-to-one comparisons between two non-equivalent entities. Anyway, you are basically correct in your analysis for the 2C: : X4000 ORCA Circuit : ------------------------------------------------------------- : 1 CLB 2 PFU 9-bit parity : The truth is: ORCA can implement up to 11 bits of : parity with a single PFU. It looks like you're right, in theory. According to the data sheet, it should be possible to map this function into a single PFU by using the C0 input. So a single Xilinx CLB handles nine bits, while a (twice as large) PFU handles 11 bits. However, NeoCAD _implements_ an 11-input XNOR in 2 separate PFUs--I just tried it. There may be a way to apply attributes forcing the mapping into a single PFU--I'm not familiar enough with NeoCAD/ORCA to know how. I used "pack logic blocks" and "optimize" options for NeoCAD and got the 2-PFU result. : 1 CLB 4 PFU 8-bit registered-input parity generator. : +8 IOB +8 IO The truth is: while ORCA does not have registered I/O, : the PFU registers can be connected directly to I/O pads. : It only takes 2 PFU to implement this circuit. Right again. If you register your inputs using the direct connects from the pads, the flip-flop outputs can loop back into the same PFU and use the function generators. So the Xilinx part uses 1 CLB and ORCA uses 2 PFUs, each of which is twice as large. The I/O flip-flops can be useful, which was the valid point. (However, our statement was wrong.) : 1 CLB 2 PFU 6-input function and sync of a separate signal. : The truth is: X4000 can NOT implement completely-covered : 6-input functions in a single CLB. The ORCA CAN implement full : 6-bit functions AND has 4 registers that can be used : independently for synchronization. I talked to the author and he says he wrote this incorrectly. He meant a _registered_ 6-input function. In that case, all four LUTs are used to implement the 6-input function, and all four flip-flops have to accept their input from the LUT outputs, in order to register the single output. (Either ALL flip-flops take their input from the function generators, or ALL use the direct inputs.) Therefore, the other three flip-flops are unusable, and the independent signal must be registered in a second PFU. If that correction is inserted, the statement is correct. Now we get to the meat of the matter, which is the logic capacity of a Xilinx CLB versus a PFU. The point here is that a single Xilinx CLB is not SUPPOSED to be the equal of one ORCA PFU. AT&T made the ORCA PFU twice the size of the CLB, so we have to compare 2 Xilinx CLBs with 1 ORCA PFU. Essentially, ORCA removes one layer of hierarchy. This is not exactly an earth-shattering difference. (By the way, the new XC5200 family also uses a larger basic building block, so it COULD be compared with the PFU on a one-to-one basis.) . The Xilinx 4K CLB has 2 FFs, ORCA PFU has 4. . The Xilinx 4K CLB has 2 function generators, the ORCA PFU has 4. . The ORCA PFU is not quite equal to two CLBs, because of the shared inputs, only five outputs, etc, and this is reflected in the price. . ORCA does NOT supply PFU arrays the same size as Xilinx CLB arrays, so it does not follow that ORCA should cost twice as much as a Xilinx array the same size. Xilinx devices provide, on average, about 50% more CLBs than ORCA does PFUs, for the same gate count (and about the same amount of money, I believe.) Yes, the PFU has twice as much RAM capacity, which is inevitable since it is equivalent to 2 CLBs. See discussion above. Oh, and by the way, at the time that white paper was written, NeoCAD didn't support the ORCA 2C, as is clearly stated in the white paper in the last sentence on page 7. They do now, and any future discussion of the software has to focus on NeoCAD. NeoCAD is a fine product and supports Xilinx as well as ORCA. By the way, thanks for the kind words at the end. We DO try. (Usual disclaimer, and yes, I DO work for Xilinx, and proud of it.) Lois Cartier Corporate Applications, Xilinx loisc@xilinx.com P.S. And thanks for the defense, Bob!Article: 638
loisc@xilinx.com (Lois Cartier of Xilinx) writes: > [ Stuff deleted ...] > It looks like you're right, in theory. According to the data sheet, it > should be possible to map this function into a single PFU by using the > C0 input. So a single Xilinx CLB handles nine bits, while a (twice as > large) PFU handles 11 bits. However, NeoCAD _implements_ an 11-input > XNOR in 2 separate PFUs--I just tried it. There may be a way to apply > attributes forcing the mapping into a single PFU--I'm not familiar enough > with NeoCAD/ORCA to know how. I used "pack logic blocks" and "optimize" > options for NeoCAD and got the 2-PFU result. This doesn't seem like a fair comparison. NeoCad should have nothing to do with it. This is like comparing two microprocessors based on how well a third party's compiler works. The ORCA can implement an 11-bit parity generator in a single PFU. The fact that you are still arguing against this is quite telling: You wish us to overlook the facts in favor how you want things to work. This is my major complaint about the Xilinx document in question: the thing is full of errors and twists on the truth. It goes beyond what is acceptable as sales hype, and raises questions about Xilinx in general: Are all engineering documents this inaccurate? (Obviously not). Is it indicative of a trend in Xilinx management? (I hope not). Should Xilinx pull the document off the shelves before AT&T starts filing lawsuits? (Yes). Have they? > Now we get to the meat of the matter, which is the logic capacity of a > Xilinx CLB versus a PFU. The point here is that a single Xilinx CLB is > not SUPPOSED to be the equal of one ORCA PFU. AT&T made the ORCA PFU twice > the size of the CLB, so we have to compare 2 Xilinx CLBs with 1 ORCA PFU. > Essentially, ORCA removes one layer of hierarchy. This is not exactly > an earth-shattering difference. Nothing about any of this is "Earth shattering" but for many design styles it is significant (More than a factor of 2 in performance). It is more efficient in logic utilization and, more importantly, reduces the impact on routing resources. >. The Xilinx 4K CLB has 2 FFs, ORCA PFU has 4. >. The Xilinx 4K CLB has 2 function generators, the ORCA PFU has 4. >. The ORCA PFU is not quite equal to two CLBs, because of the shared inputs, > only five outputs, etc, and this is reflected in the price. Again, my opinion is that the ORCA PFU is 1.5 to 2.5 times the usablility of a Xilinx CLB. I recently sketched out a preliminary floor plan for a design and found I could fit about 1.4 times the functionality in an ORCA 2C12 (324 PFU) versus a Xilinx 4013 (576 CLB). For this design the PFU is about 2.5 times as useful as the CLB (576/324*1.4). This figured heavily in my recent decision to purchase NeoCad software and design-in the ORCA. >. ORCA does NOT supply PFU arrays the same size as Xilinx CLB arrays, so > it does not follow that ORCA should cost twice as much as a Xilinx array > the same size. Xilinx devices provide, on average, about 50% more CLBs > than ORCA does PFUs, for the same gate count (and about the same amount > of money, I believe.) Here are the prices that I am using for comparison. I think the the ORCA 2C12 is roughly equivalent to the Xilinx 4013: ORCA 2C12-3: Xilinx 4013-4: 324 PFU (18x18) =~ 648 CLB 576 CLB (24x24) 288 I/O cells 192 IOB $420 208-pin PQFP $745 208-pin PQFP $586 304-pin PQFP Note that the usable I/O of the 208-pin package is about the same for ORCA vs. Xilinx, and is a better comparison. > Yes, the PFU has twice as much RAM capacity, which is inevitable since it > is equivalent to 2 CLBs. See discussion above. Which means that address lines need 1/2 the fanout and you can go to 64 bits deep before requiring an output multiplexer. > By the way, thanks for the kind words at the end. We DO try. You're welcome. I've been a Xilinx user for years, and have a certain fondness for the company. I'd hate to see it turn into an obese marketing-driven company like er... AT&T? -DonArticle: 639
Any personal success/horror stories using the former Intel / now Altera flex logic 8160 or 780 parts? --- Michael G. Reeves email: miker@megatek.com Megatek Corporation voice: (619) 675-4300 x2663 16868 Via Del Campo Court facsimile: (619) 675-4341 San Diego, CA 92127 -- --- Michael G. Reeves email: miker@megatek.com Megatek Corporation voice: (619) 675-4300 x2663 16868 Via Del Campo Court facsimile: (619) 675-4341 San Diego, CA 92127Article: 640
kenn@neocad.com (Kenn Perry) writes: >Xilinx has done a very good job with their last release of >software. The latest version of Xilinx XACT shows improvement >in many areas. However, NeoCAD still provides performance >advantages on the XC3000 and XC4000 devices we support. Very true. As a user of both systems now, as far as I'm concerned, there is no comparison at all. XACT is difficult to use, and its routers (in particular its latest routers are a joke) >> >>What is the latest update on CAE vendors like Cadence, Mentor, Viewlogic >> >>working with NeoCAD. Are they reselling NeoCAD, developing their own FPGA >>place and route tools, both, or doing nothing? (Anyone from Cadence, Mentor, >>Viewlogic, etc. care to post the official line on this?) NeoCad works well with Mentor. Here in Sydney, the Mentor agent is the NeoCad agent. I can't speak about the others. >>which is appropriate. I hope we will also hear lots of direct user feedback. >supporting the ability to upgrade as required. PC prices begin >at $995 U.S. list. NeoCAD's new, low-cost Access system >provides support for all vendor's devices under 3K gates >(approximate), timing-driven place and route, an EDA vendor >integration kit for $2,995. This configuration has been very >attractive to new users of FPGAs. I wish that was the case here. I recently got a quote, for a client, of NeoCad S/W for a PC with only basic XC3000 support. The quote was almost $A10,000, ie about $US7500. The XACT quote was even higher (but only marginally). So what gives!! >We look forward to your comments and future interest in NeoCAD. In Sydney most good engineers work as contractors. Companies here are run by marketing types or financial types who think that engineers don't care too much about money, and there are heaps of them, and an engineer is an engineer is an engineer. As a consequence there are a small army of us going around fixing up everyone's problems for them. From what I gather it isn't that much different in the Bay area at least. Amongst other areas, I work with FPGAs. Very few people here use NeoCad. The main reason is that most companies doing design work bought XACT ages ago, it cost them about $A13 - $25K depending on what they bought and they can't justify throwing it away, especially when NeoCad is just as expensive. Stories about better performance don't really do much for Engineering Managers on tight spending budgets, and every day they have some snake oil merchant telling them that they can't produce anything without this latest emulator, case tool, option on their CRO, project management system, blah blah blah. They get especially infuriated when these same merchants start working on their juniour engineers as well. (I know, I used to be an engineering mngr once before I saw the light) Is this any different State-side? I expect not! >Kenn Perry >VP of Marketing >NeoCAD, Inc. >kenn@neocad.com Well Ken, I would certainly prefer to use NeoCad, but since I can't afford to buy my own, I use what my clients own, and that is almost always XACT. (Oh and since I like to keep being employed I don't make a habit of trying to preach to my clients,..."Oh XACT, version -10 from 1923, O, yes I have used it, and sure, its a fine product and version Sir"Article: 641
Ken Yiu (kky@itd.dsto.gov.au) wrote: : Hi. : This is not an appropriate forum for this question, : so my apologies in advance. I am, however, not aware : of any appropriate news group. None of the normal groups want to encourage suppliers and vendors to trash the 'net. Your normal recourse should be through alternate distribution, and especially NOT through this group. Try calling the factory, first, as they'll have a better handle on who has what parts. If you don't think distributors & vendors are slavering at the thought of forcing their vapid advertising in the faces of 10 million possible customers, then you aren't very familiar with the breed. Most salesmen have all the tact and morals of a weasel, for the same reasons.Article: 642
Hi. We want to use the JTAG port of the XC4000 familiy to configure these devices. Unfortunately there is no detailed description on this topic available. If anyone of you did it already, could you please send me an example program or description. In detail my questions are: how long must I wait from the UPDATE-IR state (instruction configure) to the SCAN-DR state ? May I go there directly or only thru the IDLE state ? If in SHIFT-DR state, may I load all config bits in one sequence or must I go thru UPDATE-DR after every bit / frame / something ? If there is a DSDL file floating around ? (copy please) Cheers, AndreasArticle: 643
I currently have a number of behavioral VHDL models that I need to target into Xilinx FPGAs. I currently use the Model Tech VHDL simulator and am evaluating the best route to a routed Xilinx 3000 series part. I am not interested in automatic partioning or other vendors FPGAs at this stage. I am Sun Sparc based so price comparisons with PCs are not really valid. As I see it I have four options: 1> NeoCAD 2> Exemplar coupled with XACT 3> MINC VHDL input filter and XACT 4> ABEL VHDL input filter and XACT Option 1 would appear to be the simplest route, however I have experience of XACT and am concerned that if my sole FPGA routing solution comes from another vendor that I will miss out on some of the debug tools such as download cables etc. I have had a demonstration of the Exemplar software, but it seems expensive for what is essentially a VHDL to xnf conversion tool (for my application at least). I have some experience of both MINC and ABEL and to my mind these tools are suitable for blocks of a design, but less useful when whole chip designs are required. I am interested in hearing users comments on the relative merits of the four options, or any possible alternatives. Specific answers to the following would be most useful: Options 1 and 2 have the much needed advantage of potentialy allowing back- annotation of routing delays, but how good is this at the moment? Given that I have behavioral VHDL, which tool is likely to make conversion to synthesisable VHDL easier. This possibly ties in with the use of predefined or hard macros. How good are options 1 and 2 at accepting routing time constraints. Idealy I want to put time constraints in my VHDL for design management purposes. I don't mind writing a perl script to extract the relevent information as long as the routing tool can accept it. That's probably enough to get started on. I apologise if similar questions have been asked before, and I don't want to start a slanging match along the lines of NeoCAD is better than X because.... Finally is there a VHDL->FPGA FAQ available. Thanks for getting this far, Mark SnookArticle: 644
davelec@extro.ucc.su.OZ.AU (David le Comte) writes:
>kenn@neocad.com (Kenn Perry) writes:
>
>> ... PC prices begin
>>at $995 U.S. list. NeoCAD's new, low-cost Access system
>>provides support for all vendor's devices under 3K gates
>>(approximate), timing-driven place and route, an EDA vendor
>>integration kit for $2,995. This configuration has been very
|
I *think* you mean $12,995. -- be
>>attractive to new users of FPGAs.
>
>I wish that was the case here. I recently got a quote, for a client,
>of NeoCad S/W for a PC with only basic XC3000 support. The quote was
>almost $A10,000, ie about $US7500. The XACT quote was even higher
>(but only marginally). So what gives!!
I second that, David. My latest quote from NeoCad (in $US) is $4,995
for a *single* vendor (e.g. Xilinx | ATT) design suite for the PC which
included netlist translator, place & route, timing verifier, and
manual layout editor. This package doesn't include support for
FPGAs of 15K gates and up; this is a $1,250 option.
If you want the libraries for *all* FPGA vendors' devices, the
quoted price is $12,995.
For workstation (e.g. SPARC instead of 80x86) tools, if you have to ask
about the prices, then you can't afford it. :-) :-( (funny but sad)
These prices are from a quote dated 13-Jan-95.
Bob Elkind, Tektronix TV Products
Article: 645I am having problems programming an in-circuit Intel/Altera FX780 device. I get frequent verify errors and occasional "unable to open device" messages. Also, it seems like once I program it, I have to cycle the power to program it again. (I'm only trying to program the SRAM at this point, not the PROM). I'm using the Intel flex cable and programming software (pengn). Although I lengthened the cable for convenience, this doesn't seem to have any negative effect. If anything, it seems more reliable with the longer cable! Anyone else notice problems with these devices? -- ------- Bryan Butler butler@world.std.comArticle: 646
In <MIKER.95Jan25125342@sunburn.megatek.com>, miker@megatek.com (Mike Reeves) writes: > >Any personal success/horror stories using the former Intel / now Altera >flex logic 8160 or 780 parts? > Yes, the parts work well. Easily modified on-board. The 780s are SRAM based, need loading via on-board micro. They can be loaded via PC parallel port during debug. 8160s are FLASH-based which is handy. The design tools (via PDS through Intel tool suite) worked fine. The .wir file converter for Viewlogic simulation had problems with bi-directional pins. Have not used the Altera tools on these parts. Good luck. Kevin Curcuru.Article: 647
I have been told there was a discussion about pci here. My problem is to find a pci chipset tha interface easily with a motorola 68040/060. Can anybody help me? Benoit Triquet triquet_ben@lsi.supelec.fr triquet@esesd1.supelec.frArticle: 648
In article <MIKER.95Jan25125342@sunburn.megatek.com>, Mike Reeves <miker@megatek.com> wrote: > >Any personal success/horror stories using the former Intel / now Altera >flex logic 8160 or 780 parts? I used the 780 part in an 84-pin package for teaching sophomore students digital logic design. As you can imagine, students really strain chips electrically with their tendency to short signals and wire things backwards. However, in an entire 15 week semester with 16 students, I never had a failure of any 780 part. In terms of speed (performance) I can't really say anything since the students weren't doing anything more than looking for functional correctness. In terms of density, they tended to run out of I/O before logic since we used the 84-pin PLCC package. The big advantage of the FLEXlogic chip is the ability to configure individual CFBs as 128x10 RAMs for use as registers, buffers, etc. This lets you get an entire system (such as a 4-bit microcomputer) onto a single chip. This was important (to me) since that meant fewer chips had to be purchased and there were fewer wires in the student's designs (lowering the chances of shorting signals). Another advantage of the 780 was the free PLDshell programming tool. It's fast, has about 80% of the features you want, and can run on a low-end PC. Altera says they will be coming out with FLEXlogic support in the MAX+PLUS tools this quarter, so that should a more industrial-strength programming environment. -- || Dave Van den Bout || || Xess Corporation ||Article: 649
In article <D2xKIz.EC1@Corp.Megatest.COM>, rpadula@Corp.Megatest.COM (Robert J Padula) writes: > > A while ago, someone posted some information about common > Xilinx failures here. Here's my $0.02: > > We've had a fair number of Xilinx part fail due to SCR > latchup. The problem is not due to having I/O pins driven by parts > using different power supplies, but instead from the power supply > recovering from a brief short to ground. > What happens usually is an engineer is probing parts on a > board, and accidentally bridges +5V to ground. Then one or more > parts (often on other boards in the system) die. In one instance > the part's case actually cracked. We've experienced similar failures, with the same underlying cause of a slipped scope probes etc. I've had burns off Xilinx 3000 chips when they've gotten into this condition, but the parts usually survive. I've always assumed what happens is that the power glitch puts them into reprogram mode, where they manage to load a duff configuration that causes internal bus clashes. You get a similar effect if you download a bogus bit stream to a 3000 device. I seem to recall that 4000 series devices have a CRC that should prevent this type of problem? My "solution" is simply to put a slow blow fuse on each PCB. If shorting a scope probe doesn't take the fuse out, the overheating Xilinx usually does. Since adopting this practise I've killed no more Xilinx chips, but plenty of fuses.... Cheers, Ian
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