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Does anyone come across utility that will allow taking in Orcad .sch or OrCad netlist file format and convert to Xilinx's .xdf format (suitable for using its FPGA)? Thanks much in advance. If i'm going about in wrong directoy, please let me know. Thanks again. -gshinArticle: 576
We are looking at purchasing a development system for Actel to run on a
HP workstation with a Mentor Graphics environment. Is there anyone out
there using this combination?
=========================================================================
Goran Olsson
Alfven Laboratory, Plasma Physics, Space Group, Electronic Engineering,
KTH (Royal Institute of Technology), Stockholm, Sweden
F1 - The Electric Field Experiment on the FREJA satellite
Two years in orbit 6 Oct 1994
olsson@plasma.kth.se
=========================================================================
Article: 577Chuang Hsien-Ho (eea80593@twis.EE.NCTU.edu.tw) wrote: > I want to find some information about look-up table-based FPGA > made be Motorola. Could anyone help me? Thanks. > -- > =============================== > Hsien-Ho Chuang > eea80593@yankees.ee.nctu.edu.tw > =============================== I would also like to get some information on these devices, so please answer as follow up. Thomas -- -------------------------------------------------------------------------- | Thomas Hadlich Thomas.Hadlich@E-Technik.Uni-Magdeburg.DE | | hadlich@infaut.et.uni-magdeburg.de | --------------------------------------------------------------------------Article: 578
Personally, I think request for basic info is a waste of the net. Call Motorola or a distributor and ask them for their data book, DL201/D "FPGA Data, Field Programmable Gate Arrays. You might also contact NeoCAD - Motorola uses their FPGA tools. Is there anyone out there who is willing to put together a contact list for FPGA & tool vendors to take care of simple questions like this? Perhaps a consultant who wouldn't mind frequently posting their name on the net. Now, if anyone has early user experiences with Motorola FPGAs, pros & cons versus other FPGAs etc, I would like to here that. That is something I can't get by taking the trouble to pick up the phone and call a vendor. --- ~ Bill Wolf, Raleigh NC ~ I can see ~ ~ wolf@aur.alcatel.com ~ the fog ~ ~ My opinions, NOT my employer's ~ at the end of the tunnel ~Article: 579
If anyone knows Lee Fadden's (Harris) complete E-mail address please send it to me. The address I have, lfadden@harris.com comes back as undeliverable. -Ray Andraka randraka@ids.netArticle: 580
In Article 648 Chuang Hsien-Ho (eea80593@yankees.ee.nctu.edu.tw) writes:
>I want to find some information about look-up table-based FPGA
>made be Motorola. Could anyone help me? Thanks.
>
>--
>===============================
>Hsien-Ho Chuang
>eea80593@yankees.ee.nctu.edu.tw
>===============================
Motorola's FPGA architecture has been developed by a small british design company
(Pilkington). Engeneering samples will be available during this quarter.
You'll find some informations at
http://www.demon.co.uk/pmel/index.html
Or send an email to
email info@pmel.com
Also you can download a demonstration version of the software package, which works
only for the smallest device of the family (PMEL 1036, I think)
- ftp ftp.cica.indiana.edu
- ftp micros.hensa.ac.uk
cd pub/cica/win3/demo
pmelcore.zip
Hope this helps,
Gerrit.
-----------------------
telkamp@eis.cs.tu-bs.de
Article: 581In article <D1zu5s.4FA@eunet.ch> roman@pax.eunet.ch (rroman pollak) writes: It is said that Intel gives theirs away for free, try ftp.intel.com, it's a big site however, try under flex or something like that I however prefer Lattice Semiconductor ISP LSI devices, their starter kit is $99.00 and runs under window, it only supports the 1016 device, 32 I/O roughly 2000 pld gates. The upgrade is $650.00 for the higher density devices. What I really like about these is they are in-circuit programmable. For Proto- typeing you can just build a board, and later figure the logic that goes into them..... >Is there a Software on an Anonymous ftp ,to can programm resp. desing a >fpga with my circuits . >I am a normal mortal person, for my is it vary expensive to buy >the original Software mybe for one or two chips programm. >And for the local distributer have the hole installation , >it is also very expensive . >I would like to build my dream Graphic Processor it is >possible with ttl but with 30-40 ic's. >regards, >romanArticle: 582
I am currently designing a board that is using both 240 pin and 208 pin quadflat pack packages for the 4013 and 4010 xilinx chips respectively. My problem is finding specifications for the design of the footprint of these chips. I am using Mentor graphics boardstation which contains some basic pads but nothing very complex. I have checked several books both at our library at UMR and others through interlibrary loan. If anyone could point me to reference material to design the pads for these chips I would appreciate the time spent. William EathertonArticle: 583
Hi, The problem is simple: I've got a schematic with a Xilinx part symbol. After routing the Xilinx part, and after everytime I change my pinout (since the pcb hasn't been made yet) I need to update all the pin number attributes on the symbol. The pin information is available in the Xilinx netlist (.xnf), but it doesn't get backannotated into the ViewLogic wir file by XNF2WIR. Viewgen could be used to create a new symbol from the wir file (but without the pin info, this is almost useless). Xilinx said: "Ask Viewlogic"; Viewlogic said "ask Xilinx!" Has anyone foud a way to transfer all the pin information (pintype=I/O/B; #=pinnumber) to the symbol on the top level schematic? or maybe written a piece of code to do it? I would appreciate any info. Thanks! Marco -- ----- Marco Rivero mrivero@tufts.eduArticle: 584
Marco Rivero (mrivero@emerald.tufts.edu) writes: > The problem is simple: I've got a schematic with a Xilinx part symbol. > After routing the Xilinx part, and after everytime I change my pinout > (since the pcb hasn't been made yet) I need to update all the pin number > attributes on the symbol. The pin information is available in the > Xilinx netlist (.xnf), but it doesn't get backannotated into the ViewLogic > wir file by XNF2WIR. Viewgen could be used to create a new symbol from > the wir file (but without the pin info, this is almost useless). Xilinx > said: "Ask Viewlogic"; Viewlogic said "ask Xilinx!" > > Has anyone foud a way to transfer all the pin information > (pintype=I/O/B; #=pinnumber) to the symbol on the top level schematic? or > maybe written a piece of code to do it? Well, here is one way this could be done. I don't know of any code which does it. But first, a disclaimer: this is only a proposal, not a commitment to do it. In the Xilinx <-> Viewlogic path, Viewlogic's tools do not read xnf. The tools which read and write xnf are written and distributed by Xilinx. This path can be made to work if (1) Xilinx modifies xnf2wir to pass the pin number and pin type information into the wir file and (2) Viewlogic makes sure that Viewgen will use the information to put it on the symbol. - Dave Allen: allen@viewlogic.comArticle: 585
Dave Allen <allen@hex.viewlogic.com> writes: >> The problem is simple: I've got a schematic with a Xilinx part symbol. >> After routing the Xilinx part, and after everytime I change my pinout >> (since the pcb hasn't been made yet) I need to update all the pin number >> attributes on the symbol. The pin information is available in the I have some awk code that does what want for Orcad. Orcad has an Ascii format for libray source files. One prgram makes the symbol the first time another updates it, flags moved and new pins etc. If Viewlogic has a simialr input path this may be of use. If interested send me a note and I will see mail it to you, if I get othere requests I will post it. It is tested only on 3000 series parts but shoudl work for others, some care is needed in use as is the case with most software written for "self use". >Well, here is one way this could be done. I don't know of any code which >does it. But first, a disclaimer: this is only a proposal, not a >commitment to do it. > >In the Xilinx <-> Viewlogic path, Viewlogic's tools do not read xnf. The >tools which read and write xnf are written and distributed by Xilinx. This >path can be made to work if (1) Xilinx modifies xnf2wir to pass the It may be posible to get .xnf with Pin# in it already, would show up as atributes. I have not tried this I simply extract the pin# from the lca file (which is verbose but esaily parsed ascii). I do not back annotate pin types, they are noted when the file is first made. My code can also generate an "Orcad stuff" file to back annotate the pin # onto the schamtic of the Xilinx part. BTW, The program I mentioned before manages the Schematic symbol of the FPGA part that is being designed. The other part helps update the schematic OF the FPGA being designed. ( Almost forgot that I ahve been working primarly in VHDL for FPGA design lately). Martin Moeller mmoeller@delphi.com Moeller, Inc. We do video in Xilinx.Article: 586
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Eighth Annual
APPLICATION SPECIFIC INTEGRATED CIRCUIT
Conference and Exhibit 1995
"Implementing the Information Superhighway
with Emerging Technologies"
Stouffer Renaissance Hotel
Austin, Texas
September 18-22
CALL FOR PAPERS, TUTORIALS, & WORKSHOPS
The IEEE International ASIC Conference and Exhibit provides a forum
for examining current issues related to ASIC applications and system
implementation, design, test, and design automation. The conference
offers a balance of emphasis on industry standard techniques and
evolving research topics. Information is exchanged through workshops,
tutorials, and paper presentations. These promote an understanding
of the current technical challenges and issues of system integration
using programmable logic devices, gate arrays, cell based ICs, and
full custom ICs in both digital and analog domains.
____________________________________________________________________
Technical Papers, Tutorials, and Workshop Proposals are solicited in
the following areas:
ASIC Applications: Wireless Communications, PC/WS and Peripherals,
Multimedia, Networking, Image Processing, Data
Communications, Storage Technologies, Graphics,
Digital Signal Processing
Technologies: Digital, Analog, Mixed Signal, CMOS, BiCMOS, ECL,
GaAs
CAD Tools: Design Capture, Layout, Test, Synthesis,
Modeling, Simulation
Architectures: PLDs, Gate Arrays, Cell Based ICs, Full Custom ICs
Evolving Research: Research in Methodologies, Tools, Technologies &
Architectures
Design Methodologies: System Design, Top-down, Graphical, HDLs
Manufacturing: Process, Testability, Packaging
Workshops: Four or eight hour technical workshops covering ASIC design
knowledge and skills. Proposals to form these workshops for either
introductory or advanced levels are invited. ASIC industry as well as
universities are encouraged to submit proposals. Contact the Workshop
Chair.
______________________________________________________________________
INSTRUCTIONS TO AUTHORS
Authors of papers, tutorials, and workshops are asked to submit 15
copies of a review package that consists of a 500 word summary and
a title page. The title page should include the technical area from
above, the title, a 50 word abstract, the authors names as well as
an indication of the primary contact author with a COMPLETE mailing
address, telephone number and TELEX/FAX/Email. The summary should
clearly state: 1) title of the paper; 2) the purpose of the work;
3) the major contributions to the art; and 4) the specific results
and their significance.
IMPORTANT DATES
Summaries and Proposals due: March 3, 1995
Notification of Acceptance: April 14, 1995
Final Camera Ready Manuscript due: June 2, 1995
SEND REVIEW PACKAGE TO
Lynne M. Engelbrecht
ASIC Conference Coordinator
1806 Lyell Avenue
Rochester, NY 14606
Phone: (716) 254-2350
Fax: (716) 254-2237
CONFERENCE INFORMATION
http://asic.union.edu
Proceedings, and the Advance Program
Airline Discounts, Exhibits, Technical Sessions,
Schedule, Registration, Hotel Sites,
CONFERENCE CHAIR TECHNICAL CHAIR WORKSHOP CHAIR
William A. Cook Richard A. Hull P. R. Mukund
Eastman Kodak Co. Xerox Corp. RIT
Rochester, NY 14650 Webster, NY 14580 Rochester, NY 14623
Phone: (716) 477-5119 Phone: (716) 422-0281 Phone: (716) 475-2174
Fax: (716) 477-4947 Fax: (716) 422-9237 Fax: (716) 475-5845
bcook@kodak.com rah.wbst102a@xerox.com mukund@cs.rit.edu
EXHIBIT CO-CHAIRS
Kerry Van Iseghem Kenneth W. Hsu
LSI Logic Corporation RIT
Victor, NY 14564 Rochester, NY 14623
Phone: (716) 223-8820 Phone: (716) 475-2655
Fax: (716) 223-8822 Fax: (716) 475-5041
kerryv@lsil.com kwheec@ritvax.isc.rit.edu
Sponsored by the IEEE Rochester Section
in cooperation with the Solid State Circuits Council
and the IEEE Austin Section
-------------------------------------------------------------------
Article: 587>Motorola's FPGA architecture has been developed by a small british design >company(Pilkington). Engeneering samples will be available during this >quarter. The Pilkington AutoLayout tool will handle all of the Motorola devices. It will work as a back-end to Capilano Computings DesignWorks schematic capture or ViewLogics schematic. Demos of the Pilkington back-end tools and of the DesignWorks front-end can be downloaded from ftp.wimsey.com in /pub/capilano/demo. Don GambleArticle: 588
In article <3f18hg$vd7@emerald.tufts.edu>, <mrivero@emerald.tufts.edu> writes: > > Hi, > > The problem is simple: I've got a schematic with a Xilinx part symbol. > After routing the Xilinx part, and after everytime I change my pinout > (since the pcb hasn't been made yet) I need to update all the pin number > attributes on the symbol. The pin information is available in the > Xilinx netlist (.xnf), but it doesn't get backannotated into the ViewLogic > wir file by XNF2WIR. Viewgen could be used to create a new symbol from > the wir file (but without the pin info, this is almost useless). Xilinx > said: "Ask Viewlogic"; Viewlogic said "ask Xilinx!" > > Has anyone foud a way to transfer all the pin information > (pintype=I/O/B; #=pinnumber) to the symbol on the top level schematic? or > maybe written a piece of code to do it? > > I would appreciate any info. Thanks! > Marco > -- > ----- > Marco Rivero mrivero@tufts.edu Hi Marco! I have RTFM over and over again to see if some Viewlogic facility will allow this. It may be possible with PCBBCK, which is intended to backannotate from an external PCB layout system and it operates in a very general way. However, trying to figure it all out takes a lot of time which I have very little; So, I end up doing it "by hand". If you ever find a solution to this, I would sure like to hear about it. BTW, I do automate this slightly by first entering the pin number as the attribute value and then using the Windows recorder applet to rapidly add the common prefix (i.e. the "#=").Article: 589
Disclaimer: I am not an employee of Xilinx, AT&T, or NeoCad. The local Xilinx guy left a Xilinx brochure on my desk this morning titled: "Xilinx 4000 vs. AT&T ORCA FPGAs: A feature comparison." It's filled with half-truths and downright lies regarding ORCA. You should watch out for this. Certainly, someone at Xilinx should be slapped upside the head for producing something this deceptive: it makes me wonder if Xilinx can now be written off completely as being run by dimwitted marketing types. (Leaving iterative design out of their original X4000 design flow was probably the first indication of this.) An example of misrepresentation of truth is Table 1. Logic block utilization for various functions: X4000 ORCA Circuit ------------------------------------------------------------- 1 CLB 2 PFU 9-bit parity The truth is: ORCA can implement up to 11 bits of parity with a single PFU. 1 CLB 4 PFU 8-bit registered-input parity generator. +8 IOB +8 IO The truth is: while ORCA does not have registered I/O, the PFU registers can be connected directly to I/O pads. It only takes 2 PFU to implement this circuit. 1 CLB 2 PFU 6-input function and sync of a separate signal. The truth is: X4000 can NOT implement completely-covered 6-input functions in a single CLB. The ORCA CAN implement full 6-bit functions AND has 4 registers that can be used independently for synchronization. ------------------------------------------------------------- The truthful comparison of logic capacity per CLB/PFU is: ================================================================================ X4000 ORCA 2C Fully covered functions: 5-bits 6-bits 1 independent FF 4 independent usable FF Partially covered functions: 9-bits + 1 ind. FF 11-bits + 4 ind. FF RAM capacity: 16x2 16x4 RAM capacity: 32x1 32x2 Plus ORCA has payed attention to making single PFU implementation of other functions: X4000 ORCA 2C ----------------- 2 CLB 1 PFU Quad 2-1 multiplexer. 2 CLB 1 PFU Dual 4-1 mux with registered output. (ORCA uses a trick). Each flip-flop has a multiplexed input that can select either the function generator or a direct input. In addition to extending the logic capability for registered functions, this is intended to be used to create loadable counters: 4 CLB? 1 PFU 4-bit loadable up/down counter with synchronous reset. Of course, the useful comparison between ORCA and X4000 is the performance and cost. Since each ORCA PFU is between 1.5 and 2.5 times the functionality of a Xilinx CLB, you might expect similar-sized ORCA parts to cost about twice as much as their X4000 counterparts. Anyone have the latest prices? Final note: Xilinx also compares its software to AT&T's develompment system. When I called the local AT&T sales office, they recommended that I get NeoCad. They admit that NeoCad has more experience at this kind of software. I've just purchased a NeoCad system and find it superior in many ways (but not all) to Xilinx. I'm sorry if this sounds like I'm ragging on Xilinx. I still feel that Xilinx offers excellent products and service. It's just dissappointing to see such blatant lies and half-truths coming from their marketing folks. If I didn't know better, I'd swear they hired Rush Limbaugh to write it.Article: 590
In article <3f14rd$ati@hptemp1.cc.umr.edu>, <weathert@ee.umr.edu> writes: > > I am currently designing a board that is using both 240 pin and 208 > pin quadflat pack packages for the 4013 and 4010 xilinx chips respectively. > My problem is finding specifications for the design of the footprint of these > chips. I am using Mentor graphics boardstation which contains some basic > pads but nothing very complex. I have checked several books both at our > library at UMR and others through interlibrary loan. If anyone could point > me to reference material to design the pads for these chips I would appreciate > the time spent. > William Eatherton > I have never been able to find a "specification" for Plastic Quad Flat Packs. These are Japanese standards which differs from similar "JEDEC" standards used by most American engineers. There are lots of pitfalls for the unaware. One of the problems is that these standards are metric but most boards designed in the U.S. are based on an english grid. If you simply convert the metric dimensions to english so as to match the grid, you end up with an error that accumulates the farther you get from the datum. This is specially bad in large package such as 208 or 240 pins where there is little room for error; It simply won't work! The only solution I am aware of is to use a PCB layout system that can accomodate both an english and a metric grid and a PCB designer that can use it effectively. Some years back, I heard that JEDEC was working on standards to sort out the differences, but I don't know what became of it. I have always been able to avoid the problem by using ceramic PGA packages, but board space constrains will force me to adopt these metric packages in my current design. My approach will be to use IPC-D-275 for general guidelines. As a final authority, I will rely on my PCB fabricator and board assembly house to check the work of my PCB designer, since these folks deal with these problems every day. Document Engineering has the IPC spec (and most other technical specs). Their voice number is (818)782-1010. You might want to check out the Xilinx Customer Support BBS at (408)559-9327. BTW, I would be very interested in reading other opinions on this subject. -- Lou Santisteban Computer Sciences Corporation Email - lsantist@lsantist.dfrf.nasa.gov P.O. Box 387 Phone - (805)258-3786 Edwards, CA 93523-0387 Fax - (805)258-3567 "The difference between good and excellent is details", Unknown I DO NOT SPEAK FOR CSC, NASA, OR ANYONE ELSE BUT MYSELF!Article: 591
I have inherited an Actel FPGA design which was done using ViewLogic and I'm preparing to convert it to a semi-custom "sea-of-gates" chip. Unfortunately, no simulation of the design was ever done, and simulation files are required by the people doing our conversion. The simulation has fallen into my hands, and my very limited FPGA experience has already gotten me into trouble -- here goes: Many of the flip-flops in the current design do not have any reset/preset. Because of this, predicting the state at power-on is impossible, as is generating the "print-on-change" type data required. I don't think the lack of a master reset(or any reset) is a real problem from a design standpoint, as most of the FFs without resets are in clock-divider chains where state is not really an issue -- it's only from a simulation standpoint that this is troublesome. Any ideas on how this is commonly done, or why it should never be done, will be appreciated. Med Dyer JABRA Corp.Article: 592
FPGA `95 Advance Program
------------------------
1995 ACM Third International Symposium on Field-Programmable Gate Arrays
February 12-14, 1995
Marriott Hotel, Monterey, CA, USA
Note: The Symposium location is now Monterey.
Sponsored by ACM SIGDA, and Actel Corp., Altera Corp. and Xilinx, Inc.
Field-Programmable Gate Arrays (FPGAs) have revolutionized ASIC design by
providing fast turnaround and negligible overhead cost. The challenge in
FPGA research is to improve the speed and density of the devices, and find
new CAD synthesis algorithms that make effective use of the new architectures.
The objective of this symposium is to bring together people who are working
in the many areas of research that are necessary to make a complete FPGA and
high-capacity PLDs.
The technical program consists of papers concerning FPGAs and High-Capacity
PLD device architecture, Computer-Aided Design of these devices, architecture
of multi-FPGA systems and CAD tools associated with these systems. In addition,
there are several papers concerning applications of programmable logic.
The Symposium will be of interest to those developing FPGA architectures, both
at the chip and board level, and those developing CAD algorithms for FPGAs.
The Symposium is not of direct interest to immediate users of FPGAs.
General Chair: Pak K. Chan, UC Santa Cruz
Program Chair: Jonathan Rose, University of Toronto
Program Committee
Duncan Buell, SRC
Pak K. Chan, UCSC
Jason Cong, UCLA
Carl Ebeling, U. Washington
Ewald Detjens, Exemplar
Frederic Furtek, Atmel
Dwight Hill, Synopsys
Sinan Kaptanoglu, Actel
John McCollum, Actel
Jonathan Rose, U. Toronto
Richard Rudell, Synopsys
Rob Rutenbar, CMU
Takayasu Sakurai, Toshiba
Martine Schlag, UCSC
Tim Southgate, Altera
Steve Trimberger, Xilinx
Program
-------
Sunday February 12, 1995
6:00pm Registration
7:00pm Welcoming Reception, Marriott Hotel, Monterey
Monday February 13, 1995
8:20am Opening Remarks
Session 1: General Purpose Architecture
Chair: Tim Southgate, Altera
8:30am On Designing ULM-Based FPGA Logic
Modules, S. Thakur, D.F. Wong, U. of Texas
8:50am Using Architectural "Families" to Increase FPGA
Speed and Density, V. Betz, J. Rose, U. Toronto
9:10am Design of FPGAs with Array I/O for Field
Programmable MCM, J. Darnauer, J. Ramirez,
W. W-M. Dai, U. of Cal. Santa Cruz
Posters: General Purpose Architecture
9:30-10:30am Coffee & Posters
Session 2: Field-Programmable Systems
Chair: Carl Ebeling, University of Washington
10:30am TIERS: Topology Independent Pipelined Routing
and Scheduling for Virtual Wire Compilation,
C. Selvide, A. Agarwal, M. Dahl, J. Babb, Virtual
Machine Works, MA.
10:50am Logic Partition Orderings for Multi-FPGA
Systems, S. Hauck, G. Borriello, U. Wash.
11:10am An FPGA-Based Reconfigurable Co-processor
Board Utilizing a Mathematics of Arrays, H.
Pottinger, W. Eatherton, J. Kelly, T. Schiefelbein,
U. of Missouri - Rolla
Posters: Field-Programmable Systems 11:30-12
LUNCH 12:00 - 1:30
Session 3: Applications I
Chair: Pak K. Chan, UCSC
1:30pm High-Energy Physics on DECPeRLE-1
Programmable Active Memory, L. Moll,
J. Vuillemin, P. Boucard, Digital Equip. Corp,
Paris Res. Lab, France
1:50pm HGA: A Hardware-Based Genetic Algorithm,
S. D. Scott, A. Samal, S. Seth, Wash. Univ,
U. of Nebraska-Lincoln
2:10pm The U.S.C. Multiprocessor Testbed: A Rapid
Prototyping Engine, K. Oner, L. Barroso,
S. Iman, J. Jeong, K. Ramamurthy, M. Dubois,
U. Southern California
Posters: Applications
2:30-3:30pm Coffee & Posters
Session 4: Logic Synthesis
Chair: Richard Rudell, Synopsys
3:30pm Simultaneous Depth and Area Minimization in
LUT-Based FPGA Mapping, J. Cong,
Y-Y. Hwang, U. of California, L.A.
3:50pm Synthesis of Signal Processing Structured
Datapaths for FPGAs Supporting RAMs and
Busses, B. Haroun, B. Sajjadi, Concordia
University.
4:10pm On Nominal Delay Minimization in LUT-Based
FPGA Technology Mapping, J. Cong, Y. Ding,
UCLA.
Posters: Logic Synthesis and Co-Design
4:30-6:00pm Free time/Posters
Dinner 6:00-7:30pm
7:30-9:00pm PANEL
The Architecture/Software Boundary:
Motherhood & Lies.
The most crucial element in the creation of an FPGA is the
interaction between the device architecture and the software
tools that map circuits into the device. The architect should
determine the ability of the placement and routing software,
for example to:
i. Deal with routing architecture's overall structure
(such as symmetric vs. asymmetric; hierarchical vs.
flat, segmented routing etc.)
ii. Handle special purpose connections, such as carry
chains, local interconnect or hard-wired connections.
iii.Route typical circuits with the fixed total amount of
interconnect. For example, should different-sized
parts be given different quantities of routing?
Similarly the architecture should be able to deal with the
capability of the logic synthesis tools to handle:
i. The structure and function of the logic block.
ii. Special logic block features such as adder logic, clock
qualifiers and logic sharing capability.
iii.The effect of the synthesis on the routability of the
synthesized netlist.
Although FPGA vendors and academic architects will
immediately agree with that this interaction is essential, and
is indeed a motherhood issue, it is actually rare that these
interactions are enforced. Similarly, synthesis vendors (and
University CAD researchers) may claim to produce FPGA
architecture-specific algorithms but the reality is otherwise.
What makes it so difficult?
Is interaction really important, or will the effects of poor
interaction be swallowed by the next generation IC process
advance? Perhaps some very clever interactions can produce
major density and speed gains FPGA devices.
If interaction is difficult to enforce for general-purpose
FPGA architectures, will it be possible to create a next
generation of special-purpose architectures?
This panel will explore these issues by bringing together
several people from the FPGA vendor community, the
FPGA user community, synthesis vendors and researchers.
Tuesday February 14, 1995
Session 5: Architecture of Special-Purpose Structures
Chair: Steve Trimberger, Xilinx
8:30am Revisiting the Cascade Circuit in Logic Cells of
Lookup Table Based FPGAs, N-S. Woo, AT&T
Bell Labs, N.J.
8:50am Architecture of Centralized Field-Configurable
Memory, S.J.E. Wilton, J. Rose, Z.G. Vranesic,
U. Toronto
9:10am A Field-Programmable Mixed-Analog-Digital
Array, P. Chow, P. Chow, P.G. Gulak,
U. Toronto
Posters: Special-Purpose Architecture
9:30-10:30am Coffee & Posters
Session 6: Placement, Routing & Testing
Chair: Jason Cong, UCLA
10:30am PathFinder: A Negotiation-Based Performance-
Driven Router for FPGAs, L.E. McMurchie,
C. Ebeling, U. Washington
10:50am Applications of Slack Neighborhood Graphs to
Timing Driven Optimization Problems In
FPGAs, A. Mathur, K.C. Chen, C.L. Liu,
U. Illinois, Fujitsu America, San Jose
11:10am Testing of Uncustomized Segmented Channel
Field Programmable Gate Arrays, T. Liu,
W.K. Huang, F. Lombardi, Texas A&M University
Posters: Routing and Fault-Tolerance 11:30-12
LUNCH 12:00 - 1:30
Session 7: Multi-FPGA Partitioning
Chair: Martine Schlag, UCSC
1:30pm Spectral-Based Multi-Way FPGA Partitioning,
P.K. Chan, M.D.F. Schlag, J.Y. Zien, U. of
California, Santa Cruz
1:50pm Multi-Way System Partitioning into Single or
Multiple Type FPGAs, D. J-H. Huang, A.B.
Kahng, UCLA
2:10pm Multiple FPGA Partitioning with Performance
Optimization, K. Roy-Neogi, C. Sechen, U.
Washington
2:30-3:30pm Coffee & Posters
Session 8: Applications and Bit-Serial Synthesis
Chair: Sinan Kaptanoglu, Actel
3:30pm Techniques for FPGA Implementation of Video
Compression Systems, B. Schoner, J. Villasenor,
S. Molloy, R. Jain, UCLA.
3:50pm An SBus Monitor Board, H.A. Xie, K.E.
Forward, K.M. Adams, D. Leask, U. Melbourne,
Australia
4:10pm High-Level Bit-Serial Datapath Synthesis for
Multi-FPGA Systems, T. Isshiki, W. W-M. Dai,
U. California, Santa Cruz
Posters: Applications 4:30-5:00
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Article: 593In article mk@newsbf02.news.aol.com, med440@aol.com (Med440) writes: >... has fallen into my hands, and my very limited FPGA experience has already > gotten me into trouble -- here goes: Many of the flip-flops in the > current design do not have any reset/preset. Because of this, predicting > the state at power-on is impossible, as is generating the > "print-on-change" type data required. I don't think the lack of a master > reset(or any reset) is a real problem from a design standpoint, as most of > the FFs without resets are in clock-divider chains where state is not > really an issue -- it's only from a simulation standpoint that this is > troublesome. > For what it's worth, I'm currently experiencing the same problem. I'm designing two Actel 1280A's using the Cadence tools and Rapidsim. The problem is the same. I have found that if you run the simulation long enough, sometimes the unknowns get resolved (sometimes not) also you might try checking to see of your simulator will allow you to initialize gates (I can initialize them to all 0, all 1, postive logic state, or negative state). No method I have found is easy or works every time. I have always been succesful at resolving this problem by trial and error when doing functional simulation. HOWEVER, when doing back annotated timing simulation I have had less luck. I am at this very moment waiting for my design to load to see if my next attempt will work. I'll let you know how it goes. My best advice would be to contact someone who knows ViewLogic and see if they can find a way for you to initialize the unknown states. I doubt if you'll get any solution from Actel, as you have said, the part will work regardless of initialization state. Best Luck. John Noll jnoll@su19bb.ess.harris.comArticle: 594
We are about to get into FPGA design and would like to be able to use both schematic entry (OrCAD on a PC) and VHDL. We like SGI workstations, and would not want to migrate to Sun or HP for our other work, so we'd be very interested in tools that run on SGI machines, at least for the compute-intensive part of the design process (we could live with transferring netlists from the PC). Is this a pipe dream ? Thanks. -- Rainer Malzbender Senior Research Physicist Displaytech, Inc. 2200 Central Ave. Boulder, CO 80301 rainer@sdisplay.com rainer@colorado.eduArticle: 595
In Article <D2D9xq.MHt@news.ess.harris.com> jnoll@su19bb.ess.harris.com (John Noll) writes: > >In article mk@newsbf02.news.aol.com, med440@aol.com (Med440) writes: >>... has fallen into my hands, and my very limited FPGA experience has already >> gotten me into trouble -- here goes: Many of the flip-flops in the >> current design do not have any reset/preset. Because of this, predicting >> the state at power-on is impossible, as is generating the >> "print-on-change" type data required. I don't think the lack of a master >> reset(or any reset) is a real problem from a design standpoint, as most of >> the FFs without resets are in clock-divider chains where state is not >> really an issue -- it's only from a simulation standpoint that this is >> troublesome. >> > >For what it's worth, I'm currently experiencing the same problem. I'm designing >two Actel 1280A's using the Cadence tools and Rapidsim. The problem is the same. >I have found that if you run the simulation long enough, sometimes the unknowns get >resolved (sometimes not) also you might try checking to see of your simulator will >allow you to initialize gates (I can initialize them to all 0, all 1, postive logic >state, or negative state). No method I have found is easy or works every time. I >have always been succesful at resolving this problem by trial and error when doing >functional simulation. HOWEVER, when doing back annotated timing simulation I have >had less luck. I am at this very moment waiting for my design to load to see if >my next attempt will work. I'll let you know how it goes. My best advice would be >to contact someone who knows ViewLogic and see if they can find a way for you to >initialize the unknown states. I doubt if you'll get any solution from Actel, as you >have said, the part will work regardless of initialization state. > >Best Luck. > >John Noll jnoll@su19bb.ess.harris.com > I see this quite a bit since I usually don't use the async sets and clears and use a synchronous reset only where it is essential. The way I usually get around this is by defining a vector containing the D inputs to the flops which do not become known after your reset. At the beginning of simulation, assign that vector to zero (or some other value) for one clock cycle then release the vector. This has the effect I believe you are looking for. The viewlogic sim command file would contain something like: v init <list of flops> a init 0 c r init You will also want to make sure that your circuit really will start up from a random state. If need be, you can simulate that by assigning different values to the init vector. Hope this helps, Ray Andraka the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 email randraka@ids.net The Andraka Consulting Group is is digital design firm specializing in getting the maximum performance from FPGAs. Services include complete design, development, simulation and integration of these devices. We also evaluate, troubleshoot and improve existing designs.Article: 596
To be more clear on the subject, the ASIC vendor does *not* want simulation files. The ASIC vendor wants fault test patterns to verify that the devices were built correctly. Simulation is what the designer does in the privacy of his/her "home" to verify that the *design* is correct. Fault testing is done by the foundry to verify that the parts are *built* correctly. By definition, any parts that correctly pass the test pattern you give the foundry are good enough for you to buy, whether or not they work in your circuit. In sum, fault pattern generation and simulation pattern generation are very different problems. regards, Bob Elkind, Tektronix TV Products, bobe@tv.tv.tek.comArticle: 597
dh@fncrd7.fnal.gov (don husby) writes (heavily edited! -- BE):
>The local Xilinx guy left a Xilinx brochure on my desk this morning
>titled: "Xilinx 4000 vs. AT&T ORCA FPGAs: A feature comparison."
<snip>
>The truthful comparison of logic capacity per CLB/PFU is:
>=========================================================================
> X4000 ORCA 2C
>Fully covered functions: 5-bits 6-bits
> 1 independent FF 4 independent usable FF
^
| I think this is 2 independent FFs,
| depending on your definition of the term
>Partially covered functions: 9-bits + 1 ind. FF 11-bits + 4 ind. FF
^
| again, I think this is 2!
>RAM capacity: 16x2 16x4
>RAM capacity: 32x1 32x2
>
>Plus ORCA has payed attention to making single PFU implementation of other
>functions:
>
>X4000 ORCA 2C
>-----------------
>2 CLB 1 PFU Quad 2-1 multiplexer.
>2 CLB 1 PFU Dual 4-1 mux with registered output. (ORCA uses a trick).
> Each flip-flop has a multiplexed input that can select either
> the function generator or a direct input. In addition to
> extending the logic capability for registered functions, this
> is intended to be used to create loadable counters:
>4 CLB? 1 PFU 4-bit loadable up/down counter with synchronous reset.
^
| I believe this can be implemented with 2 CLBs, 2 bits per CLB, using the
| fast carry and add/sub control features. You may have to do a bit of
| manual, custom macro layout work to do it, but that's life.
<more snipped>
>Final note:
> Xilinx also compares its software to AT&T's develompment system. When I
>called the local AT&T sales office, they recommended that I get NeoCad. They
>admit that NeoCad has more experience at this kind of software. I've just
>purchased a NeoCad system and find it superior in many ways (but not all) to
>Xilinx.
I believe that ATT no longer offers a proprietary tool set. I believe that
NeoCad is now the sole official vendor for Orca back-end tools. I believe
that ATT recently made this decision (last half of 1994?) and that it's a
very good move on their part. I've done work with both Orca and Xilinx
(4K/3K) devices and toolsets, and I'm convinced that the hardware vendors
should leave the immense problem of SW toolset to a dedicated EECAD SW
vendor.
NeoCad has a good reputation, and they support Xilinx, Moto, and ATT/Orca
FPGAs with back-end (place/route/manual layout) tools.
<balance snipped>
Bob Elkind, Tektronix TV Products, bobe@tv.tv.tek.com
Article: 598weathert@ee.umr.edu (Terry Chevalier) writes: > I am currently designing a board that is using both 240 pin and >208 pin quadflat pack packages for the 4013 and 4010 xilinx chips >respectively. My problem is finding specifications for the design of >the footprint of these chips. <snip> >If anyone could point me to reference material to design the pads for >these chips I would appreciate the time spent. >William Eatherton The latest Xilinx data book, 1994 *second edition*, contains all the info you need, including the PCB pad layout dimensions, etc. The previous 1994 data book had all the package info, but *not* the PCB footprint info. Also, the first 1994 databook has a note about "cavity up or cavity down" in the packaging section. There, it says that the ceramic quad flatpak packages are all constructed "cavity down" to maximise heat flow from the die to ambient air. Make sure you understand that *ceramic* quad flatpak does not equal *metal* quad flatpak, and all the metal quads are indeed cavity *up*. The largest 4K devices are not available in any sort of cavity down (thermally better) surface mountable package. I don't work/speak for Xilinx, I'm just a customer, and my opinions should be subject to verification. Bob Elkind, Tektronix TV Products, bobe@tv.tv.tek.comArticle: 599
>sometimes the unknowns get resolved (sometimes not) also you might try >checking to see of your simulator will allow you to initialize gates (I can >initialize them to all 0, all 1, postive logic state, or negative state). I think that the real problem that the original poster is having is that because the flip-flops don't have resets, the device doesn't have predictable outputs after reset, and so he can't generate test vectors for the semi-custom fab line. My only suggestion is to go back to the original design and put in some resets - enough so that you can guarantee known outputs after some number of clocks. If there isn't a spare input pin available for reset, maybe you could use a combination of inputs to recognize a reset (for example, if there were separate read and write enable inputs, having both asserted simultaneously could be decoded as a reset). -- +===============================================================+ + Joe Samson (313) 994-1200 x2878 + + Research Engineer, ERIM + + P.O. Box 134001 email samson@erim.org + + Ann Arbor, MI 48113-4001 + +===============================================================+
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