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Just When You thought It Was Safe To Go On Vacation
HOT CHIPS SYMPOSIUM VI
A Symposium on High-Performance Chips
(Advance Program)
Sponsored by the IEEE Computer Society
Technical Committee on Microprocessors
Stanford University, Palo, Alto, California
Memorial Auditorium
August 14-16, 1994
Attend HOT Chips VI, a symposium on high-performance chips, which will bring
together researchers and developers of chips used to construct high-performance
workstations and systems. Enjoy the informal format offering interaction with
speakers. The first five HOT Chips Symposiums were huge successes and prompted
articles in five special issues of IEEE Micro magazine. This year's HOT Chips
VI will again bring you the latest developments in chip technology.
ORGANIZING COMMITTEE
General Chairman: John Mashey, Silicon Graphics
Vice Chairman: Nam Ling, Santa Clara University
Program Co-Chairmen: Alan J. Smith, UC Berkeley
Don Alpert, Intel
Finance Chairman: Dennis Reinhardt, Intel
Registration Chairman: Robert Stewart, Stewart Research
Publication Chairman: David Gustavson, SCI Technical Consortium
Publicity Chairman: S. Diane Smith, Consultant
Local Arrangements Chairmen: Alan Johnson,
Cary Kornfeld, Interval Research
Tutorials Chairman: Qiang Li Santa Clara University
At Large: Martin Freeman, Philips Research
John Hennessy, Stanford University
PROGRAM COMMITTEE
Donald Alpert, Intel (Program Co-Chairman)
Forest Baskett, Silicon Graphics
Alan Baum, Apple Computer
Anoop Gupta, Stanford University
Norman Jouppi DEC WRL
Ruby Lee, Hewlett Packard
Alan J. Smith, UC Berkeley (Program Co-Chairman)
PROGRAM
August 14, 1994
Tutorial Schedule:
7:30-8:30 Registration & Coffee at Memorial Auditorium
8:30-12:00 Algorithms & Hardware for Video Compression
12:00-1:00 Lunch
1:00-4:30 Instruction-Set Extension for Multiprocessor Interconnects
4:30-6:00 Wine & Cheese Reception in the Dohrman Grove
Just North of the Hoover Tower on Serra Street
Tutorial 1: Algorithms & Hardware for Video Compression
Teresa Meng, Stanford University
This tutorial will give an overview of the industry standards for video
compression, including compression algorithms, performance comparisons
and hardware implementations. Fast algorithms to achieve real-time
encoding and decoding will be one focus of this tutorial. Besides
industry standards, recent developments in compression techniuqes, such
as subband and wavelet filtering and vector quantization will be
covered. Finally research activities in the area of low-power
implementations for portable video applications will be surveyed.
Tutorial 2: Instruction-Set Extensions for Multiprocessor Interconnects
David James, Apple Computer
Most instruction sets have been optimized for uniprocessor
environments. To effectively utilize multiprocessors on scalable
interconnects, processors need to support additional capabilities,
including 64-bit addressing, a well-defined set of memory access
capabilities (loads, stores, and locks), non-blocking interrupts and
synchronized time-of-day clocks. As background, the constraints of a
typical high-speed interconnect, ANSI/IEEE Std 1596-1992 Scalable
Coherent Interface (SCI), are considered. We show that specialized
signals (such as bus-lock and interrupt) as well as eavesdrop or
broadcast-based protocols can be avoided, explicit lock instructions
(such as fetch&add) scale better than LoadReserved- and
StoreConditional-based instruction sequences, and mixed endian data
types (big and little) require minimal hardware (but significant
compiler) support. We show how these conditions impact the design of
processor instruction-set extensions.
August 15, 1994
9:00-9:15 Welcome and Opening Remarks
John Mashey, General Chair
Don Alpert, Alan Jay Smith, Program Co-Chairs
9:15-10:45 CPUs - 1
Session Chair: Norman Jouppi, DEC WRL
. An Overview of the 21164 Alpha AXP Microprocessor
Paul Rubinfeld, Digital Equipment Corp.
. The Power2+ Processor
David Shippy, IBM
. A 500MHz 32b 0.4um CMOS RISC Processor (Gallop)
Kazumasa Suzuki, NEC Corporation
10:45-11:15 Break
11:15-12:45 Multiprocessor and Encryption
Session Chair: Howard Sachs, Sun Microsystems
. The Alewife CMMU: Addressing the Multiprocessor
Communications Gap
John Kubiatowicz, MIT
. nCube3 Integrated MPP Node Processor
Robert Duzett, nCube
. A 100Kbit/sec Single Chip Modular Exponentiation Processor
Holger Orup, Aarhus University, Denmark
12:45-2:15 Lunch
2:15-3:45 Networks, Communications
Session Chair: Forest Baskett, Silicon Graphics
. UAI2110: An Universal GaAs ATM Interface Chip
for High Speed Networks
Premysl Vaclavik, Thomas Neuroth GmbH, Austria
. A 500 MHz BiCMOS GByte/Second SCI-Link Implementation
Wayne Nation, IBM
. The STC104 Asynchronous Packet Switch
Peter Thompson, INMOS Ltd.
3:45-4:30 Break
4:30-5:30 CPUs - 2
Session Chair: Don Alpert, Intel
. The New i960 CPU that offers More for Less, the P100
Richard Brunner/Deif Atallah, Intel
. SH-II- A Low Power RISC Micro for Consumer Applications
Shumpei Kawasaki, Hitachi
5:30-7:30 Buffet Dinner
7:00-9:00 Evening Panel Session
The Investor (Venture) Community View of What's Hot
Moderator: Forest Baskett, Silicon Graphics
Panelists: Cliff Friedman, Bear Stearns
Stephen Shapiro, Tiger Management
Peter Thomas, Institutional Venture Partners
August 16, 1994:
9:00-10:00 Chipsets
Session Chair: Allen Baum, Apple Computer
. 82430NX PCIset: Companion to the Highest
Performance Pentium Processor
Patrick Correia, Intel Corporation
. A Power PC/PCI Bridge Chip with a
Cache and Memory Controller
Karl Wang, Motorola, Inc.
10:00-10:30 Break
10:30-12:30 Graphics
Session Chair: Ruby Lee, Hewlett Packard
. An ASIC for Interactive 3D Graphics
Stephanie Winner, Apple Computer Inc.
. GLiNT - a 3D Graphiucs Processor Based on the OpenGL Standard
Neil Trevett, DuPont Pixel
. The Smart Frame Buffer Goes Hollywood: 3D and TV
Joel McCormack, Digital Equipment Corporation
. A Cached VRAM for 3D Graphics
Michael Deering, SUN Microsystems
12:30-2:00 Lunch
2:00-3:30 Video
Session Chair: Anoop Gupta, Stanford University
. Video Compression Processor for H.320-to-Indeo Transcoding
Bryan Martin, Integrated Information Technology
. A High Performance Programmable Multi-Standard
Video Compression Chip Set
David Still, Array Microsystems Inc.
. Multimedia Enhancements for PA-RISC Processors
Ruby Lee, Hewlett-Packard
3:30-4:00 Break
4:00-6:00 CPUs - 3
Session Chair: Alan J. Smith, UC Berkeley
. PowerPC 604
Marvin Denman, IBM
. The Thunder SPARC Processor
Bruce Lightner, Metaflow Technologies Inc.
. The Superscalar Hardware Architecture of the MC68060
Joe Circello, Motorola
. A High Performance, Low Power, Pentium Processor
Doug Carmean, Lawrence Clark, Robert Rozploch, Intel
6:00 Closing Remarks
HOUSING INFORMATION
Housing is available on the Stanford University campus in student
dormatories which are vacant in the summer. These have central lavatory
facilities and cost about $40 per night --- single, $50 per night ---
double, for the nights of the symposium. A key deposit of $50 is
required that will be refunded at checkout. Housing arrangements on the
Stanford campus must be made by August 4 through HOT Chips, not
Stanford.
Housing is also available at numerous hotels and motels on the
peninsula in Palo Alto, Menlo Park, Mountain View, and Los Altos within
5 miles of the campus. You are responsible for making such reservations
directly with the motel.
If you would like additional housing information, please check the housing
information request box on the registration form.
IEEE/Computer Society Membership
To join call John Gill at (202) 371-0101. With confirmation, you may
register for HOT Chips VI at member rates.
QUESTIONS?
For more information on registration and local arrangements contact Dr.
Robert Stewart at (415) 941-6699 or r.stewart@compmail.com.
REGISTRATION INCLUDES:
* Attendance * Sunday Evening Wine &
* One Copy of the Notes Cheese Reception
* Two Luncheons * Monday Evening Reception
* Coffee Breaks * Parking
A Stanford map, parking permit, the location of parking, and a receipt
will be mailed to early registrants.
ON-SITE REGISTRATION is available Sunday morning before the tutorial
and each morning at the Symposium. Early advanced registration is
recommended because of the large attendance.
Group discounts are available.
CANCELLATION OF REGISTRATION: Must be made in writing prior to Sunday,
August 7, 1994. A $40 fee will be charged for cancellation.
FEDERAL TAX ID NUMBER IS: 13-1656633 for the
Institute of Electrical & Electronic Engineers
345 E. 47th Street
New York, NY 10017
Use certified mail for registration confirmation.
=============================================================================
HOT CHIPS VI REGISTRATION FORM
Name________________________________________________________________________
Organization________________________________________________________________
Dept/Mail Stop______________________________________________________________
Mailing Address_____________________________________________________________
City/State/Zip______________________________________________________________
Country_____________________________________________________________________
Area Code/Phone #___________________________________________________________
Email Address_______________________________________________________________
FAX_________________________________________________________________________
Membership: IEEE/CS______ ACM_______
Student______ None______
Society Membership Number___________________________________________________
Check One:
______Check drawn on a U.S. Bank ______MasterCard
Make Check Payable To:
Hot Chips Symposium ______VISA
Name on Credit Card_________________________________________________________
Credit Card #_______________________________________________________________
Expiration Date_____________________________________________________________
Signature___________________________________________________________________
FEES: CIRCLE APPROPRIATE VALUES
IEEE/Computer Society $230
or ACM Member
Non-Member $290
Student Member $100
Sunday Tutorials, Member $45
Tutorials, Non-Member $60
Tutorials, Student $30
Extra Copy of Notebook $30
(with no mailing)
Stanford University Dormitory Housing
______ nights @$40 per night single; $50 double $_________
Arrival__________________ Departure___________________
TOTAL AMOUNT PAID ______________
Electronic Registration, paid via VISA or Mastercard Registration:
FAX: (415) 941-5048
EMAIL: r.stewart@compmail.com
Surface Mail Registration To:
Dr. Robert G. Stewart
Stewart Research Enterprises
1658 Belvoir Drive
Los Altos, CA 94024
Do NOT put me on the Hot Chips Mailing List _____
Stanford University Housing Information Requested _____
Article: 26In article <316qf6INN5o2@sun004.cpdsc.COM> cshelor@cpdsc.com (Charles Shelor-Consultant) writes: >Welcome to the new Xilinx users: >Get ready to spend a lot more time doing place and route than you >EVER anticipated if you are using XC4010 or larger. >Best bet, skip the Xilinx PPR software and get NeoCad! Tell me more about NeoCad. We have a project on an XC4010 that takes 4 hours to place and route on a Sparc 10/51 with 96 megs of RAM. I sure would like to hear about any alternatives to PPR!!Article: 27
Please feel free to rebroadcast this announcement to any interested groups.
One Day Xilinx Summer Workshop
"Field Programmable Gate Arrays in the Classroom"
Workshop 1 (Viewlogic Based)
Date: Friday, August 12
Location: Painter 3.20 (Dell Lab)
University of Texas at Austin
Austin, Texas
Workshop 2 (Mentor Based)
Date: Monday, August 15
Location: University of Notre Dame
Notre Dame, Indiana
Workshop 3 (Mentor Based)
Date: Thursday, August 18
Location: Colorado State University
Fort Collins, Colorado
The Xilinx University Program will be holding several
regional one-day "hands-on" workshops in August to
introduce university faculty, staff, and graduate
students to Field Programmable Gate Arrays as a learning
tool in Digital Design courses. The goal of the workshop
is to provide the information and assistance necessary to
develop and conduct or enhance undergraduate courses in
Digital Design using FPGAs. This intensive one day
workshop will allow a forum for gathering information and
provide first hand experience with industry CAE and FPGA
implementation tools. The hands-on labs are structured
so the students will perform the entire design flow and
see it working in a prototyping board.
FPGAs are not just for Digital Design courses. Many
universities have utilized the technology for courses
in computer architecture, senior research projects, VLSI
design, and ASIC design. The flexibility of the
architecture, reprogrammability of the devices, and the
simplicity of the design tools makes Xilinx FPGAs ideal
for the university environment. An instructor can guide
their students through an entire design entry, implementation,
and simulation process and download results directly into
silicon on the desktop. New features in the XACT 5.0 software
will be covered.
The workshops will be free of charge. A complimentary
continental breakfast and lunch will be served on premises.
An information packet will be sent to you by Stacey Pinckert
of Xilinx. The packet will include directions to the university
and a list of lodges in the area. Applications are due two days
before the workshop date.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Topics:
Various ways to use Xilinx
Xilinx Design Environment
Automatic Tools
XC4000 Architecture
Design Entry Methods
FPGA Implementation
New XACT 5.0 Features
BORG Prototyping Board
Xilinx University Program
Q&A Session
Format:
Begins - 9:00am
Ends - 5:00pm
* Labs will remain open after 5:00pm
AM - Lecture (See Topics Section)
PM - Hands-on
* Design Entry
* Implementation
* Simulation
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
EMAIL APPLICATION FORM
One Day Xilinx Summer Workshop
"Field Programmable Gate Arrays in the Classroom"
Which workshop do you wish to attend? __________
Name: _________________________________________
Title: ________________________________________
University: ____________________________________
Department: ____________________________________
Address: _______________________________________
Address: _______________________________________
Tel: ___________________________________________
Fax: ___________________________________________
Email: _________________________________________
Presently using FPGAs in course work? Yes____ No____
If yes, is it from Xilinx? Yes____ No____
Are you planning on using FPGAs in your course? Yes____ No ____
Will your University support the use of FPGAs? Yes____ No____
Which design entry tool are you familiar with? _______________
*** Please send your completed application to:
Stacey Pinckert
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Tel: 408-879-5150
Fax: 408-879-4676
Email: stacey@xilinx.com
*** For more information on the Workshop Contact
David Lam
Xilinx University
2100 Logic Drive
San Jose, CA 95030
(T) 408-879-4961
(F) 408-879-4676
Email: dlam@xilinx.com
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 28Since some body asked, I'll respond. We are offering a new book which teaches digital logic design using the Intel/Altera FLEXlogic FPGA. The book shows how to build a FPGA prototyping board for about $100 and then uses the board to build combinatorial logic, state machines, and a 4-bit microcomputer. A completely-assembled 4'' x 2'' circuit board is also available for those who want to get started quickly. Several of these boards can be concatenated to build multi-FPGA systems. The book and board use the Intel PLDshell software for programming, and PLDshell is available free from Intel either as floppy disks or from several FTP sites. For a more complete description of these products, send e-mail to devb@vnet.net with the subject line of "fpga". -- || Dave Van den Bout || || Xess Corporation ||Article: 29
richw@lsid.hp.com (Rich Wilson) writes: >I found their support (via internet Email) to be very >rapid and helpful. We must have trained them! We begged for an internet address & we were refused! There were a few issues regarding the iFX780 which the phoneline tech support people hadn't been briefed at all. Glad your experience was a better one. After we got the problems worked out they have worked very good. Cheers, Bob -- <> Bob "Bear" Geer <> <> <> bgeer@xmission.com <> Even paranoids <> <> Salt Lake City, <> have enemies, too! <> <> Utah, USA <> <>Article: 30
I'm interested in finding descriptions of the file formats used by Xilinx and NEOCad. Are these published anywhere? Has anyone reverse-engineered them? The reason I ask is that the company I work for uses Xilinx parts a lot but the placement and routing is a major bottleneck in the design process. I'd like to experiment with some placement and routing methods of my own but I need to read these files to do it. Thanks, David Wheeler wheelerd@clark.netArticle: 31
Hi, Just how expensive is FPGA development? Is it at all possible for an individual to purchase the necessary software/hardware to use high density devices for example at a reasonable cost? I have looked at some vendors such as Lattice and Intel. The Intel SW is quite nice as it allows device independent design, something which the Lattice pLSi sw doesn't seem to do. However these vendors seem to be making a good effort to get their products into the hands of individuals at a reasonable cost. Do I really need to purchase several hundred pounds worth of software to even consider looking at the high density FPGAs? A simple functional design tool would suit me fine, it doesn't have to be fast or Windows based. Any advice appreciated. Best Regards, Roger -- ----------------------------------------------------------------------------- Roger Kinkead EMAIL: roger@rkhost.demon.co.uk "Moorcroft", 27 Antrim Road, Lisburn,County Antrim, Northern Ireland -----------------------------------------------------------------------------Article: 32
In article <775585746snz@rkhost.demon.co.uk>, Roger Kinkead <roger@rkhost.demon.co.uk> wrote: >Hi, > >Just how expensive is FPGA development? Is it at all possible for an individual >to purchase the necessary software/hardware to use high density devices for >example at a reasonable cost? > Hmm... I remember about ~12 years ago I would get Fortran source code for Palasm from MMI; thats right, joe user had to compile the stuff himself - I even added a few routines to create nroff data sheets that would become 'unix-like' man pages. Those were the days... Now we have companies like Xilinx, Actel, etc; these guys are really software companies - Xilinx and Actel will even tell you so if you have the chance to talk to some of there high level engineering folks. --- I wonder why the PC based tools are cheaper than the Unix tools. In the past the argument was that Unix was multi-tasking, therefore you could 'do more' than with a PC running DOS. Five years ago with the home brew Unix license mechanisms of these vendors this was true; today with Highland Digital you can restrict all the way down to a single task per node. What gives? -- /* Mark A. Indovina, mark_indovina@pts.mot.com */ /* Motorola, Inc., Applied Research, Advanced IC Technology Laboratory */ /* Mail Stop 63, 1500 Gateway Avenue, Boynton Beach, FL 33436-8292 USA */ /* phone, 1-407-364-2379, fax, 1-407-364-3904 */Article: 33
Arnim Littek (arnim@actrix.gen.nz) wrote: : the situation. Xilinx seems to be moving away from ASCII outputs, : and NeoCAD has never been that open, as far as I know. However, : that's another issue altogether. I don't think that this is true. All my intermediate files are ASCII. I can't even find a "convert to binary" converter. I'm using XACT 5.0. Roger. -- * As a protest against the recent bunch proposed anti-cryptography * * laws, this message has been doubly encrypted using the rot13 algorithm. * EMail: wolff@dutecai.et.tudelft.nl ** Tel +31-15-783643 or +31-15-142371Article: 34
In article 3809@krabat.marco.de, frank@krabat.marco.de (frank) writes:
>We were thinking of using the flexlogic chips here, but
>now that Intel is apparently selling all its PLD and flexlogic business
>to Altera, who knows what the future for these chips is. Anybody know
>and like to comment?
>
I have included the press release about the sale at the end of this
article. You can read it for yourself. Altera will acquire this
business on October 1, pending government approval. Until then,
we are definitely here doing our jobs.
The PLDshell software is available, for free, at
ftp.intel.com:/pub/pld_fpga/software/dos/pldshell.zip
(about 2 Megabytes to download)
As for the book "FPGA Workout", the designs are available in
ftp.intel.com:/pub/pld_fpga/designs/fpga-workbook/fpga-wor.zip
-or- ftp.intel.com:/pub/pld_fpga/designs/fpga-workbook/fpga-workout.tar
An order form for the book and board is a Postscript file in
ftp.intel.com:/pub/pld_fpga/designs/fpga-workbook/orderform.ps
You can call Xess Corp. at 800-549-XESS (USA) or email to dev@vnet.net for
more information.
--Richard Vireday
Intel PLD & FPGA Business Unit
================= ftp.intel.com:/pub/pld_fpga/press/sold =====================
OTC 07/12 1622 Altera to acquire Intel programmable logic business
SAN JOSE, CALIF. (JULY 12) BUSINESS WIRE - July 12, 1994--Altera Corp.
(NASDAQ:ALTR) announced Tuesday that it will acquire Intel Corp.'s
programmable logic business for a price of approximately $50 million.
The purchase price consists of $25 million in cash and 779,277 shares of
Altera common stock, subject to certain post-closing adjustments. The
transaction is expected to be completed on Oct. 1, subject to governmental
approval. Immediately after the closing, Robert Reed, senior vice
president and general manager of Intel's Semiconductor Products Group, is
expected to join Altera's board of directors.
The relationship between the two companies dates back to 1984 when
Altera licensed Intel to Altera's first family of products in exchange for
process technology and wafer manufacturing services.
"Intel is the premier semiconductor company in the world. Our
partnership with Intel played a significant role in Altera's early
development and we look forward to continuing our relationship with Bob
Reed on our board of directors, " said Rodney Smith, president, chief
executive officer, and chairman of Altera Corp.
As part of the sale, Altera will receive Intel PLD products and licenses
to use associated process technologies and intellectual property to build
PLD products. In addition, Intel agrees to supply wafers to Altera in
support of the business.
"Altera is a recognized leader in the programmable logic market. Intel's
investment in Altera allows Intel to share in the continued growth and
development of the PLD market and to realize the best possible return on
its prior investment in this business. I will work actively with Altera to
ensure a smooth transition for Intel customers," according to Reed of
Intel. The two companies are each planning to prepare customers for the
transition of the products to Altera by Oct. 1.
Employee transfers are not included in the transaction. However, Altera,
at its discretion, may make employment offers to any of Intel's current PLD
employees.
Altera pioneered the high density PLD market which remains one of
today's fastest growing semiconductor areas. The addition of the Intel
products complements Altera's broad range of programmable logic solutions.
Software support will continue to be provided by Altera through Intel's
PLDshell product and will be added into Altera's MAX+PLUS II software in
the future.
The Intel product line consists of 15 devices ranging from the popular
22V10 to the recently introduced FLEXlogic line. FLEXlogic contains
several unique features compared to other high density programmable logic
devices on the market and complements Altera's industry leading MAX 7000
and FLEX 8000 families.
About Altera
Altera Corp., founded in 1983, is a worldwide leader in
high-performance, high-density programmable logic devices and associated
computer aided engineering (CAE) logic development tools. Programmable
logic devices are semiconductor chips that offer on-site programmability to
customers. The chips are programmed using tools that run on personal
computers or engineering workstations.
User benefits include ease of use, lower risk, and fast time-to-market.
The company offers the broadest line of CMOS programmable logic devices
that address high-speed, high-density and low-power applications. Altera
products serve a broad range of market areas, including telecommunications,
data communications, computers, and industrial applications.
About Intel
Intel, the world's largest chip maker, is also a leading manufacturer of
personal computer, networking and communications products.
-0-
NOTE TO EDITORS: Altera, MAX, and FLEX are registered trademarks, and
MAX 7000, FLEX 8000, and specific device designations are trademarks of
Altera Corp.
--30--ahc/sf cs/sf
CONTACT: Altera Corp., San Jose
Erik Cleage or Robert K. Beachler, 408/894-7000
Intel Corp.
Larry Palley or Janet Woodworth, 916/356-6653
Franson, Hagerty and Associates
Susan Cain, 415/462-1605
KEYWORD: CALIFORNIA
INDUSTRY KEYWORD: COMPUTERS/ELECTRONICS COMED
TELECOMMUNICATIONS MANUFACTURING
MERGERS/ACQ MANAGEMENT CHANGES Z REPEATS: New York
212-575-8822 or 800-221-2462; Boston 617-330-5311 or 800-225-2030; SF
415-986-4422 or 800-227-0845; LA 310-820-9473
Article: 35> I wonder why the PC based tools are cheaper than the Unix tools. I've always thought it was the perception that those people/groups running UNIX workstations had more money and thus would be able to pay more. -GeorgeArticle: 36
Charles F. Shelor writes: >Welcome to the new Xilinx users: >Get ready to spend a lot more time doing place and route than you >EVER anticipated if you are using XC4010 or larger. >Best bet, skip the Xilinx PPR software and get NeoCad! Yeah. I heard through the grapevine that it may take up to a day to coplete a compilation of Xilinx designs before you can program silicon. But of course this is unconfirmed hearsay and I have not worked w/ the Xilinx design tools. I have heard about NeoCad. I thought it was only a design capture and sim tool. Does it compile designs for target FPGAs as well? John _____________________ All opinions are my own and not those of TI.Article: 37
Hi Everybody,
The following is a list of articles and references for FPGA based designs. I would like to thank all of you who replied to my "by-now-forgotten" posting on request for references on FPGA based designs. I have found most of the references. I havent particulary paid any attention to the periodicals so i
maniar@charlie.ece.scarolina.edu
and i will post a continuation of this posting.
Prashant.
~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~THE FUTURE BELONGS TO THOSE WHO BELIEVE IN THE BEAUTY OF THEIR DREAMS !!!~
~ ~
~ \\|// PRASHANT B. MANIAR ~
~ (o|o) email : maniar@charlie.ece.scarolina.edu ~
~-----ooO-~-Ooo------- ~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Literature Survey for FPGA based Design's.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1> Electronic design ( periodical )
2> Computer Design
3> ASIC and EDA ( magazine )
4> ISSCC proceedings ( what does ISSCC stand for...never heard of it ) ( has details on latest FPGA semiconductor processes and some information on architecture trends.)
5>
% DPGA Related Reference Collection
%
i> http://www.ai.mit.edu/projects/transit/tn95/tn95.html
ftp://transit.ai.mit.edu/transit-notes/tn95.ps.Z
Transit Note #95
Unifying FPGAs and SIMD Arrays
Michael Bolotski, Andre DeHon, and Thomas F. Knight, Jr.
Original Issue: September, 1993
ii> http://www.ai.mit.edu/projects/transit/tn100/tn100.html
ftp://transit.ai.mit.edu/transit-notes/tn100.ps.Z
Transit Note #100
DPGA-Coupled Microprocessors:
Commodity ICs for the Early 21st Century
Andre DeHon
Original Issue: January, 1994
@INPROCEEDINGS{asic_microprocessors,
AUTHOR = {M. J. Flynn and R. I. Winner},
TITLE = {ASIC Microprocessors},
BOOKTITLE = {Proceedings of the 22nd Annual Workshop on Microprogramming and Microarchitecture},
YEAR = {1989},
PAGES = {237-243},
ORGANIZATION = {ACM},
PUBLISHER = {ACM Press},
MONTH = {August}
}
@PROCEEDINGS{fccm93,
TITLE = {Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines},
YEAR = {1993},
EDITOR = {Duncan A. Buell and Kenneth L. Pocek},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {April}
}
@ARTICLE{prism_computer93,
AUTHOR = {Harvey F. Silverman},
TITLE = {Processor Reconfiguration Through Instruction-Set Metamorphosis},
JOURNAL = {IEEE Computer},
YEAR = {1993},
VOLUME = {26},
NUMBER = {3},
PAGES = {11--18},
MONTH = {March}
}
@INPROCEEDINGS{prism2_fccm93,
AUTHOR = {M. Wazlowski and L. Agarwal and T. Lee and A. Smith and E. Lam and P. Athanas and H. SIlverman and S. Ghosh},
TITLE = {PRISM-II Compiler and Architecture},
BOOKTITLE = {Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines},
YEAR = {1993},
EDITOR = {Duncan A. Buell and Kenneth L. Pocek},
PAGES = {9--16},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {April}
}
@INPROCEEDINGS{cm2x_fccm93,
AUTHOR = {Steven A. Cuccaro and Craig F. Reese},
TITLE = {The CM-2X: A Hybrid CM-2/Xilinx Prototype},
BOOKTITLE = {Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines},
YEAR = {1993},
EDITOR = {Duncan A. Buell and Kenneth L. Pocek},
PAGES = {121--130},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {April}
}
@INPROCEEDINGS{splash,
AUTHOR = {M. Gokhale, et. al.},
TITLE = {SPLASH: A Reconfigurable Linear Logic Array},
BOOKTITLE = {Proceedings of the International Conference on Parallel Processing},
YEAR = {1990},
PAGES = {526--532},
MONTH = {August}
}
@TECHREPORT{splash2,
AUTHOR = {D. A. Buell},
TITLE = {A Splash~2 Tutorial},
INSTITUTION = {Supercomputing Research Center},
YEAR = {1992},
TYPE = {Technical Report},
NUMBER = {SRC-TR-92-087},
ADDRESS = {Bowie, Maryland},
MONTH = {December}
}
@TECHREPORT{pam_intro,
AUTHOR = {Patrice Bertin and Didier Roncin and Jean Vuillemin},
TITLE = {Introduction to Programmable Active Memories},
INSTITUTION = {DEC Paris Reserch Laboratory},
YEAR = {1989},
TYPE = {PRL Report},
NUMBER = {3},
ADDRESS = {85, Av. Victor Hugo, 92563 Rueil-Malmaison Cedex, France},
MONTH = {June}
}
@MANUAL{algotronix_cal1024,
TITLE = {The Configurable Logic Data Book},
ORGANIZATION = {Algotronix Ltd.},
ADDRESS = {Edinburgh, UK},
YEAR = {1990}
}
@MANUAL{xilinx,
TITLE = {The Programmable Gate Array Databook},
ORGANIZATION = {Xilinx, Inc.},
ADDRESS = {2100 Logic Drive, San Jose, CA 95124},
YEAR = {1989}
}
@INPROCEEDINGS{furtek_fccm93,
AUTHOR = {Frederick Furtek},
TITLE = {Arithmetic Benchmarks for the CLi6000},
BOOKTITLE = {Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines},
YEAR = {1993},
EDITOR = {Duncan A. Buell and Kenneth L. Pocek},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {April},
Note = {Paper does not appear in printed proceedings; contact author {\tt fred@clogic.com}}
}
%% get full names and issue number for rsa_cacm
%% NUMBER = {},
@ARTICLE{rsa_cacm,
AUTHOR = {R. Rivest and A. Shamir and L. Adleman},
TITLE = {Public Key Cryptography},
JOURNAL = {Communications of the ACM},
YEAR = {1979},
VOLUME = {21},
PAGES = {120-126},
NOTE = {}
}
@INPROCEEDINGS{pam_rsa,
AUTHOR = {M. Shand and J. Vuillemin},
TITLE = {Fast Implementations of RSA Cryptography},
BOOKTITLE = {Proceedings of the 11th Symposium on Computer Arithmetic},
YEAR = {1993},
EDITOR = {Earl {Swartzlander Jr.} and Mary Jane Irwin and Graham Julien},
PAGES = {252--259},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {June}
}
@TECHREPORT{pam_performance_assessment,
AUTHOR = {P. Bertin and D. Roncin and J. Vuillemin},
TITLE = {Programmable Active Memories: A Performance Assessment},
INSTITUTION = {DEC Paris Reserch Laboratory},
YEAR = {1992},
TYPE = {PRL Report},
ADDRESS = {85, Av. Victor Hugo, 92563 Rueil-Malmaison Cedex, France},
MONTH = {June}
}
@INPROCEEDINGS{dzung_splash2_fccm93,
AUTHOR = {Dzung T. Hoang},
TITLE = {Searching Genetic Databases on Splash~2},
BOOKTITLE = {Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines},
YEAR = {1993},
EDITOR = {Duncan A. Buell and Kenneth L. Pocek},
PAGES = {185--191},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {April}
}
@ARTICLE{splash_computer91,
AUTHOR = {Maya Gokhale and William Holmes and Andrew Kopser and Sara Lucas and Ronald Minnich and Douglas Sweely and Daniel Lopresti},
TITLE = {Building and Using a Highly Programmable Logic Array},
JOURNAL = {IEEE Computer},
YEAR = {1991},
VOLUME = {24},
NUMBER = {1},
PAGES = {81--89},
MONTH = {January}
}
@INPROCEEDINGS{lopresti_advvlsi91,
AUTHOR = {Daniel Lopresti},
TITLE = {Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays},
BOOKTITLE = {Advanced Research in VLSI},
YEAR = {1991},
EDITOR = {Carlo H. S\'equin},
PAGES = {138--152},
PUBLISHER = {MIT Press},
ADDRESS = {Cambridge, MA},
MONTH = {April}
}
@INPROCEEDINGS{sorting_on_algotronix_fccm93,
AUTHOR = {Wayne Luk and Vincent Lok and Ian Page},
TITLE = {Hardware Acceleration of Divide-and-Conquer Paradigms: a Case Study},
BOOKTITLE = {Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines},
YEAR = {1993},
EDITOR = {Duncan A. Buell and Kenneth L. Pocek},
PAGES = {192--1201},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {April}
}
@INPROCEEDINGS{dbc_fccm93,
AUTHOR = {Maya Gokhale and Ron Minnich},
TITLE = {FPGA Computing in a Data Parallel C},
BOOKTITLE = {Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines},
YEAR = {1993},
EDITOR = {Duncan A. Buell and Kenneth L. Pocek},
PAGES = {94--101},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {April}
}
@MANUAL{xilinx_product_guide_93,
TITLE = {Product Description and Selection Guide},
ORGANIZATION = {Xilinx, Inc.},
ADDRESS = {2100 Logic Drive, San Jose, CA 95124},
MONTH = {April},
YEAR = {1993}
}
@INPROCEEDINGS{luk-fccm94,
AUTHOR = {Wayne Luk and Teddy Wu and Ian Page},
TITLE = {Hardware-Software Codesign of Multidimensional Programs},
BOOKTITLE = {Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines},
YEAR = {1994},
EDITOR = {Duncan A. Buell and Kenneth L. Pocek},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {April}
}
@INPROCEEDINGS{siu-fccm94,
AUTHOR = {Greg J. Gent and Scott R. Smith and Regina L. Haviland},
TITLE = {An FPGA-based Custom Coprocessor for Automatic Image Segmentation Applications},
BOOKTITLE = {Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines},
YEAR = {1994},
EDITOR = {Duncan A. Buell and Kenneth L. Pocek},
ORGANIZATION = {IEEE Computer Society},
PUBLISHER = {IEEE Computer Society Press},
ADDRESS = {Los Alamitos, California},
MONTH = {April}
}
6>
%% stuff to potentially include
%% ftp.eecg.toronto.edu
%% pub/tech_reports/SteveBrown
%% cicc94.fm.ps.Z
%% phd.ps.tar.Z
%% stochastic.ps.Z
7> August '93 edition of "Journal of VLSI Signal Processing", Special Issue on FPGAs (Kluwer Academic Publishers).
8> Altera's data books.
9> Xilinx data books.
10> A. Wolfe, J.P.Shen, " Flexible Processors : A promising Application Specific Processor Design Approach," Proceedings of MICRO '21.
11> Christian Iseli & Eduardo Sanchez, "Beyond Superscalar Using FPGAs",
IEEE International Conference on Computer Design, Cambridge Mass.,
October 1993.
12> Christian Iseli & Eduardo Sanchez, "Spyder: A SURE (SUperscalar and
REconfigurable) Processor", The Journal of Supercomputing, to be
published in autumn 1994.
13> anon ftp from ftp.inf.ethz.ch
i> Author: N. Wirth, S. Ludwig
Title: An Extension-Board with an FPGA for Experimental Circuit Design
CL - An Editor for the CLi6000 Field Programmable Gate Array
and its Implementation CL-Editor User Manual
Dokument: 198 / 1993
ii> Author: H. Eberle, S. Gehring, S. Ludwig, N. Wirth
Title: Tools for Digital Circuit Design using FPGAs
Document: 215 / 1994
Article: 38In article <Ctv06F.671@pts.mot.com> ep520mi@pts.mot.com (MARK INDOVINA Xxxxx Ppppp) writes: >Now we have companies like Xilinx, Actel, etc; these guys are really >software companies - Xilinx and Actel will even tell you so if you have >the chance to talk to some of there high level engineering folks. I don't agree. These software products look great on the marketing man's papers, but when you really start doing something you'll notice that the tools do just about the minimum, what they have to. Well, some people like to say that a SW product is never ready. And these companies do get their bread from the HW... qru -- lkuru@snakemail.hut.fiArticle: 39
In article <m363Yc.gdZ@asic.sc.ti.com>, jmassoth@asic.sc.ti.com (John Massoth) writes: > > Yeah. I heard through the grapevine that it may take up to > a day to complete a compilation of Xilinx designs before you > can program silicon. But of course this is unconfirmed hearsay > and I have not worked w/ the Xilinx design tools. I have been using Xilinx and ppr for about two years. I have not used any other competing programs, so have no other point of reference. The compilation time of ppr depends very much on how far you are pushing the technology, both in how much of the Xilinx device is being used, and in your speed requirements. I have used devices ranging from a 4005 to a 4010. I run ppr on a SparcStation IPX with clock-doubled CPU. For any of the devices, with up to about 70% utilization of function generators (I tend to use them up first) and about 60% utilization of flip flops, I see from 10 to 15 minutes of ppr time for one run. If you use the path timing capability of ppr (where you can place an upper limit on the time from a flop's output to another flop's input, the time can go up by a factor of three or four. I've tried path timing only once and found it very lacking compared to my usual approach of flagging critical nodes and doing hand placement of flops for time critical portions of the circuit. I have found that if I go over about 75% utilization of function generators, ppr has real problems. I suspect that it is because my circuits don't always fit cleanly into the Xilinx model of four inputs feeding each flop, so the actual resource utilization is much more than 70%. Occasionally ppr will take a long time (30 minutes instead of 10 minutes) when it does a really poor placement. My really time-critical circuits meet the four-input constraint for all time critical flops, and I have completely hand-placed a couple of 4006's to get things to run fast enough. ppr didn't have a chance of meeting my timing requirements without this. All of this is to say that "up to a day" is, in my experience, not close to the truth. Of course, if you need 100 runs to get one with good enough timing, it can easily take a day. Also, getting the first one through the tool set will take a while, just to learn how the tools work. David Eby Tektronix, Inc.Article: 40
Arnim Littek wrote in article <Cto8vK.FzJ@actrix.gen.nz> :
>>
>>cshelor@cpdsc.com writes
>>>Get ready to spend a lot more time doing place and route than you
>>>EVER anticipated if you are using XC4010 or larger.
>>>
>>>Best bet, skip the Xilinx PPR software and get NeoCad!
>>
>>I don't suppose you could be a bit more specific in this case? Have
>>you got some side-by-side examples of the same data being submitted
>>to PPR and to the NeoCAD tools?
>>
>>We are still using the 3K stuff principally, and the APR tool, so I
>>am not willing to comment on the PPR stuff, but in our comparisons,
>>from 2018 devices right through to 3195, there are some patterns.
>>
>>Firstly, the NeoCAD tools are a lot faster than the Xilinx factory
>>tools, by a factor of 3-4 times, particularly on the larger designs.
>>This is based on the APR V3.30 which was in the last pre-XACT5.0
>>release. (Haven't tried with the APR in XACT 5.0) The NeoCAD tools
>>I've tried on are V4.1.
>>
>>However, in defence of APR, it is seems more flexible, allowing
>>us to tailor the placement and routing in ways that the NeoCAD
>>isolates the user from. For that matter, APR also seems to have that
>>all over PPR too. Too bad its being put on the shelf.
>>
>>The trend seems to be to isolate the user from any understanding of
>>what's happening. We much prefer the use of intermediate files in
>>ASCII, rather than hiding things in proprietary binary files. Nobody
>>is perfect at error messages, and the more information we have to go
>>on when the going gets tough, the more likely we are to get out of
>>the situation. Xilinx seems to be moving away from ASCII outputs,
>>and NeoCAD has never been that open, as far as I know. However,
>>that's another issue altogether.
>>
>>Arnim Littek. arnim@digitech.co.nz
>>
>>
>>--
>> arnim@actrix.gen.nz
>>
Article: 41I need large net lists for a current study of cpld/fpga/asic design. 10K gates/1000clb/1000le/1000modules would be fine, 100K gates even better. Edif/xnf/verilog/vhdl is ok. Does anyone know of such a database (or have any to donate). I don't need the functional specification, I am only interested in the geometric structure. I already know about mcnc, so no need to reference them. Thanks for your help Stephen -------------------------------------------------------- home: sjsmith@netcom.com work: sjsmith@altera.com --------------------------------------------------------Article: 42
--- We have developed some (in house) layout tools that are timing driven and do great job when compared with Xilinx tools for some of the MCNC and other benchmark examples. I am interested in getting some design examples with timing constraints that are desired. Currently we do routing using our own fast multi-terminal router but that is going thru changes. The placement part is fully automated. Correct lca files are generated to perform routing using Xilinx router(s). Anybody willing to share design examples (nda no problem) would help us a lot!! --dinesh Dinesh Bhatia University of Cincinnati --Article: 43
Hi all, How does XACT5.0 compare to XACT 4.03? I have used xact 4.03 and don't think much of it, espcially the xblox library. Has the routing become more predictable? have they allowed the designer more access to routing resources? Are there any *TRUE* incremental routing utils in XACT 5.0? Can we generate "hard macros" in xact 5.0? can we route a functional-block of arbitrary fix it in that position in subsequent routing ? your views would be appreciated Ahmed... ------------------- Attention To Detail | Tel: +44 926 843 444 Unit 3, Nunhold Business Centre | FAX: +44 926 843 363 Dark Lane, Hatton | Modem: +44 926 843 587 Warwick, U.K. CV35 8XB | Email: ahmed@atdetail.demon.co.uk -------------------Article: 44
In article <LKURU.94Aug2200742@alpha.hut.fi> lkuru@snakemail.hut.fi writes: >>Now we have companies like Xilinx, Actel, etc; these guys are really >>software companies - Xilinx and Actel will even tell you so if you have >>the chance to talk to some of there high level engineering folks. > >I don't agree. These software products look great on the marketing >man's papers... >And these companies do get their bread from the HW... Not to be grumpy or anything :-), but if they got their bread from their hardware, one would expect them to be enthusiastically handing out free copies of the software to promote hardware sales. Nothing could be farther from the truth... -- "We must choose: the stars or the dust.| Henry Spencer @ U of Toronto Zoology Which shall it be?" -H.G.Wells | henry@zoo.toronto.edu utzoo!henryArticle: 45
Just to add another data point, I have been using Xilinx ppr tool for about a year. My target devices are 4010 parts, with a utilization of 50-60%. However, my place and route times are on the order of 2-3 hours using a sparcstation 10. Some of the things which are no doubt causing added processing are: 1) The abundant use of path timing constraints, some of which are tight. 2) The use of several hard counter macros (which obstruct routing). 3) The use of several 16 and 32-bit busses (which require lots of routing). 4) Setting place and route effort levels fairly high to get good timing. --Charles flaig@3do.comArticle: 46
Baiju Jacob (jake@astro.ocis.temple.edu) wrote: Ok, A design I was part of used 14 Altera MAX devices to build a superclone of the RCA 1802. We called it the 18020. This design was then exported to workstations and then built into custom ASICs. All in all a great experience! bob proffittArticle: 47
Has anyone tried ever to create a pierce x-tal oscillator using I/O pins from a FPGA (I'm thinking here about the intel 780)? I would need this for a slowish (<10MHz) oscillator on a single-chip solution using the FPGA. Any luck, or should I use an external oscillator? Frank -- ------------------------------------------------------------------------ Frank A. Vorstenbosch +31-70-355 5241 P.O. Box 85800 Kingswood Software Fax/Modem +31-70-355 8674 2508 CM The Hague prompt@hacktic.nl The NetherlandsArticle: 48
The key to getting the s/w free is to dangle a large enough quantity of parts to be sold in front of the Rep/Disti/Dude. Most of these companies want to sell 10,000 or 100,000 parts and are willing to hose the smaller companies/individuals and only hand out freebies where they think they can get business. Otherwise software is just another profit center :-( In a sense this is similar to NRE costs on ASICs - you can pay now, or make it up in volumes later. I would love to see all of the FPGA guys come out with a bare-bones product for free - no auto place & route, no support, just a disk - take netlist in, spit timing out, and maybe an interface to a simulator and a bitstream for the part. That would keep the 'freebie' people happy, and save the real effort for the paying customers.Article: 49
Hello, I'm having problems with my mouse when I start MAKEBITS from XDE. Somehow the program recognizes my mouse as a XCHECKER cable. Thus I can't use my mouse. I already tryed the 'port' command, and to save a proper configu- ration in the profile, but that doesn't help. Somehow the problem can be fought by moving the mouse when starting MAKEBITS. But that works only in 2 of 3 cases. And I feel really stupid jerking around while starting a program.. :) I'm not quite sure if this is the right place to ask, but I know no better place.. If you can help me please answer by pm. Thank you Thomas Hadlich -- -------------------------------------------------------------------------- | Thomas Hadlich hadlich@infaut.e-technik.tu-magdeburg.DE | | hadlich@csmd.cs.tu-magdeburg.de | | | | snail: Joh.-Kirsch-Strasse 19; D-39106 Magdeburg; Germany | | Tel. : (0391) 5611021 | --------------------------------------------------------------------------
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