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PLDshell R3.1 is available in
ftp.intel.com:/pub/pld_fpga/software/dos/pldshell.zip
However, the pld_fpga area will vanish on OCTOBER 1 when the
deal is completed. So, get what you need before then.
--Richard Vireday
Intel PLD & FPGA Business Unit
Article: 151In article <Cv1sM5.D1L@nntpa.cb.att.com>, satwant@regulus (Satwant Singh) writes: |> Brad Hutchings (hutch@timp.ee.byu.edu) wrote: |> |> : Can someone give me some information on DHARMA? Are there some |> papers, |> : technical reports, etc.? |> |> DHARMA is an FPGA architecture patented by University of |> California at Berkeley. It was developed as a PhD research |> project by Narsimha Bhat (Is he listening?). |> |> I once attended the following talk: |> Performance-Oriented Fully Routable Dynamic Architecture for |> a Field Programmable Logic Device. |> By Narsimha Bhat. |> |> The thesis copy should be available from UC Berkeley |> library. I am not aware of any other reference on this. |> |> Satwant. Dharma was a joint work with Narasimha and me. The work was published in last years Oxford FPGA workshop, and we are currently working on the journal paper. If you can't find the paper I will be glad to send you, or if you need any more information I would be glad to provide it.Article: 152
> Wrong!!!!! We have purchased one eval. kit last year. It does NOT include > simulation. Finally, we have purchased a full package. We have checked > with our representative a few days ago. They say that the eval. kit does > not include simulation. Dear Sir, Remember way back in article #223 when I suggested that you check out QuickLogic's CURRENT databook? Did you actually heed this advice before making your last post? Sure doesn't sound like it to me. It appears that you have been given some very outdated information. You know, sales reps and disti's don't always keep up with the companies they deal with. If you want positive proof of how horrendously wrong (and ignorant) you are, why don't you just call the QuickLogic headquarters yourself? You should have their phone number if you have their full toolkit. Next time, make SURE you know the facts before you tell someone they're wrong. Have a nice day :) -mArticle: 153
Michael K. Hinazumi (hinazumi@spot.Colorado.EDU) wrote: : > Wrong!!!!! We have purchased one eval. kit last year. It does NOT include : > simulation. Finally, we have purchased a full package. We have checked : > with our representative a few days ago. They say that the eval. kit does : > not include simulation. : Dear Sir, : Remember way back in article #223 when I suggested that you check : out QuickLogic's CURRENT databook? Did you actually heed this : advice before making your last post? Sure doesn't sound like it : to me. : It appears that you have been given some very outdated information. : You know, sales reps and disti's don't always keep up with the : companies they deal with. If you want positive proof of how : horrendously wrong (and ignorant) you are, why don't you just : call the QuickLogic headquarters yourself? You should have their : phone number if you have their full toolkit. : Next time, make SURE you know the facts before you tell someone : they're wrong. : Have a nice day :) : -m Dear Michael, Do you have a eval. kit right now? Would you give us some evaluation results on that? It is very interesting for us that it just costs $99 to have full function except parts programming. Best Regards, Onmate Technology Ltd.Article: 154
I have a Texas Instrument's Activator 2 that I won't be able to use. Hence it's for sale or trade to someone who can use it. * The Activator 2 is designed to allow programming of TI's TPC10 and TPC12 series devices and will program any TI design created with the TI Action Logic development system (TI-ALS). For example, 1010, 1010A, 1020, 1020A, 1280, 1240, 1225. This model has 4 ports for 4 programming adapters which allow simutaneous programming of up to four FPGA devices. * One ACT1-84LCC programming adapter is included. Adapters for 44, 68 and 84 pin PLCCs, 84, 132 and 176 pin PGAs, 100, 144 and 160 QFPs are available from Actel/TI. * Action Logic System (ALS) for PC 386/486, Ver 2.1, Rev 2A * ViewLogic Release V4.0D. The softwares above are older DOS versions. New Windows versions (ALS 2.2sa and ViewLogic V5.1 are available for $3495 and $4450 respectively for up to 10,000 gates, or $995 and $2295 for up to 2500 gates, MSRP) The MSRP for the Activator 2 is $3995 The price for the programming adapter is probably ~ $200 So basically this WAS a $10,000 value. If you think you can use the above, make me an offer. No offer is too low, and of course, no offer is too high :-) I can't use it, someone might as well use it if you do ASIC design and programming. I will even consider trading for some computer equipments.Article: 155
In article <345gbu$kp0@ornews.intel.com>, Richard Vireday <rvireday@pldote.fm.intel.com> wrote: >PLDshell R3.1 is available in > > ftp.intel.com:/pub/pld_fpga/software/dos/pldshell.zip > > >However, the pld_fpga area will vanish on OCTOBER 1 when the >deal is completed. So, get what you need before then. > >--Richard Vireday >Intel PLD & FPGA Business Unit I should add something to Rich's comment. I have recently spoken to Altera concerning their support of the Intel FLEXlogic FPGAs and PLDshell Plus programming environment once Altera takes over the product line on October 1. They have told me: 1) Altera will continue to provide the Intel FLEXlogic FPGAs for at least the next 3 years. They are not going to abandon the chips as some have feared. 2) PLDshell will still be available for FREE. Altera is not going to start charging for it. 3) Altera will incorporate the software for programming the Intel FLEXlogic FPGAs into their own MAX+PLUS II programming environment. The date for that is sometime in 1995. As for how Altera will distribute PLDshell after Oct 1, I'm not exactly sure. I am talking with them about allowing XESS to distribute the software over the Internet. In addition, the PLDasm examples for my FPGA book are now available from the FTP site ftp.vnet.net and the files are stored in /pub/xess under the name workout.tar.gz. All the examples have been UNIX-tarred and GNU zipped, so if you can't decode them let me know and I'll provide them in another format such as PKZIP. I want to publicly thank Intel and Rich Vireday for providing a distribution site for these examples. -- || Dave Van den Bout || || Xess Corporation ||Article: 156
: Does anyone know where Intel's ftp site is? I'm trying
: to get ahold of PLDshell.
The PLDshell software is available, for free, at
ftp.intel.com:/pub/pld_fpga/software/dos/pldshell.zip
(about 2 Megabytes to download)
Article: 157The Intel ftp site is ftp.intel.com. While is software is okay, I have had problems with its handling of the internal SRAM (the simulator supports only two of a possible six configurations). Please keep in mind that Intel sold its Flexlogic line of FPGAs about three months ago (which PLDShell targeted). In article <1994Sep1.154114.14217@peavax.mlo.dec.com>, arthur@alcor1.mlo.dec.com (Ed Arthur) wrote: > Hi, > > Does anyone know where Intel's ftp site is? I'm trying > to get ahold of PLDshell. > > Thanks, > /Ed -- Larrie Carr Product Designer PMC-Sierra, Inc. Burnaby, B.C.Article: 158
In article <1994Aug31.210514@timp.ee.byu.edu>, Brad Hutchings <user@machine.domain> wrote: > >To some extent, in static run-time reconfigured systems anyway, it is a matter >of how often the system gets reconfigured. You might view the set of static >RTR systems as a continuum: > >Configured Once Configured many >per algorithm +++++++++++++++++++++++++++++++++++++++++ times per algorithm > >where systems such as Splash, Prism, PAM are on the left, and systems >such as RRANN are on the right. Of course there are different reasons >for implementing systems with varying frequencies of reconfiguration. Yes, ideally there will be some kind of reconfiguration cost metric that can be plugged into the compiler so that it will spit out the best (re)configuration strategy -- once, some, or many configurations -- that minimizes the overall execution time...with cheaper reconfiguration, you can afford to reconfigure more often. I had written: >|> Even more challenging is to define an architecture & executable format >|> so that the same dynamic configuration execution file can run on >|> different-sized FPGA's (and take advantage of the additional resources >|> available in larger ones). >This is an interesting idea. Kind of reminds me of binary compatability >of software. The obvious thing is to reconfigure less often when >you have plenty of silicon, more often when there is less silicon >available. Yes exactly -- just as how today the same executable can be run either on a vanilla micro or on a four-way superscalar. However, now it looks like we need to define a relocatable configuration format, so that a configuration can execute either on an entire 25,000-gate FPGA, or on either the left or right half of a 50,000-gate FPGA, etc., wherever there are some available resources. Not easy! > Beyond this it would seem that some additional placing >and routing might be required to use the additional area >(similar to recompilation). In my situation -- looking to replace standard microprocessors in workstations with specialized FPGAs -- the problem is that the directory of executables may be mounted across the network by many workstations having different-sized FPGA compute engines... while you could have a different executable for each size, it would be nice to instead have only one. > Brad L. Hutchings (801) 378-2667 >Brigham Young University - Electrical Eng. Dept. - 459 CB - Provo, UT 84602 > Reconfigurable Logic Laboratory -------------------------------------------------------------------------- Tim Callahan timothyc@cs.berkeley.edu timothyc@icsi.berkeley.edu UC Berkeley, EECS, CS Div. International Computer Science InstituteArticle: 159
Those of you using Xilinx XACT 5.0 with the Mentor interface might want to think twice about upgrading to 8.4 (A-1.F). It appears that Mentor changed the shared libraries distributed with this version and now the Xilinx tool, gen_sch8, which produces backannotated schematics does not work. Xilinx has verified this but it is not clear when a workaround will be available. If 8.4 is important to you, you might want to give Xilinx a nudge ... :-) -- Jim Frenzel, Asst. Prof Electrical Engineering, BEL 213 208-885-7532 University of Idaho jfrenzel@uidaho.edu Moscow, ID 83844-1023 USAArticle: 160
A question for any experienced Xilinx designers who have used both the XC3000
and XC3100 series Xilinx parts:
What speed increase can I expect by migrating a design from an XC3090-100
to an XC3190-3?
I have a design which employs some long combinatorial chains (up to 6
CLBs) which unfortunately cannot be pipelined. I have implemented the design
using a 100MHz XC3090, and the design falls over at about 22MHz (as expected).
The system spec requires this design to run at 33 MHz. Is a 50% increase in
speed a realistic expectation?
regards,
===============================================================================
Richard Keaney
School of Maths, Physics, Computing and Electronics
Macquarie University, Sydney NSW 2109 Australia
phone + 61 2 850 8437
fax + 61 2 850 9128
===============================================================================
Article: 161National Semiconductor was making the Opal jr JEDEC Logic compiler available free of charge, but I heard they are dropping PLDs. Does anyone know of an ftp address where this could be downloaded? Or any other JEDEC compiler? -- Michael DeCosta IIIArticle: 162
I have been using an XC3130 in a design for several months. During these months I have come across 3 failures (out of around 50 boards). Examination showed that when the devices were being programmed the !LDC pin was high rather than low. Also the Dout pin did not track Din during the preamble part of programming (serial slave mode). I sent two parts off to the Xilinx processing Labs and got a reply verifying that the devices had failed - the cause being "severe electrical overstress". On questioning them I was told that: - this cannot be due to EDS - this could be caused by either overshoot or high currents I have done some further testing on the overshoot front by inputting 3V of overshoot on an 8KHz signal (total = 8V). Under normal operation this signal has about 2V of overshoot and is the worst of all inputs. This input (8V) was left for a weekend and didn't cause any problem to the device. Has anyone ever come across a similar situation or does anyone have a suggestion of possible causes? Emma MowatArticle: 163
In article 6wu@SSD.intel.com, michaelt@ssd.intel.com (Michael Tchou) writes: [ Stuff Snipped ] ---> --->Does Xilinx not directly offer an edif-to-xnf tool? This --->would seem to be an important capability for XIlinx to --->support, for strategic reasons. They used to, it appeared in the 1992 data book but was later withdrawn. When I inquired earlier this year I was fobbed of with the pretty lame excuse that compatibility problems between the various versions of edif used by some third party vendors was the reason for this. My guess is that by removing such third party links they can make more money selling their own software. Paul.Article: 164
>The AE sheepishly replied that he used Data/IO's software to do the >design, then translated it at the end! Here in Germany the sell a book calld "Handbuch der PLDs und FPGAs" which includes a more ore lesse functionabel develpment kit for the isp1016... It uses Eazy-Abel for generating of the equations, a special programm called winptrans for the convertion to a Lattice ldf-file and the lattice Starter kit... It works almost fine... of course some bugs which need a little handwork between the conversation but the Program is under development... Bye SteveArticle: 165
richardk@mpce.mq.edu.au (Richard Keaney) writes: ... >What speed increase can I expect by migrating a design from an XC3090-100 >to an XC3190-3? > >I have a design which employs some long combinatorial chains (up to 6 >CLBs) which unfortunately cannot be pipelined. I have implemented the design >using a 100MHz XC3090, and the design falls over at about 22MHz (as expected). Try re-running XDELAY, only tell XDELAY that you are using a 3190-3. XDELAY will load the appropriate timing/delay template and give you an excellent idea of the expected speed/delay difference. Bob Elkind, Tektronix TV bobe@tv.tv.tek.comArticle: 166
Hi dear friends I'm doing PhD research in university of Birmingham, UK and need your help. I want some information about a chip produced by Harris Semiconductors, called HSP45256, which is a binary correlator. I've already read Harris data book, many times, but still there are many questions that I can't find their answers in the data book. So please, if you know any article, application, or papers regarding the above mentioned IC, let me know. Also, if you know any other company who has produced similar ICs, please let me know. (Harris HSP45256 is used in DSP systems). I appreciate your attention and looking forward to hear from you soon. My email is : H.R.YAZDI@BHAM.AC.UK Cheers H.R.YazdiArticle: 167
In article <347qlh$mgn@owl.csrv.uidaho.edu>, jff@mrc-gwy.uidaho.edu (Jim Frenzel) writes: |> Those of you using Xilinx XACT 5.0 with the Mentor interface |> might want to think twice about upgrading to 8.4 (A-1.F). |> |> It appears that Mentor changed the shared libraries distributed |> with this version and now the Xilinx tool, gen_sch8, which produces |> backannotated schematics does not work. Xilinx has verified this |> but it is not clear when a workaround will be available. |> |> If 8.4 is important to you, you might want to give Xilinx |> a nudge ... :-) And as a former Mentor employee, I suggest that you give Mentor a nudge as well. |> |> -- |> |> Jim Frenzel, Asst. Prof Electrical Engineering, BEL 213 |> 208-885-7532 University of Idaho |> jfrenzel@uidaho.edu Moscow, ID 83844-1023 USA -- Brett C. Stutz Staff Engineer and Object Wrangler Xilinx Opinions are mine, not those of my employer.Article: 168
In article <1994Sep6.234750.28206@xilinx.com> bretts@fred.xilinx.com (Brett Stutz) writes: > >In article <347qlh$mgn@owl.csrv.uidaho.edu>, jff@mrc-gwy.uidaho.edu (Jim >Frenzel) writes: >|> Those of you using Xilinx XACT 5.0 with the Mentor interface >|> might want to think twice about upgrading to 8.4 (A-1.F). >|> [snip] > >And as a former Mentor employee, I suggest that you give Mentor a nudge >as well. >|> This is ridiculous! I've been on the Mentor/Xilinx rollercoaster since the Mentor 7.x/Apollo days and the introduction of the XC4000 family. I'm really getting tired of convincing my management that Mentor/Xilinx is the way to go only to be hit with yet another buggy version of one or the other (or both)! Not only are new bugs introduced, but a fair number of old ones are never fixed. What's the sense of reporting a bug and some workaround I've come up with, only to find it in the next version? Of course, I'm a low volume Xilinx/Mentor user, so I guess my voice is just like that little squeak in the attic - you know about it, you'll get to it someday, but not just now. Hey Mentor! Hey Xilinx! NUDGE!!!!!!! NUDGE!!!!!! Get in sync people. I don't care how terrific your product is, if your support tools don't work, neither do I. And if I don't work, I guess I can't buy your product. I may not be a large market share, but I can certainly help spread the word. -- Joe Schulingkamp, joes@vfl.paramax.com Unisys Valley Forge Engineering CenterArticle: 169
> Do you have a eval. kit right now? Would you give us some evaluation > results on that? It's a very nice toolkit... very easy to learn, and the tools run pretty fast (as compared to the 8+ hour P&R you'd see with some "brand-X" parts). The other thing you should take note of is that it's their FULL tollkit (minus the ability to program an FPGA), so there's no limit on the size of your design, and you can target your design for any of their device/package combinations. You also get their full macro library (475+). > It is very interesting for us that it just costs $99 to > have full function except parts programming. Yes, it's extremely worthwhile if you're even considering using QuickLogic parts. The eval kit lets you see which device your design will fit into, and it lets you examine issues such as the speed your design will run at, density, and ultimately, cost (after which you may decide for or against buying their full toolkit). As I mentioned before, if you want more info, you may contact a friend of mine who works there: randyo@qlogic.com Regards, -mArticle: 170
Hello all....
I saw mention of GigaOps just-introduced video-compute-engine
development platform in an EE Times article.
Does anyone have knowledge about this product that they are willing to
share. Questions that come to mind are:
- Which FPGA are they based upon? SRAM/VRAM?
- How does the system scale upwards for larger problem
- What tools/libraries are used
- In what form is image data put in and taken out?
- Is this a proprietary hardware system?
Eric
--
Eric Pearson -- Focus Systems -- Waterloo, Ontario
ecp@focus-systems.on.ca (519) 746-4918
--
Eric Pearson -- Focus Systems -- Waterloo, Ontario
ecp@focus-systems.on.ca (519) 746-4918
"We Engineer Innovative Imaging Solutions"
Article: 171I'm currently doing my final year thesis at the James Cook University of North Queensland, Australia, building a NOAA satellite receiver card for a PC and using an IFX780 (84 pin pkg) epld to implement some synchronous logic. Basically I've just got a few counters, a 15 bit shift register and other logic - about 70 macro cells. I used a schematic program (SCHEMA) to lay down the logic schematic, and the PLDShell software to produce a .PDS file, .JED file etc. I'm at the testing stage at the moment and facing some major problems! As this is the first time anyone in our deparmtment has used this EPLD I'm hoping someone out there in netland may be able to help me out. I'm inputing a 660 kbit/sec clock and data stream straight into a D flip flop. The output feeds a shift register and also goes to an output pin. At the moment when I program the whole design I can't get anything happening on the output of the D flip flop! It stays high regardless of the data input. I've checked all the CFB supply voltages, Grounds, and verified the programming of the SRAM. I made a simple test circuit with just a D flip flop, data and clock, and that worked fine. It's only when I download the entire design that I can't get anything on the data output. I'm using the clock on pin 43, it's being used in some asyncronous logic so I didn't use the dedicated clock pins, data_in on 41 and data_out on 72. This config makes my pcb board a bit simpler, but i can change the pins around if need be. Should only certain pins be used for external clock input ? I tried moving the clock and data pins around with no luck. If anyone has worked with this chip and can spare a few minutes to give me some direction/pointers/ideas, then I'd be grateful. Thanks in advance, Michael Cameron eng-mjc@manta.jcu.edu.auArticle: 172
Does anyone have the postal address of I-Cube. If you have can you e-mail it to me. Thanks. AndyArticle: 173
> Also, if you know any other company who has produced similar ICs, please let me know.
LSI Logic makes the;
L64230 - Binary Filter and Template Matcher (BFIR) 20Mhz, 32x32 pixel binary correlator.
can also be s/w configured for 16x64, 8x128, 4x256, 2x512 or 1x1024.
L64240 - Multi-bit Filter (MFIR) 20Mhz, 8x8 pixel, 8 bit coefficient & data, correlator.
can also be s/w configured for 4x16, 2x32 or 1x64.
-------------------------------------------------------------------------------
Jeff Cummings, Sandia National Laboratories, (505)-844-2094, jtcummi@sandia.gov
MS 0503
Department 2335
-------------------------------------------------------------------------------
Article: 174In <34n680$na6@hippo.shef.ac.uk> A.Shelley@Sheffield.ac.uk writes: > Does anyone have the postal address of I-Cube. If you have can you e-mail it to me. > Thanks. > Andy > > > Andrew, please fix your address field. This is what I got when I tried to `reply` to your post: > Your message was not delivered to A.Shelley@Sheffield.ac.uk > for the following reason: > Unknown Address > MTA 'Sheffield.ac.uk' gives error message Unknown local user > 'A.Shelley' In <34n680$na6@hippo.shef.ac.uk> A.Shelley@Sheffield.ac.uk writes: > Does anyone have the postal address of I-Cube. If you have can you e-mail it to me. > Thanks. > Andy Andrew: I-Cube, Inc. 2328-C Walsh Avenue Santa Clara, CA 95051 USA Phone: +1 408 986 1077 FAX: +1 408 986 1629 BBS: +1 408 986 1652 email: marketig@icube.com All this from the back of a May 94 data sheet, so it should be current. Hope this helps. -- Norbert Juffa (juffa@ira.uka.de)
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