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Gavin Brebner (gavinb@shannon.tellabs.com) wrote:
: Does anyone have contact information they can pass on
: to me for I-Cube; email / fax / telephone or even snail
: mail address all acceptable.
I have some information for you. :)
Wichai Tang
====================================================================
: Regarding #3, there is another vendor supplier field programmable
: interconnect chips (FPICs); they are:
: I-Cube
: Santa Clara, CA
: (408) 986-1077
: board that consists of FPGAs and FPICs. I-Cube appears to be content with
: being a chip vendor rather than moving up the food chain as did Aptix.
I-Cube has online versions of it's datasheets and appnotes available
from the the following source:
ftp.netcom.com in directory \pub\icube
Have fun
_______________________________________________________________________
Kent Dahlgren Phone: (408) 986-1198
I-Cube Inc. FAX: (408) 986-1629
2328-C Walsh Avenue Email: kentd@icube.com
Santa Clara, CA 95051
_______________________________________________________________________
The three sub-directories contain I-Cube's product support literature
organized as follows.
Directory Contents
--------- --------
AppNotes Application Notes and Application Briefs
DataSheets Product Data sheets
TechNotes Technical information related to product usage
All files are in postscript format and are compressed. You may obtain
a hardcopy of the information by copying these files and sending them to
a postscript capable printer.
If you have any questions, please contact I-Cube at:
EMAIL: marketing@icube.com
TEL: +(408) 986-1077 (ask for Marketing)
FAX: +(408) 986-1629 (address it to Marketing)
Titles of the various documents available as of [3/31/94] are:
Application Notes and Briefs:
-----------------------------
asicemul.ps.Z Using FPID Devices In FPGA-based Prototyping
buswatch.ps.Z Programmable Bus Watcher
commswit.ps.Z FPID-based Communications Switching
faulttol.ps.Z Fault Tolerant Memory Design
ipcommne.ps.Z Interprocessor Communications Network
lainterf.ps.Z Logic Analyzer Interface
lanswitc.ps.Z FPID-based 10Base-T Switching Hub
largecro.ps.Z A Large Crossbar Switch Using Multiple FPID Devices
progback.ps.Z Optimizing Performance in Multistage Network
smartswi.ps.Z Combining FPGAs and FPID Devices in Networking Applications
Data Sheets
-----------
fpid.dsheet.ps.Z The FPID Family Data Sheet - Rev 1.0, February 1994
Technical Notes
---------------
parallel.ps.Z Configuring FPID Devices Using PC Parallel Port
Article: 1026In <3mm49h$b2f@hex.viewlogic.com> allen@hex.viewlogic.com (Dave Allen) writes: >TAM ERNEST CHI YUI (tame@eecg.toronto.edu) wrote: >> When I want to ppr my design in XC4010, it says that the .xtf file is >> missing. I used ppr before but that time, my design was made of >> standard logic. This time, all the building blocks are described in >> VHDL. I am working in the Powerview environment. I use vhdl analyzer >> to analyze the source code and then use vhdl2sym to create the >> symbol for each block. Afterwards, I use Viewdraw to put together >> all the blocks and simulate. >> >> Is there any step I have to do before I run the PPR program? >> How can I generate the .xtf file for PPR? >Are you using the Xilinx "xmake" program to run all of the Xilinx tools >automatically? There are a number of tools in the Xilinx design flow, >such as wir2xnf, xnfmerge, and xnfprep. The tools must be run in the >correct order, which is what xmake does for you. The "xtf" file is one >of the intermediate files in this chain of tools. >- Dave Allen: allen@viewlogic.com Also, are you using just the analyser, or are you synthesising gates using ViewSynth? Good Luck. -- David Lanza dlanza@harris.comArticle: 1027
In article <D71Lt3.4vq@world.std.com>, Joseph H Allen <jhallen@world.std.com> wrote: >In article <D710CG.HMB@world.std.com>, >John Cooley <jcooley@world.std.com> wrote: > >>Next week, a small FPGA start-up formed by an ex-Mentor synthesis R & D >>guru, Ken McElvain, will be announcing a rather unusual FPGA synthesis >>tool for both the PC and UNIX marketplace. What makes this tool so >>different is closely reflected in the name on the company: Synplicity. > >>Ken's tool takes in Verilog or VHDL source code and synthesizes it >>with NO SWITCHES -- that is, the GUI consists of: > >When is someone going to write a freeware synthesis tool (or a even a $100 >synthesis tool)? This couldn't be that hard to do: simulated annealing for >placement is almost trivial, a maze-router for placement is straightforward, >as is a C to logic compiler. A low quality synthesis tool shouldn't be that >hard to come out with. > >Once there is a freeware synthesis tool, we could start a free hardware >foundation. I could see a few high-level free hardware designs making a big >impact on FPGA sales. Imagine if there was a free serial CPU design that >could fit in medium sized FPGA? This is too much to write for one project, >but if a free version was out there I could see people integrating it in >their controller designs- a CPU with a tiny bit of custom logic would be >ideal. FPGAs could be competative with micro controllers. Likewise for >things like DRAM controllers, video controllers and stepper motor drivers. > Joe, The foundations of your "Free-ware" synthesis tools are there; look at the SIS synthesis package from UCB and NETOPTIM, part of the Alliance tool set from "Universite Pierre et Marie Curie (PARIS VI)". SIS is a general purpose package with open libraries; the drawback is that SIS doesn't support any of the popular HDL's as RTL based input. NETOPTIM supports RTL VHDL input, but only targets the Alliance standard cells. Marry the two, and you've got one hell of a package. (SIS already has direct support for Actel and Xilinx I believe??? ...at least Actel). Well...any takers? Regards, Mark -- /* Mark A. Indovina, Principal Staff Engineer mark_indovina@pts.mot.com */ /* MOTOROLA Strategic Semiconductor Operation, IC Technology Laboratory */ /* Mail Stop 63, 1500 Gateway Boulevard, Boynton Beach, FL 33436-8292 USA */ /* phone: 1-407-739-2379, fax: 1-407-739-3904 ...just speaking for me! */Article: 1028
> 1. Free CAD software would be (IMHO) welcomed widely. As I see it, there > would be two obstacles, viz. > > b. Getting the intimate design data (fuse locations) out of the FPGA > vendors. They seem very tight with it. This will change. The first FPGA house to publish this data will be the first company to challenge the big CPU makers. > 2. This would be a delightful challenge, but how practical is it? Unlike > software, hardware cannot be copied at essentially no cost. With a free > design, we still must either buy FPGA's, or persuade some kind soul to > have some wafers run off. Presumably the "free" CPU would need to be > either cheaper or faster than current commercial offerings. Some of the > RISC chips are getting quite inexpensive. Tell me when you can run "Free Software" on "Free Intel CPUs". As far as putting CPUs in FPGAs that sounds like making 8086s emulate PDP-8s. A quote I have always liked is "Todays software is tomorrows hardware and vice-versa" -- A.S. Tannenbaum. Steve CasselmanArticle: 1029
In article <620930260wnr@rmcecl.demon.co.uk>
Mark@rmcecl.demon.co.uk "Mark Webster" writes:
> Hi,
>
> Has anyone tried to use the DOS based Viewlogic suite of programs under
> Windows '95 ?
>
> I have the XACT 5.1 basic kit for Xilinx FPGA's. At the moment I use
> the tools under DOS 6.22 & QEMM & I would like to install Windows '95.
>
Prehaps when MicroSoft release Windows '95 I would be able to tell you, but
my checking last week told me some software supplies haven't even received
there Beta copies yet. If I'm wrong, please tell me someone who has it in
stock.
--
God Bless
Chris Abbott
============================================================================
Article: 1030> 2. A "free CPU architecture", which could be implemented in FPGA's, and > made generally available to be enhanced, etc. Son of MIX? An open architecture for a simple CPU/controller would be nice for ASIC and FPGA use as well as academic tinkering. Support from multiple hardware and software development tool vendors, etc, etc. --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 1031
In article <3mvvoj$h6j$1@perth.DIALix.oz.au>,
David Brooks <daveb@perth.DIALix.oz.au> wrote:
>A few days ago, someone (my apologies, I didn't save a copy, and have
>mislaid their name) posted here, a proposal for "free hardware", along
>the lines of the Free Software Foundation.
>As I recall, the proposal was twofold:
>1. A set of free FPGA design software, produced and distributed similarly
>to Linux.
>2. A "free CPU architecture", which could be implemented in FPGA's, and
>made generally available to be enhanced, etc. Presumably one would hope
>to port Linux to this, obtaining a "free system".
I was thinking more in terms of microcontrollers, and serial ones at that.
FPGAs are really not dense, fast or cheap enough to build a competative
general purpose computer. This could change though: if AT&T ORCA fpgas
suddenly become cheap, then you may have a product.
However, many products become possible with free FPGA software. You could
make a general purpose interface card for a PC, which has an FPGA, ram and a
D connector. This would be useful for connecting a PC to all kinds of
hardware, but it's not viable if you require the user to buy >$1000
software. You could make a hand-held computer with a programmable I/O port.
You could make high-speed industrial control modules (they may even be
programmable in 'ladder logic' :-).
With a library of free complex hardware designs, many small projects become
easier. You could make a truly useful microcontroller: one FPGA, an EPROM
and maybe a RAM chip. A three chip microcontroller with exactly the I/O you
need for your project. A xilinx 3030 (a $25 FPGA) is probably just (barely)
large enough to do something like this.
Also if you could include a synthesis tool in the software of your system,
the system could reconfigure the FPGA (or part of the FPGA) depending on
setup parameters. The very power of the FPGA is itself improved. Consider
a video generator design (dram controller, sync generator and bus
interface). It is easy to fit a video generator for fixed sync frequencies
into a small fpga. If you want to make a fully programmable video
generator, you need an fpga of at least 4 times the size just for the
configuration registers. But this is stupid: static-ram FPGAs are already
reprogrammable. I've actually seen special purpose video cards with
hundreds of fpga files for different sync frequencies. This nonsense could
easily be eliminated with freeware synthesis tools and an open fpga design.
For vertical product engineering consultants like myself, a free (or cheap)
fpga synthesis tool would be immensely useful. Such a tool could really
eliminate the need for TTL and smaller PLDs.
>If I have quoted correctly, I would like to follow up thus:
>1. Free CAD software would be (IMHO) welcomed widely. As I see it, there
>would be two obstacles, viz.
> a. The sheer size of the task - OK the Linux project shows it's possible.
It turns out that a great deal of this work is already done. There already
is a freeware synthesis package called SIS from a group at berkeley. This
package optimizes your logic or state machine design and maps it onto the
technology of the FPGA. I.E., if your FPGA is made of 5-input/1-output
logic blocks with a register (xilinx 3000 CLBs), then this package outputs
your design in terms of connected blocks of this form. I think the package
may not be able to deal with asynchronous flip-flop reset signals, but that
may not be too much of a problem (maybe one algorithm has to be redone).
Once you have a design in this form you have only to optimize the placement
of the logic blocks and route the signals between them. The algorithms for
doing these are not difficult to implement. In fact some students in
holland made a complete asic synthesis system (called 'ocean') by writing
these modules for their own asic mask. I don't have access to cmos vlsi
fabrication, so this system is not all that useful (to me).
The input to SIS is ugly, but easily machine generated. A schematic capture
program and/or a C-like hardware description language would be needed as a
front-end. These are sizeable projects, but are completely straightforward.
> b. Getting the intimate design data (fuse locations) out of the FPGA
> vendors. They seem very tight with it.
Yeah, this is the real problem. Luckily reverse engineering is a legitimate
way of obtaining trade secrets. The only legal problem may be a shrink-wrap
license violation- but these are not very strong (not that I want to deal
with any kind of lawsuit).
I'm wondering if the main part of Xilinx's revenue is from software tools
instead of chip sales. This may be the reason for their reluctance to
divulge this information. On the other hand, I doubt a free synthesis tool
would effect them all that much. It would allow people who otherwise
wouldn't buy their development system to use their chips. Unless the
quality of a freeware tool is higher than their own, I doubt it will effect
their software sales. It would increase their chip sales (but for
vertical markets that is probably not significant).
>2. This would be a delightful challenge, but how practical is it? Unlike
>software, hardware cannot be copied at essentially no cost. With a free
>design, we still must either buy FPGA's, or persuade some kind soul to
>have some wafers run off. Presumably the "free" CPU would need to be
>either cheaper or faster than current commercial offerings. Some of the
>RISC chips are getting quite inexpensive.
I don't think there will ever be free hardware, but there could certainly be
free hardware designs.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 1032In article <3mt85v$kru@news.csie.nctu.edu.tw>, Chuang Hsien-Ho <eea80593@maddux.EE.NCTU.edu.tw> wrote: >Hi: > >I want translate SIS's output(blif/slif/eqn...) to XNF format. >Does anyone has the translator? Or any other sugesstion to me? >Thanks a lot! > I wanted to do the same thing a year or two ago. The problem was that after SIS had mapped to LUT/CLB's, you lose that mapping when you write it out as EQN (or at least the mapping was lost somewhere along the path to XNF). I had a version of SIS that had a write_map function that wrote out a .MAP file, but that was for X3000 series, and it did some funny stuff with the DFFs (it latched the output of every CLB, even in multi-level mappings). So...I wrote a routine called write_xnf that writes out something kinda like X4000 XNF, using only 4- and 5-input ROMS, i.e. arbitrary 4- and 5-input boolean functions. It seems to work, but I haven't tested it on any large projects yet. Oh, and I think it only works with purely combinatorial circuits -- if you are synthesizing a FSM, you need to add the state registers manually. I will put a link to the code, as is, in my home page in the next day or two. ------------------------------------------------------------------------ Tim Callahan 441 Soda Hall, (510) 643-8229 timothyc@cs.Berkeley.EDU http://http.cs.berkeley.edu/~timothyc/ ------------------------------------------------------------------------Article: 1033
David Brooks <daveb@perth.DIALix.oz.au> writes: >On a more positive note, about 20 years ago, I built a homebrew CPU using >some 120 TTL/MSI chips. 64kB space, operands 8-64 bits wide. The design >could quite readily be modernised and migrated to a FPGA. If anyone is >interested, I could do this, and am quite happy to publish the FPGA >design files, as a "free CPU". However, it will never be as hot as a >Pentium :) I would be interested in seeing your design, in descrete chips would be fine. The best part would be designing it myself but I would like some hints to get me going which your design might just do. I think that there are quite a few people intersted in such a project.Article: 1034
In article <D71Lt3.4vq@world.std.com>, Joseph H Allen <jhallen@world.std.com> wrote: > Joe, The foundations of your "Free-ware" synthesis tools are there; look at the SIS synthesis package from UCB and NETOPTIM, part of the Alliance tool set from "Universite Pierre et Marie Curie (PARIS VI)". SIS is a general purpose package with open libraries; the drawback is that SIS doesn't support any of the popular HDL's as RTL based input. NETOPTIM supports RTL VHDL input, but only targets the Alliance standard cells. Marry the two, and you've got one hell of a package. (SIS already has direct support for Actel and Xilinx I believe??? ...at least Actel). Well...any takers? Regards, Mark The latest release of SIS (1.2) has a vst2blif converter that allows to use SIS as a back-end of Alliance. I have never used it, but I will start using it very soon. For what Xilinx support is concerned, I am told that only 3000's are supported. As a part of my research work my advisor asked to add support for 4000's, so stay tuned... Regards -- Arrigo Benedetti e-mail: benedett@dsi.unimo.it University of Modena graduate student abenedetti@deis.unibo.it address: Via S. Agata 11 41100 MODENA - ITALY phone: (home) + 39 59 224929 (office) +39 59 216688 (fax) +39 59 220727 -- Arrigo Benedetti e-mail: benedett@dsi.unimo.it University of Modena graduate student abenedetti@deis.unibo.it address: Via S. Agata 11 41100 MODENA - ITALY phone: (home) + 39 59 224929 (office) +39 59 216688 (fax) +39 59 220727Article: 1035
Joseph Allen wrote: >However, many products become possible with free FPGA software. You could >make a general purpose interface card for a PC, which has an FPGA, ram and a >D connector. This would be useful for connecting a PC to all kinds of >hardware, but it's not viable if you require the user to buy >$1000 >software. You could make a hand-held computer with a programmable I/O port. >You could make high-speed industrial control modules (they may even be >programmable in 'ladder logic' :-). >With a library of free complex hardware designs, many small projects become >easier. You could make a truly useful microcontroller: one FPGA, an EPROM >and maybe a RAM chip. A three chip microcontroller with exactly the I/O you >need for your project. A xilinx 3030 (a $25 FPGA) is probably just (barely) >large enough to do something like this. In fact we are working on just such a thing at Cornell. However, rather than use a generic "microcontroller" we compile a concurrent language (similar to occam) into hardware. We've built a prototype compiler and source language debugger. The compiler spits out low level hardware descriptions (currently for the Altera tools). Our prototype hardware is a RIPP10 board from Altera connected to external D/A and A/D. This board is I/O starved and we don't really need access to multiple FPGAs, so our next generation board will be locally designed with lots of I/O, one FPGA for the bus interface, one FPGA for the application, and high speed SRAM for data collection. The advantage of FPGAs is that concurrency is free. The disadvantage is that numerical hardware is expensive. My view is that applications involving timing and moving data around are ideal. If you would like to read more. Some slightly old papers are available at ftp.tesla.ee.cornell.edu. The paths are public/gbrown/dac95-tr.ps.Z and public/gbrown/fpga95.ps.Z. At the time these papers were written, we didn't have a working hardware setup. We've developed a number of working examples since then. Also if you'd like a peek at the users guide for our tools look at public/gbrown/ug.ps.Z. Since this was written, we've added a TK front end to our debugger which allows true source level debugging. Nothing is ready for release now -- perhaps by september. Geoffrey BrownArticle: 1036
In article <BENEDETT.95Apr19093628@caliban.dsi.unimo.it>, benedett@caliban.dsi.unimo.it (Arrigo Benedetti) writes: > > > In article <D71Lt3.4vq@world.std.com>, > Joseph H Allen <jhallen@world.std.com> wrote: > > > Joe, > The foundations of your "Free-ware" synthesis tools are there; look at the > SIS synthesis package from UCB and NETOPTIM, part of the Alliance tool set > from "Universite Pierre et Marie Curie (PARIS VI)". SIS is a general purpose > package with open libraries; the drawback is that SIS doesn't support any > of the popular HDL's as RTL based input. NETOPTIM supports RTL VHDL input, > but only targets the Alliance standard cells. Marry the two, and > you've got one hell of a package. (SIS already has direct support for > Actel and Xilinx I believe??? ...at least Actel). > > Well...any takers? > > Regards, > Mark > >The latest release of SIS (1.2) has a vst2blif converter that allows to use SIS as >a back-end of Alliance. I have never used it, but I will start using it very soon. >For what Xilinx support is concerned, I am told that only 3000's are supported. As >a part of my research work my advisor asked to add support for 4000's, so stay >tuned... > >Regards >-- >Arrigo Benedetti e-mail: benedett@dsi.unimo.it >University of Modena graduate student abenedetti@deis.unibo.it >address: Via S. Agata 11 41100 MODENA - ITALY >phone: (home) + 39 59 224929 (office) +39 59 216688 (fax) +39 59 220727 SNIP ...DUplicate Address Information I am familar with the Alliance tool set, and how to aquire it, but I am not familar with the SIS tool set. For future reference, could someone post information about where and how to aquire the SIS set. If this has already been hashed out before in this area, my apologies. (if this is the case, if someone could email me the info I would muchly appreciate it.) Loren Charnley Electronics Engineer Process Systems, Inc. lcharnle@mosaic.uncc.eduArticle: 1037
I am trying to synthesise some VHDL into XNF format using exemplar. This works fine, but when I run xnf2wir to perform functional simulation in Powerview the wirelist produced contains question marks for some of the clock enables on the FDRD flip flops. How do I either get Powerview to make some assumptions about this and allow simulation or get exemplar to sort it out. Confused, I am... Andy Shelley, University of Sheffield.Article: 1038
In article <3n34nu$a07@news.uncc.edu> lcharnle@uncc.edu (Loren Charnley) writes: I am familar with the Alliance tool set, and how to aquire it, but I am not familar with the SIS tool set. For future reference, could someone post information about where and how to aquire the SIS set. If this has already been hashed out before in this area, my apologies. (if this is the case, if someone could email me the info I would muchly appreciate it.) You can get sis-1.2 from ftp.eecs.berkeley.edu or alternatively, if you have a www client from http:/www.eecs.berkeley.edu. Look for the CAD group and CAD software. cheers, Eric -- Eric Aardoom CAA Institute of Satellite Navigation Dept. of Electronic and Electrical Engineering University of Leeds, LS2 9JT, UK E-mail: E.Aardoom@CAAISN.leeds.ac.uk Phone: +44 113 233 2090 Fax: +44 113 233 2032Article: 1039
In article <D78HAE.ILq@pts.mot.com>, MARK INDOVINA Xxxxx Ppppp <ep520mi@pts.mot.com> wrote: >Joe, >The foundations of your "Free-ware" synthesis tools are there; look at the >SIS synthesis package from UCB and NETOPTIM, part of the Alliance tool set >from "Universite Pierre et Marie Curie (PARIS VI)". SIS is a general purpose >package with open libraries; the drawback is that SIS doesn't support any >of the popular HDL's as RTL based input. NETOPTIM supports RTL VHDL input, >but only targets the Alliance standard cells. Marry the two, and >you've got one hell of a package. (SIS already has direct support for >Actel and Xilinx I believe??? ...at least Actel). I've run across mention of the alliance tools occasionally. I'm interested in looking at them to see if the could be used as replacement or additional seats. Currently we use Cadence for schematics and layout, verilog for simulation, gemini for lvs and magic for drc's. Is the alliance package a possible replacement for Cadence layout and schematics? For example, we felt magic as a layout tool was not an acceptable replacement for Cadence layout. I'd appreciate any info on the alliance tools as they are quite a large package to start looking into without some indication as to whether they are suitable. >Well...any takers? > >Regards, >Mark > >-- >/* Mark A. Indovina, Principal Staff Engineer mark_indovina@pts.mot.com */ >/* MOTOROLA Strategic Semiconductor Operation, IC Technology Laboratory */ >/* Mail Stop 63, 1500 Gateway Boulevard, Boynton Beach, FL 33436-8292 USA */ >/* phone: 1-407-739-2379, fax: 1-407-739-3904 ...just speaking for me! */ -- __________________________________________________________________ | | | Name: Kurt Rosenhagen Email: kjr@panix.com | |__________________________________________________________________|Article: 1040
As I have never heard of either before, any information on how to obtain them would be most greatfull. -- God Bless Chris Abbott ============================================================================Article: 1041
Mark@rmcecl.demon.co.uk writes: > Has anyone tried to use the DOS based Viewlogic suite of programs under > Windows '95 ? > > I have the XACT 5.1 basic kit for Xilinx FPGA's. At the moment I use > the tools under DOS 6.22 & QEMM & I would like to install Windows '95. Xilinx claims that its next release will be windows-based. In particular, it will switch to workview Pro-series for windows. I've been using the Pro-series schematic capture for a few months now, and have had no problem. It's basically a kluged version of the DOS-based system. They eliminated three-button mouse support but included double-click support for many operations. There are still a few goofy features that didn't port well to windows, but everything considered, I prefer the pro-series. The goofy stuff should be real easy to clean up in the next release. I had no problem using ProCaps with my old workview files. Workview gave a $1000 trade-in allowance for my old Xilinx-only version of workview. This allowed me to upgrade to a full working license (not Xilinx-only) for $1500.Article: 1042
Loren Charnley <lcharnle@uncc.edu> wrote:
>I am familar with the Alliance tool set, and how to aquire it, but I am not
>familar with the SIS tool set. For future reference, could someone post
>information about where and how to aquire the SIS set. If this has already
>been hashed out before in this area, my apologies. (if this is the case, if
>someone could email me the info I would muchly appreciate it.)
>
>Loren Charnley
>Electronics Engineer
>Process Systems, Inc.
>lcharnle@mosaic.uncc.edu
Loren,
SIS and MIS are public domain synthesis tools that were developed at
U.C. Berkeley and are available (I think) by anonymous ftp. (Don't
ask me where; I don't know.) Although these tools aren't supported
by anyone, many of the R & D departments of EDA companies that sell/sold
synthesis products are staffed by graduate students and PhD types that
cut their synthesis eye teeth working on these tools. Much of Synopsys,
Exemplar, Mentor Graphics, IBM EDA, AT&T EDA, and Cadence's synth tools
have some sort of indirect ancestral "link" to these two Berkeley
tools -- althought what these companies offer today is considerably
more evolved.
I haven't personally used SIS or MIS so I can't comment on how practical
or impractical it is to design with these tools.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3271 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 1043Sorry, I don't have any journal suggestions for you; however, I am interested in your paper. Is it available on the the net in a PostScript version? If not, do you know when the ACM will publish your paper? Thanks Scott sfrederi@s-cwis.unomaha.edu cewi466@aol.comArticle: 1044
>>>I read an article that said AT&T had dissolved its software group after the Neocad agreement. If this is true I can only guess at how AT&T will proceed. Rebuild a S/W group and give them a piece of code they didn't write and ask them to maintain it. Good Luck! What about new architectures in the future? <<< No, actually, what AT&T disolved was work on their ODS tool in favor of work on the (previously known as) Neocad Foundry tool. They have 30+ developers who have been working for some time on what will now be known as AT&T Foundry, or ORCA Foundry. They are not rebuilding a software group, they are adding to an already large group. Certainly the Neocad takeover is inconvenient, but AT&T is not in the same position that Motorola seems to be in.Article: 1045
> The foundations of your "Free-ware" synthesis tools are there; look at the > SIS synthesis package from UCB and NETOPTIM, part of the Alliance tool set > from "Universite Pierre et Marie Curie (PARIS VI)". SIS is a general purpose > package with open libraries; the drawback is that SIS doesn't support any > of the popular HDL's as RTL based input. NETOPTIM supports RTL VHDL input, > but only targets the Alliance standard cells. Marry the two, and > you've got one hell of a package. (SIS already has direct support for > Actel and Xilinx I believe??? ...at least Actel). SIS does read and write a structural subset of VHDL. It also has support for synthesis of FPGAs (both Actel and Xilinx). The next release will have the capability of directly writing out xnf format (trivial, but not in the released version thus far). Ellen -- Ellen M. Sentovich Tel: (33) 93 95 74 76 INRIA Project Meije FAX: (33) 93 95 74 88 2004, Route de Lucioles - B.P. 93 Home:(33) 93 95 21 41 06902 Sophia-Antipolis Cedex, FRANCE ellen@cma.cma.frArticle: 1046
In <3n3bfr$pq4@hippo.shef.ac.uk> ajs@shef.ac.uk (Andrew Shelley) writes: > >I am trying to synthesise some VHDL into XNF format using exemplar. This works >fine, but when I run xnf2wir to perform functional simulation in Powerview the >wirelist produced contains question marks for some of the clock enables on the >FDRD flip flops. How do I either get Powerview to make some assumptions about >this and allow simulation or get exemplar to sort it out. > >Confused, I am... > >Andy Shelley, University of Sheffield. If you take the design all the way to LCA (it does not need to be routed) then back out to .XNF .WIR .VSM the process will trim out all the unused logic. Good luck. David HolmesArticle: 1047
WWW Site for DAC '95 at URL http://www.dac.com/dac.html
-----------------------------------------------------------
The 32nd Annual Design Automation Conference (DAC) will be held at the
Moscone Center in San Francisco, California, on June 12-16, 1995. You can
use this WWW site to get more information about the Conference and download
the registration forms for conference attendance, hotel reservations, "Free
Monday" exhibits pass, and a DACnet account.
This site will also host the DAC Vendor and Exhibitor Guide when it
becomes available and provide up to date information on meetings and events
scheduled for this year's DAC. Pointers to sights and events in San Francisco
are also included. A detailed overview of the site follows.
What's New?
4/15/95: Moscone Area Map
4/13/95: San Franciso Traveler's Services
4/5/95: New online forms for Free Monday and DACnet account registration
4/5/95: Current hotel and tutorial availability.
4/4/95: Online forms to schedule a meeting and request action/info
from conference managers
4/3/95: Preview the DAC University Booth
Conference Information - Highlights
Technical program and Designer Track program
Friday Tutorials
Proceedings and Best paper info
Exhibits, Exhibitors, and Exhibitor Presentations
Show Hours
Cruisin' - the DAC Party
Meetings at DAC
ACM-SIGDA
Birds of a Feather (BOF)
Contacting convention management services
Registration and Reservations
Conference
Hotel
Air transportation
Travel grant information
DACnet accounts
Spouse and guest registration
The People Behind DAC
Executive Committee
Program Committee
EDA Industry Committee
San Francisco
Ground transportation and Airport shuttle service
Traveler's services
Digital Restaurant Guide to San Francisco
Moscone Convention Center area map
Sites to see / Things to do
San Francisco Chronicle -- Datebook Entertainment listings
Weather
Sponsoring And Cooperating Organizations
The Association for Computing Machinery (ACM) Membership Info
The ACM Special Interest Group for Design Automation (SIGDA).
The Electronic Design Automation Companies(EDAC)
The Insititute for Electrical and Electronics Engineers (IEEE)
The IEEE Circuits and Systems Society (IEEE-CAS)
Other Web Sites of Interest to the DA Community
The SIGDA WWW server has a plethora of DA information, including a
comprehensive list of DA Conferences at http://kona.ee.pitt.edu/
Electrical Engineering World Wide Web Hotlist at http://www.e2w3.com/
________________________________________________________________________
Posted for 32nd DAC by Sean Murphy, Leader-Murphy, Inc.
http://www.l-m.com/l-m.html
Article: 1048Hi, We are interested in implementing a VMEbus (with DMA support) interface using Altera devices (81500 perhaps ?). Has anyone done this kind of design before ? I would like to hear about your experience with such a design. thanks, Raminder p.s. Bus interface designs would make a nice addition to type of designs being discussed in the free hardware thread. 226 Pond Laboratory Tel. 814-863-7325 FAX 814-865-3176 email: bajwa@cse.psu.eduArticle: 1049
( Please repost this to your company's internal newsgroups
and/or mailing lists if they're in New England. - John )
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - /
_] [_ Come See Newborn Lambs Plus Meet The "Real" Aart & Harvey!
Holliston Poor Farm Open House (Noon to 4:30 PM)
Earth Day, Saturday, April 22nd, 1995
If you're part of the greater New England electronic design engineering
community (or just visiting), I'm inviting you and your family to the
Holliston Poor Farm in Holliston, Massachusetts to see 18 sheep and 12
newborn lambs plus meet the "real" Aart and Harvey -- two goats named
after the CEO and Chairman of the Board of the 1200 employee, $250 million
electronic design automation software company "Synopsys." (This is not a
Synopsys endorsed event nor anything to do with electronics; I'm just
doing it to celebrate Earth Day in my own special way.)
This event is meant to be a hands-on activity where you'll get to touch,
walk with and hold the sheep & goats. At the top of every hour I'll lead
a walk into the back pasture/woodlands & stream area with a talk on:
- The history of the poor farm / poor house social welfare system
in colonial New England before the advent of U.S. state & federal
Social Security and Welfare. How the Holliston Poor Farm went
from poor farm to hippie commune to "mainstream" residential living.
- What's involved with raising & birthing lambs; ewe/lamb bonding;
tail docking; the historical environmental impact of sheep on
New England; sheep/goat sociology; how to tell when sheep are angry.
Bring your camera and shoes appropriate for a sheep pasture (hint! hint!).
This is meant to be a drop-in/drop-out type of gathering -- if you want
food or soda, bring it! (Since I'm opening my house to God-knows-who, I'd
like to ask that you please bring your business card.) The lambs are all
1 to 10 days old. For Native American buffs, my quirky landlord has put
up a full scale big white teepee in the back yard. A good place for
breakfast or lunch before 1:30 is Norman's Restaurant (see directions).
Tell them "John Cooley sent us."
Heads up -- I'm not a Synopsys employee; if you work at a competitor of
Synopsys (like ViewLogic, Mentor, Cadence) PLEASE come! This is *social*
gathering; not a Synopsys anything gathering. Even Cadence's Spectrum
Consulting (which I so love to publically badmouth) is welcome!
---- ---- ---- ----
DIRECTIONS: Mass Pike (I-90) to I-495 SOUTH to Exit 19. Immediately
turn right of I-495 ramp, go 100 meters and right again at the light.
(Burger King will be on your right where you turn.) Drive 0.25 miles
to another light and turn right onto Rt.16 EAST. (You should be going
back under an interstate bridge.) Drive 6.0 miles. Near the 5.5 mile
point look for intersection of Rt. 16 and Rt. 126 near "Cumberland
Farms", "Bertucci's Brick Oven Pizzeria", "Country Liquors", "Baybanks
ATM" and "Norman's Restaurant". The Poor Farm is 0.25 miles WEST on
Rt. 16 from this intersection. Look for the first big white farmhouse
on the LEFT that has fields near it and/or a big white teepee behind it.
The second driveway shows a glassed in greenhouse extention to the
farmhouse. (Park on the street OFF the road and go in the greenhouse
extention sliding glass door. Since I'm opening my house to God-knows-who,
I'd like to ask that you please bring your business card.)
From Boston: Mass Pike (I-90) WEST to 128 SOUTH to Rt.16 WEST in Wellesley.
STAY on Rt.16 WEST for 12 to 14 miles (it does some tricks to try to lose
you!) until you see "WELCOME TO HOLLISTON"; in 0.2 miles cross the railroad
tracks & pass the blue "BFI" sign. Look on the RIGHT for an orange,
diamond shaped sign with the black silhouette of a man wearing a hat
crossing the street. My driveway is 3 feet from that sign. (Park on the
street OFF the road and go in the greenhouse extention sliding glass door.
Since I'm opening my house to God-knows-who, I'd like to ask that you
please bring your business card.)
- John Cooley
part-time EDA Consumer Advocate
part-time Sheep & Goat Farmer
full-time contract ASIC & FPGA designer
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3349 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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