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sc@vcc.com (Steve Casselman) wrote:
>>Another, somewhat better way of doing it would have been to define new
>>integer types:
>>
>> int13 a, b, c;
>Wouldn't it be better just to say bit a[13], b[13], c[13]; Then
>I could write c[5] = a[2] & b[3] ;
Steve, this is a clear case of confusing semantics. C vs. HDL
You want to be able to access the bits of a fundamental data type.
But the [] operator works on arrays.
If you want to port "billions & billions" of lines of code, then you
have to keep the [] operator as an array, and define a new operator or
base function to access the elements of the type.
Based on my experience, a function to access the n'th bit of an array
is easier to maintain and port then overloading or adding Yet
Uh'nother Crummy Konstruct.
So, > c[5] = a[2] & b[3] ;
would become
bit_set(c, 5) = bit_get(a,2) & bit_get(b, 3);
or better yet
bit_set(c,5, bit_and ( bit_get(a,2) , bit_get(b,3), ...) ;
Note that you have to define the type operators anyway, and you can
either go for more overloading, or make your parsing/translator tasks
easier and use the function notation.
Uh-oh. It's starting to look like EDIF!...
--Richard Vireday
Article: 2976Steve Casselman (sc@temp.vcc.com) wrote: : > From: ejessen@ix.netcom.com (Erik Jessen) : > : > 1) Try implementing everything in VHDL, : This is fine for new programs but I want to be able to port the : "billions and billions" of lines of code already out there. Steve, Abandon all hope of porting compute-intensive code to reconfigurable machines. I've looked at a lot of integer-oriented, compute-intensive algorithms, and although you can often get whiz-bang speed-ups using FPGAs, you can't do it from the C code written for a CPU. The more compute-critical something is, the more people pound on it, and the more machine-specific the code gets. I've spent some time working with people who do speech recognition. CMU has about two decades of software development in speech recognition. Algorithmically, phoneme and word recognition algorithms are integer search techniques, which should be great for FPGAs (with lots of nearby memory.) NONE of that code was useable by me to develop FPGA-based solutions. If you want to know why, you can look at my paper at FCCM last year. (http://www.ece.cmu.edu/afs/ece/usr/herman/.home-page.html) I actually had to go back and start from scratch writing a reduced search algorithm. It did work great, but my source code was a couple of PhD thesis, which can be as easily transcribed into Verilog as into C :). I had the same experience when I played around with fuzzy controllers. To accomplish the same purpose, you write very different algorithms depending on whether you're implementing the system in software or on FPGAs. No one specification, written in any language I know, was general enough to describe how to create efficient software and how to create efficient FPGA implementation. I think the only reason to champion C or some variant is that people are not very familiar with VHDL or Verilog, and they make the assumption (as you did, Steve) that they cannot easily specify algorithms in these languages. Now, I do think that this perception is a big problem for custom computing machines. But it is not the first problem. We don't do a good job now of synthesizing designs from ANY language. Herman ------------------------------------------------ Herman Schmit, Research Engineer Department of Electical and Computer Engineering Carnegie Mellon University 5000 Forbes Ave. Pittsburgh PA 15213 Tel: (412) 268-6642 email: herman@ece.cmu.eduArticle: 2977
In article <313BCDC6.3B31@netcom.com>, vcc <vcc@netcom.com> writes:
> Dave Galloway wrote:
[snip]
> > >(tmcc for short). The tmcc compiler lets you specify the length of each
> > >integer variable by using a C pragma statement. You can specify a 13 bit
> > >addition this way:
[snip]
> >
> > Steve Casselman said:
> > Wouldn't it be better just to say bit a[13], b[13], c[13]; Then
> > I could write c[5] = a[2] & b[3] ;
[snip]
> > In reconfigurable computing, I suspect that 13 bit adds are more common,
> > and that individual bit twiddling is less common. I want to stick with
> > standard C as much as possible, and I don't want to add features unless
> > they are really going to help.
Has anyone considered C's bit-field members? Sure, they're only valid in struct
declarations, but if the user is going to explicitly code for 13-bit values, he/she
can cope with accessing a structure's member.
The following is valid ANSI C code:
#include <stdio.h>
typedef struct { int value:13; } int13;
int main()
{
int13 a,b,c;
a.value = 8000;
b.value = 200;
c.value = a.value + b.value;
printf("%d\n",c.value);
return 0;
}
The value printed is '8', as you would expect from 13-bit addition. The technique
is a little awkward, since you have to access the structure member 'value', but this
could be shortened to 'val' (or even 'v' or '_').
Just wondering,
--Jim
Article: 2978Doug Shade wrote: > > Are there erasable serial PROMs for the Xilinx > family? > > TIA > > Doug Shade > rxjf20@email.sps.mot.com Yes! Check out Atmel's 17C65/128/256. Info at: http://www.atmel.com/atmel/products/products3.html Cheers, ScottArticle: 2979
In article <1996Mar5.164309.18882@jarvis.cs.toronto.edu>,
Dave Galloway <drg@cs.toronto.edu> wrote:
>I'm confused. Surely no one is suggesting a language that claims to be based
>on C, but has different semantics for the same syntax. If you write:
>
> a = input;
> b = a + 6;
> a++;
> c = a;
>
>and input has the value 3, then the results should be a = 4, b = 9 and c = 4
>in any language that is like C. A compiler (even tmcc, which is pretty
>simple) can find the low level parallelism in those statements, and
>generate a circuit that produces the three correct results in parallel, in
>one clock cycle.
Yes, you're right of course. I was trying to say, that I think it's hard
to write parallel programs in a sequential language. Even though the compiler
might catch all the parallelism that is there. Maybe I'm wrong and the quality
of the produced hardware is as good as when you'd use a parallel language like
VHDL.
Regards,
Stefan H-M Ludwig mailto:ludwig@inf.ethz.ch
http://www-cs.inf.ethz.ch/~ludwig
Institute for Computer Systems
Swiss Federal Institute of Technology (ETH)
CH-8092 Zurich, Switzerland
Phone: 41-1-63 27301
Fax : 41-1-63 21307
Article: 2980I have built 24Bit DDS circuits using Xilinx 4000 series and XBLOX, at about your frequency requirement. The 4000 series is nice because of the built in fast carry logic. XBLOX makes the big accumulators etc. easy. I needed analog out, so I included the SIN look up tables, and a noise generator to dither away the unwanted peaks in the output spectrum. If all you want is 1 bit out, your job will be simpler. Dave Decker ddecker@diablores.com 408 730 9555Article: 2981
In article <377cc$131921.86@sj-rsrch.demon.co.uk>, steve@sj.co.uk says... > >A couple of years back, OCCAM was being touted as the language that would >compile well to both opcodes and silicon. There was never any question of >bolting on extensions to permit parallel-aware versions of the language, >they 'just existed'. (and worked, cleanly, not a bodge in sight) > Having used the language a _lot_ in embedded work, and now using VHDL >for a living, I miss the clean nature of OCCAM. Things that used to be >easy are now damn hard, not for any clear reason, more because VHDL feels In fact Ian Page at Oxford and my group at Cornell have languages similar to occam (Ian has lately taken the politically astute path of making his syntax look more like C). In my group we are compiling for data acquisition applications where the primary goal is to move data around and perform accurate timing, but not to perform lots of computation on the data. FPGA's are great for parallel control and moving data around, but pretty poor for arithmetic intensive applications. Geoffrey Brown >that it was never designed to compile to silicon. It's a fine simulation >language, but, as an efficient synthesis tool, I'm losing patience with >it. > This may be because I'm targetting FPGAs, and _care_ about gate counts, >depths of logic, the immense pain of 'just dropping yet another pipeline >stage' into a complex state machine, you name it, it's hard. > There were projects going on into OCCAM compilers to silicon, anyone >know what happened to them? Is it simply that OCCAM wasn't C, so 'must be >bad' or for a real reason? > > Rant over. > > Steve > >Steve Wiseman, Senior H/W Engineer, SJ Research Ltd, Cambridge, England. >steve@sj.co.uk +44 (0) 1223 416715 > >Article: 2982
Dear Colleague,
Below is the advance program for the 1996 ACM/SIGDA Physical Design Workshop,
which is sponsored in part by the U.S. National Science Foundation.
Please note that the the hotel room reservation deadline is March 24,
and the workshop registration deadline is also near, so we encourage
you to register soon.
For more information, please see our WWW home page at:
http://www.cs.virginia.edu/~pdw96/
Please pass along this advance program to your collagues.
Thanks,
Gabe
p.s. The advance program is enclosed in both in ASCII and Latex formats.
======================================================
Name: Prof. Gabriel Robins
General Chair, PDW'96
U.S. Mail: Department of Computer Science
Thornton Hall
University of Virginia
Charlottesville, VA 22903-2442
Phone: (804) 982-2207
FAX: (804) 982-2214
E-mail: robins@cs.virginia.edu
WWW: http://www.cs.virginia.edu/~robins/
======================================================
=============================================================================
ADVANCE PROGRAM
Fifth ACM/SIGDA Physical Design Workshop
April 15-17, 1996 - The Sheraton Reston Hotel, Reston, Virginia USA
http://www.cs.virginia.edu/~pdw96/
The ACM/SIGDA Physical Design Workshop (PDW'96) provides a relaxed
atmosphere for exchange of ideas and promotes research in critical
subareas of physical design for VLSI systems.
This year's workshop emphasizes deep-submicron and high-performance
issues, and also provides a special focus on opportunities in CAD for
micro electromechanical systems (MEMS). There are four outstanding
panel sessions:
(1) future needs and directions for deep-submicron physical design,
(2) physical design needs for MEMS,
(3) manufacturing and yield issues in physical design, and
(4) critical disconnects in design views, data modeling, and back-end
flows (e.g., for physical verification).
There are also many outstanding technical paper sessions.
Free-flowing discussion will be promoted through the limited workshop
attendance, the poster session and the "open commentary" mechanism in
each technical session, as well as a concluding open problems session.
During the workshop, a benchmarks competition will occur in the areas
of netlist partitioning and performance-driven cell placement.
=============================================================================
SUNDAY, APRIL 14
=============================================================================
6:00pm-8:30pm: Registration
(the registration desk will also be open 8:00am-5:00pm on Monday
and 8:00am-12:00pm on Tuesday)
7:00pm-8:30pm: Reception (refreshments provided)
=============================================================================
MONDAY, APRIL 15
=============================================================================
8:30am-8:40am: Welcome
8:40am-10:00am: Session 1, Timing-Driven Interconnect Resynthesis
Interconnect Layout Optimization by Simultaneous Steiner Tree
Construction and Buffer Insertion, T. Okamoto and J. Cong (UC Los Angeles)
Simultaneous Routing and Buffer Insertion for High Performance
Interconnect, J. Lillis, C.-K. Cheng and T.-T. Lin (UC San Diego)
Timing Optimization by Redundancy Addition/Removal, L. Entrena, E. Olias
and J. Uceda (U. Carlos III of Madrid and U. Politecnica of Madrid)
Open Commentary - Moderators: D. Hill (Synopsys),
P. Suaris (Interconnectix)
10:00am-10:20am: Break
10:20am-12:00pm: Session 2, Interconnect Optimization
Optimal Wire-Sizing Formula Under Elmore Delay Model,
C. P. Chen, Y. P. Chen and D. F. Wong (U. Texas Austin)
Reducing Coupled Noise During Routing, A. Vittal and M. Marek-Sadowska
(UC Santa Barbara)
Simultaneous Transistor and Interconnect Sizing Using General
Dominance Property, J. Cong and L. He (UC Los Angeles)
Hierarchical Clock-Network Optimization, D. Lehther, S. Pullela,
D. Blaauw and S. Ganguly (Somerset Design Center and Motorola)
Open Commentary - Moderators: D. Hill (Synopsys),
M. Lorenzetti (Mentor)
12:00pm-2:00pm: Lunch
Workshop Keynote Address: Prof. C. L. Liu, U. of Illinois
Algorithmic Aspects of Physical Design of VLSI Circuits
2:00pm-2:45pm: Session 3, A Tutorial Overview of MEMS
Speaker: K. Gabriel (ARPA)
2:45pm-3:00pm: Break
3:00pm-4:15pm: Session 4, Physical Design for MEMS
Physical Design for Surface Micromachined MEMS, Gary K. Fedder and
Tamal Mukherjee (Carnegie-Mellon U.)
Physical Design Support for MCNC/MUMPS, R. Mahadevan (MCNC)
Synthesis and Extraction for MEMS Design, E. Berg, N. Lo and
K. Pister (UC Los Angeles)
4:15pm-4:30pm: Break
4:30pm-6:00pm: Session 5, Panel: Physical Design Needs for MEMS
Moderator: K. Pister (UC Los Angeles)
Panelists include:
S. Bart (Analog Devices)
G. Fedder (Carnegie-Mellon U.)
K. Gabriel (ARPA)
I. Getreu (Analogy)
R. Grafton (NSF)
R. Mahadevan (MCNC)
J. Tanner (Tanner Research)
6:00pm-8:00pm: Dinner
8:00pm-9:30pm: Session 6, Panel: Deep-Submicron Physical Design:
Future Needs and Directions
Panelists include:
T. C. Lee (former VP Eng, SVR; President/CEO, Neo Paradigm Labs)
L. Scheffer (Architect, Cadence)
W. Vercruysse (UltraSPARC III CAD Manager, Sun)
M. Wiesel (CAD Manager, Intel)
T. Yin (VP R&D, Avant!)
=============================================================================
TUESDAY, APRIL 16
=============================================================================
8:30am-9:50am: Session 7, Partitioning
VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement
Techniques, S. Dutt and W. Y. Deng (U. Minnesota and LSI Logic)
A Hybrid Multilevel/Genetic Approach for Circuit Partitioning,
C. J. Alpert, L. Hagen and A. B. Kahng (UC Los Angeles and Cadence)
Min-Cut Replication for Delay Reduction, J. Hwang and A. El Gamal
(Xilinx and Stanford U.)
Open Commentary - Moderators: J. Frankle (Xilinx),
L. Scheffer (Cadence)
9:30am-10:10am: Break
10:10am-11:50am: Session 8, Topics in Hierarchical Design
Two-Dimensional Datapath Regularity Extraction, R. Nijssen and
J. Jess (TU Eindhoven)
Hierarchical Net Length Estimation, G. Zimmermann (U. Kaiserslautern)
Exploring the Design Space for Building-Block Placements Considering
Area, Aspect Ratio, Path Delay and Routing Congestion, H. Esbensen and
E. S. Kuh (UC Berkeley)
Genetic Simulated Annealing and Application to Non-Slicing Floorplan
Design, S. Koakutsu, M. Kang and W. W.-M. Dai (Chiba U. and UC Santa Cruz)
Open Commentary
11:50pm-1:30pm: Lunch
1:30pm-3:00pm: Session 9, Poster Session
Physical Layout for Three-Dimensional FPGAs, M. J. Alexander, J. P.
Cohoon, J. Colflesh, J. Karro, E. L. Peters and G. Robins (U. of Virginia)
Efficient Area Minimization for Dynamic CMOS Circuits, B. Basaran
and R. Rutenbar (Carnegie-Mellon U.)
A Fast Technique for Timing-Driven Placement Re-engineering,
M. Hossain, B. Thumma and S. Ashtaputre (Compass Design Automation)
An Approach to Layout and Process Verification for Microsystem,
Physical Design, K. Hahn and R. Bruck (U. Dortmund)
Computer Aided Micro-Machining for Wet Etch Fabrication,
M. K. Long, J. W. Burdick and T. J. Hubbard (Caltech)
Over-the-Cell Routing with Vertical Floating Pins, I. Peters, P. Molitor
and M. Weber (U. Halle and Deuretzbacher Research GmbH)
Congestion- Balanced Placement for FPGAs, R. Sun, R. Gupta and C. L. Liu
(Altera and U. Illinois)
Fanout Problems in FPGA, K.-H. Tsai, M. Marek-Sadowska and S. Kaptanoglu
(UC Santa Barbara and Actel)
An Optimal Pairing and Chaining Algorithm for Layout Generation,
J. Velasco, X. Marin, R. P. Llopis and J. Carrabina (IMB-CNM
U. Autonoma de Barcelona, Philips Research Labs Eindhoven)
Clock-Delayed Domino in Adder and Random Logic Design, G. Yee and
C. Sechen (U. Washington)
3:00pm-4:00pm: Session 10, Manufacturing/Yield Issues I
Layout Design for Yield and Reliability, K. P. Wang, M. Marek-Sadowska
and W. Maly (UC Santa Barbara and Carnegie-Mellon U.)
Yield Optimization in Physical Design, V. Chiluvuri (Motorola)
(invited survey paper)
4:00pm-4:15pm: Break
4:15pm-5:45pm: Session 11, Panel: Manufacturing/Yield Issues II
Panelists include:
V. Chiluvuri (Motorola)
I. Koren (U. Massachusetts Amherst)
J. Burns (IBM Watson Research Center)
W. Maly (Carnegie-Mellon U.)
5:45pm-7:30pm: Dinner
7:30pm-9:30pm: Session 12, Panel: Design Views, Data Modeling and
Flows: Critical Disconnects
A Talk by C. Sechen (U. Washington)
A Gridless Multi-Layer Channel Router Based on Combined Constraint Graph
and Tile Expansion Approach, H.-P. Tseng and C. Sechen (U. Washington)
A Multi-Layer Chip-Level Global Route, L.-C. E. Liu and C. Sechen
(U. Washington)
Panelists include:
W. W.-M. Dai (UC Santa Cruz, VP Ultima Interconnect Technologies)
L. Jones (Motorola)
D. Lapotin (IBM Austin Research Center)
E. Nequist (VP R&D, Cooper & Chyan)
R. Rohrer (Chief Scientist, Avant!)
P. Sandborn (VP, Savantage)
=============================================================================
WEDNESDAY, APRIL 17
=============================================================================
8:30am-9:50am: Session 13, Performance-Driven Design
A Graph-Based Delay Budgeting Algorithm for Large Scale Timing-Driven
Placement Problems, G. Tellez, D. A. Knol and M. Sarrafzadeh
(Northwestern U.)
Reduced Sensitivity of Clock Skew Scheduling to Technology Variations,
J. L. Neves and E. G. Friedman (U. Rochester)
Multi-Layer Pin Assignment for Macro Cell Circuits, L.-C. E. Liu and
C. Sechen (U. Washington)
Open Commentary
9:50pm-10:10pm: Break
10:10am-11:30am: Session 14, Topics in Layout
Constraint Relaxation in Graph-Based Compaction, S. K. Dong, P. Pan,
C. Y. Lo and C. L. Liu (Silicon Graphics, Clarkson U., Lucent, U. Illinois)
An O(n) Algorithm for Transistor Stacking with Performance Constraints,
B. Basaran and R. Rutenbar (Carnegie-Mellon U.)
Efficient Standard Cell Generation When Diffusion Strapping is Required,
B. Guan and C. Sechen (Silicon Graphics and U. Washington)
Open Commentary - Moderator: A. Domic (Cadence)
11:30am-12:00pm: Session 15, Open Problems
Moderators: A. B. Kahng (UC Los Angeles), B. Preas (Xerox PARC)
12:00pm-2:00pm: Lunch (and benchmark competition results)
2:00pm: Workshop adjourns
=============================================================================
TRAVEL AND ACCOMODATIONS
=============================================================================
PDW '96 is being held at the Sheraton Reston in Reston, Virginia, near
Washington, D.C. The hotel is minutes from Dulles International
Airport (IAD), and 24-hour courtesy shuttles are available from the
airport to the hotel. The area is also served by Washington National
Airport (DCA), about 20 miles away, and Baltimore-Washington
International Airport (BWI), about 50 miles away.
The Sheraton Reston is located at:
11810 Sunrise Valley Drive
Reston, Virginia 22091
phone: 703-620-9000
fax: 703-860-1594
reservations: 800-392-ROOM
*** Please make your room reservation directly with the Reston ***
*** Sheraton hotel. ***
Driving directions from Dulles Airport: take the Washington Dulles
Access and Toll Road (route 267) to the Reston Parkway Exit (3). Turn
right at the light after paying toll. Take the next left onto Sunrise
Valley Drive, and continue for a couple blocks to the Sheraton (on
your left).
A block of rooms is being held for the nights of Sunday through
Wednesday (April 14 through April 17). Room rates are $95 per night
for single occupancy, and $105 per night for double occupancy. The
number of rooms available at these rates is limited, and they are only
being held through March 24 (so early registration is highly
recommended).
The Washington D.C. weather tends to be chilly in April, so warm dress
is suggested for the outdoors.
=============================================================================
SIGHTSEEING AND ATTRACTIONS
=============================================================================
The Nation's Capitol offers much in the way of sightseeing. The most
popular destinations are located in downtown Washington D.C.,
surrounding several square miles of park area known as the "National
Mall." There is no charge to visit the National Memorials located on
the Mall, which include the Washington Monument, where you may ascend
555 feet to an observation post; the Lincoln Memorial, whose design
adorns the back of the US penny; the Jefferson Memorial, which
includes a 19-foot bronze statue of Thomas Jefferson; and the Vietnam
Memorial, a long wall of black Indian granite dedicated in 1982.
The Smithsonian Institution (telephone (202) 357-2700) operates a
number of superb museums that flank the National Mall, including:
Freer Gallery of Art (Asian and 19th and 20th-century American art)
Hirshhorn Museum and Sculpture Garden (modern and contemporary art)
National Air and Space Museum (history of aviation and space exploration)
National Museum of African Art (collection and study of African art)
National Museum of American Art (paintings, graphics, and photography)
National Museum of American History (technology and culture in America)
National Museum of Natural History (history of the natural world)
National Portrait Gallery (portraits of distinguished americans)
National Postal Museum (history of postal communication and philately)
Sackler Gallery of Asian art (from ancient to present)
Other attractions and tours around the D.C. area include (please call
the numbers below for schedules):
Arlington National Cemetary (703) 697-2131
Bureau of Engraving and Printing (202) 622-2000
Congressional buildings (202) 225-6827
FBI Headquarters (202) 324-3447
Library of Congress (202) 707-5000
National Aquarium (202) 482-2825
National Archives (202) 501-5000
National Zoological Park (202) 673-4821
The Pentagon (703) 695-1776
Supreme Court (202) 479-3030
Treasury Department (202) 622-2000
The White House (202) 456-7041
There are a number of reasonably priced eating places on the Mall; the
East Wing of National Gallery and the Air and Space Museums offer good
food and a place to sit down after sightseeing. Provisions will be
made for low-cost transportation to and from the Mall and downtown
Washington D.C., so bring your camera and strolling shoes and enjoy
our Nation's Capital!
=============================================================================
WORKSHOP ORGANIZATION
=============================================================================
General Chair:
G. Robins (U. of Virginia)
Technical Program Committee:
C. K. Cheng (UC San Diego)
J. P. Cohoon (U. of Virginia)
J. Cong (UC Los Angeles)
A. Domic (Cadence)
J. Frankle (Xilinx)
E. Friedman (Rochester)
D. Hill (Synopsys)
L. Jones (Motorola)
A. B. Kahng (UC Los Angeles, Chair)
Y.-L. Lin (Tsing Hua)
K. Pister (UC Los Angeles)
M. Marek-Sadowska (UC Santa Barbara)
C. Sechen (Washington)
R.-S. Tsay (Avant!)
G. Zimmermann (Kaiserslautern)
Steering Committee:
M. Lorenzetti (Mentor Graphics)
B. Preas (Xerox PARC)
Keynote Address:
C. L. Liu (Illinois)
Benchmarks Co-Chairs:
F. Brglez (NCSU)
W. Swartz (TimberWolf Systems)
Local Arrangements Chair:
M. J. Alexander (U. of Virginia)
Treasurer:
S. B. Souvannavong (HIMA)
Publicity Chair:
J. L. Ganley (Cadence)
Sponsors:
ACM / SIGDA
U.S. National Science Foundation
Avant! Corporation
=============================================================================
WORKSHOP REGISTRATION
=============================================================================
Fifth ACM/SIGDA Physical Design Workshop
April 15-17, 1996 - The Sheraton Reston Hotel, Reston, Virginia USA
Name: _______________________________________________________________
Company/University: _________________________________________________
Title: ______________________________________________________________
Address: ____________________________________________________________
City: _________________________________________ State: ______________
Phone: ____________________________ Email: __________________________
Registration Fees (Includes All Meals)
Advance (Through April 1) Late (After April 1/On-Site)
ACM Members __ $355 __ $440
Non-ACM __ $455 __ $540
Students __ $250 __ $250
ACM Membership Number: _____________________________
Dietary restrictions, if any: ______________________
Special needs: _____________________________________
The registration fee includes the workshop proceedings and all meals
(i.e., 3 breakfasts, 3 lunches, and 2 dinners), refreshments during
breaks, and a reception on Sunday evening. The total number of
attendees is limited (registrations will be returned if the workshop
is oversubscribed).
*** Note: Hotel reservations must be made directly with the Sheraton ***
*** (see above). ***
The only acceptable forms of payment are checks (personal, company,
and certified/bank checks) in US funds drawn on a US bank and made
payable to "Physical Design Workshop 1996" (credit cards will not be
accepted). Payment must accompany your registration. No FAX or Email
registrations will be processed.
Please mail your payment (checks only) along with this registration form to:
Sally Souvannavong, Treasurer
1996 ACM/SIGDA Physical Design Workshop
Department of Computer Science
Thornton Hall
University of Virginia
Charlottesville, VA 22903-2442 USA
Phone: (804) 982-2200
Email: pdw96@cs.virginia.edu
Cancellations must be in writing and must be received by March 31, 1996.
=============================================================================
The following is a Latex version of the PDW '96 advance program.
=============================================================================
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\begin{document}
$~$
\vspace{-0.0in}
\header{Advance Program}
\begin{center}
\vspace{0.1in}
{\Large\bf Fifth ACM/SIGDA Physical Design Workshop} \\
\vspace{0.1in}
{\large April 15--17, 1996 --- The Sheraton Reston Hotel, Reston, Virginia USA}
{\tt\large http://www.cs.virginia.edu/$_{\large\bf\tilde{~}}$pdw96/}
\end{center}
\progspace
The ACM/SIGDA Physical Design Workshop (PDW'96) provides a relaxed
atmosphere for exchange of ideas and promotes research in critical
subareas of physical design for VLSI systems.
\progspace
This year's workshop emphasizes deep-submicron and high-performance
issues, and also provides a special focus on opportunities in CAD for
micro electromechanical systems (MEMS). There are four outstanding
panel sessions:
(1) future needs and directions for deep-submicron physical design,
(2) physical design needs for MEMS,
(3) manufacturing and yield issues in physical design, and
(4) critical disconnects in design views, data modeling, and back-end flows
(e.g., for physical verification).
\progspace
There are also many outstanding technical paper sessions.
Free-flowing discussion will be promoted through the limited workshop
attendance, the poster session and the ``open commentary'' mechanism
in each technical session, as well as a concluding open problems
session. During the workshop, a benchmarks competition will occur in
the areas of netlist partitioning and performance-driven cell
placement.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\dsep
\header{Sunday, April 14}
\dsep
\myevent{6:00pm--8:30pm}{Registration}{}
(the registration desk will also be open 8:00am-5:00pm on Monday
and 8:00am-12:00pm on Tuesday)
\myevent{7:00pm--8:30pm}{Reception}{(refreshments provided)}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\dsep
\header{Monday, April 15}
\dsep
\myevent{8:30am--8:40am}{Welcome}{}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{1}{Timing-Driven Interconnect Resynthesis}{8:40am--10:00am}
{Session Chair}{XXX}{XXX}
\mylist
\mypaper{T. Okamoto and J. Cong}{UC Los Angeles}
{Interconnect Layout Optimization by Simultaneous Steiner Tree
Construction and Buffer Insertion}
\mypaper{J. Lillis, C.-K. Cheng and T.-T. Lin}{UC San Diego}{Simultaneous
Routing and Buffer Insertion for High Performance Interconnect}
\mypaper{L. Entrena, E. Olias and J. Uceda}{U. Carlos III of Madrid and U.
Politecnica of Madrid}{Timing Optimization by Redundancy
Addition/Removal}
\item Open Commentary -- Moderators: D. Hill (Synopsys),
P. Suaris (Interconnectix)
\end{list}
\progspace
\mybreak{10:00am--10:20am}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\newpage
\progspace
\NewSessionN{2}{Interconnect Optimization}{10:20am--12:00pm}
{Session Chair}{XXX}{XXX}
\mylist
\mypaper{C. P. Chen, Y. P. Chen and D. F. Wong}{U. Texas Austin}{Optimal
Wire-Sizing Formula Under Elmore Delay Model}
\mypaper{A. Vittal and M. Marek-Sadowska}{UC Santa Barbara}{Reducing Coupled
Noise During Routing}
\mypaper{J. Cong and L. He}{UC Los Angeles}{Simultaneous Transistor and
Interconnect Sizing Using General Dominance Property}
\mypaper{D. Lehther, S. Pullela, D. Blaauw and S. Ganguly}{Somerset Design
Center and Motorola}{Hierarchical Clock-Network Optimization}
\item Open Commentary -- Moderators: D. Hill (Synopsys), M. Lorenzetti (Mentor)
\end{list}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\mylunch{12:00pm--2:00pm}{}
{\large {\bf Workshop Keynote Address}: {\bf Prof. C. L. Liu}, U. of
Illinois\\ {\em Algorithmic Aspects of Physical Design of VLSI Circuits}}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{3}{A Tutorial Overview of MEMS}{2:00pm--2:45pm}{Speaker}
{K. Gabriel}{ARPA}
\progspace
\mybreak{2:45pm--3:00pm}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{4}{Physical Design for MEMS}{3:00pm--4:15pm}{Session Chair}
{K. Gabriel}{ARPA}
\mylist
\mypaper{Gary K. Fedder and Tamal Mukherjee}{Carnegie-Mellon U.}
{Physical Design for Surface Micromachined MEMS}
\mypaper{R. Mahadevan}{MCNC}{Physical Design Support for MCNC/MUMPS}
\mypaper{E. Berg, N. Lo and K. Pister}{UC Los Angeles}
{Synthesis and Extraction for MEMS Design}
\end{list}
\progspace
\mybreak{4:15pm--4:30pm}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{5}{Panel: Physical Design Needs for MEMS}{4:30-6:00pm}
{Moderator}{K. Pister}{UC Los Angeles}
Panelists include:
\mylist
\item S. Bart (Analog Devices)
\item G. Fedder (Carnegie-Mellon U.)
\item K. Gabriel (ARPA)
\item I. Getreu (Analogy)
\item R. Grafton (NSF)
\item R. Mahadevan (MCNC)
\item J. Tanner (Tanner Research)
% \item S. Senturia (MIT)
\end{list}
\progspace
\mydinner{6:00pm--8:00pm}{}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\newpage
\progspace
\NewSessionN{6}{Panel: Deep-Submicron Physical Design:
Future Needs and Directions}{8:00pm--9:30pm}
{Moderator}{XXX}{XXX}
Panelists include:
\mylist
\item T. C. Lee (former VP Eng, SVR; President/CEO, Neo Paradigm Labs)
\item L. Scheffer (Architect, Cadence)
\item W. Vercruysse (UltraSPARC III CAD Manager, Sun)
\item M. Wiesel (CAD Manager, Intel)
\item T. Yin (VP R\&D, Avant!)
\end{list}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\dsep
\header{Tuesday, April 16}
\dsep
\progspace
\NewSessionN{7}{Partitioning}{8:30am--9:50am}
{Session Chair}{XXX}{XXX}
\mylist
\mypaper{S. Dutt and W. Y. Deng}{U. Minnesota and LSI Logic}{VLSI Circuit
Partitioning by Cluster-Removal Using Iterative Improvement Techniques}
\mypaper{C. J. Alpert, L. Hagen and A. B. Kahng}{UC Los Angeles and Cadence}{A
Hybrid Multilevel/Genetic Approach for Circuit Partitioning}
\mypaper{J. Hwang and A. El Gamal}{Xilinx and Stanford U.}{Min-Cut
Replication for Delay Reduction}
\item
Open Commentary -- Moderators: J. Frankle (Xilinx), L. Scheffer (Cadence)
\end{list}
\progspace
\mybreak{9:50am--10:10am}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{8}{Topics in Hierarchical Design}{10:10am--11:50am}
{Session Chair}{XXX}{XXX}
\mylist
\mypaper{R. Nijssen and J. Jess}{TU Eindhoven}{Two-Dimensional Datapath
Regularity Extraction}
\mypaper{G. Zimmermann}{U. Kaiserslautern}{Hierarchical Net Length Estimation}
\mypaper{H. Esbensen and E. S. Kuh}{UC Berkeley}{Exploring the Design Space for
Building-Block Placements Considering Area, Aspect Ratio, Path Delay
and Routing Congestion}
\mypaper{S. Koakutsu, M. Kang and W. W.-M. Dai}{Chiba U. and UC Santa
Cruz}{Genetic Simulated Annealing and Application to Non-Slicing
Floorplan Design}
\item Open Commentary % XXX -- Moderators:
\end{list}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\mylunch{11:50pm--1:30pm}{}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{9}{Poster Session}{1:30pm--3:00pm}
{Session Chair}{XXX}{XXX}
\mylist
\mypaper{M. J. Alexander, J. P. Cohoon, J. Colflesh, J. Karro, E. L. Peters and
G. Robins}{U. of Virginia}{Physical Layout for Three-Dimensional
FPGAs}
\mypaper{B. Basaran and R. Rutenbar}{Carnegie-Mellon U.}{Efficient Area
Minimization for Dynamic CMOS Circuits}
\mypaper{M. Hossain, B. Thumma and S. Ashtaputre}{Compass Design Automation}{A
Fast Technique for Timing-Driven Placement Re-engineering}
\mypaper{K. Hahn and R. Bruck}{U. Dortmund}
{An Approach to Layout and Process Verification for Microsystem
Physical Design}
\mypaper{M. K. Long, J. W. Burdick and T. J. Hubbard}{Caltech}
{Computer Aided Micro-Machining for Wet Etch Fabrication}
\mypaper{I. Peters, P. Molitor and M. Weber}{U. Halle and Deuretzbacher
Research GmbH}{Over-the-Cell Routing with Vertical Floating Pins}
\mypaper{R. Sun, R. Gupta and C. L. Liu}{Altera and U.
Illinois}{Congestion-Balanced Placement for FPGAs}
\mypaper{K.-H. Tsai, M. Marek-Sadowska and S. Kaptanoglu}{UC Santa Barbara and
Actel}{Fanout Problems in FPGA}
\mypaper{J. Velasco, X. Marin, R. P. Llopis and J. Carrabina}{IMB-CNM U.
Autonoma de Barcelona, Philips Research Labs Eindhoven}{An Optimal
Pairing and Chaining Algorithm for Layout Generation}
\mypaper{G. Yee and C. Sechen}{U. Washington}{Clock-Delayed Domino in Adder
and Random Logic Design}
\end{list}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{10}{Manufacturing/Yield Issues~I}{3:00pm--4:00pm}
{Session Chair}{XXX}{XXX}
\mylist
\mypaper{K. P. Wang, M. Marek-Sadowska and W. Maly}{UC Santa Barbara and
Carnegie-Mellon U.}{Layout Design for Yield and Reliability}
\mypaper{V. Chiluvuri}{Motorola}{Yield Optimization in Physical Design}
(invited survey paper)
\end{list}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\mybreak{4:00pm--4:15pm}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{11}{Panel: Manufacturing/Yield
Issues~II}{4:15pm--5:45pm}{Moderator}{XXX}{XXX}
Panelists include:
\mylist
% XXX missing names / affiliations here:
\item V. Chiluvuri (Motorola)
\item I. Koren (U. Massachusetts Amherst)
\item J. Burns (IBM Watson Research Center)
\item W. Maly (Carnegie-Mellon U.)
\end{list}
\progspace
\mydinner{5:45pm--7:30pm}{}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSession{12}{Panel: Design Views, Data Modeling and Flows: Critical
Disconnects}{7:30pm--9:30pm}{A Talk by}{C. Sechen}{U. Washington}
\mylist
\mypaper{H.-P. Tseng and C. Sechen}{U. Washington}{A Gridless Multi-Layer
Channel Router Based on Combined Constraint Graph and Tile Expansion Approach}
\mypaper{L.-C. E. Liu and C. Sechen}{U. Washington}{A Multi-Layer Chip-Level
Global Route}
\end{list}
\newpage
Panelists include:
\mylist
\item W. W.-M. Dai (UC Santa Cruz, VP Ultima Interconnect
Technologies)
\item L. Jones (Motorola)
\item D. Lapotin (IBM Austin Research Center)
\item E. Nequist (VP R\&D, Cooper \& Chyan)
\item R. Rohrer (Chief Scientist, Avant!)
\item P. Sandborn (VP, Savantage)
\end{list}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\dsep
\header{Wednesday, April 17}
\dsep
\NewSessionN{13}{Performance-Driven Design}{8:30am--9:50am}{XXX}{XXX}{XXX}
\mylist
\mypaper{G. Tellez, D. A. Knol and M. Sarrafzadeh}{Northwestern U.}{A
Graph-Based Delay Budgeting Algorithm for Large Scale Timing-Driven
Placement Problems}
\mypaper{J. L. Neves and E. G. Friedman}{U. Rochester}{Reduced Sensitivity of
Clock Skew Scheduling to Technology Variations}
\mypaper{L.-C. E. Liu and C. Sechen}{U. Washington}{Multi-Layer Pin Assignment
for Macro Cell Circuits}
\item Open Commentary % -- Moderator: XXX
\end{list}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\mybreak{9:50pm--10:10pm}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{14}{Topics in Layout}{10:10am--11:30am}{XXX}{XXX}{XXX}
\mylist
\mypaper{S. K. Dong, P. Pan, C. Y. Lo and C. L. Liu}{Silicon Graphics,
Clarkson U., Lucent, U. Illinois}{Constraint Relaxation in Graph-Based
Compaction}
\mypaper{B. Basaran and R. Rutenbar}{Carnegie-Mellon U.}{An $O(n)$ Algorithm
for Transistor Stacking with Performance Constraints}
\mypaper{B. Guan and C. Sechen}{Silicon Graphics and U. Washington}{Efficient
Standard Cell Generation When Diffusion Strapping is Required}
\item Open Commentary -- Moderator: A. Domic (Cadence)
\end{list}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\NewSessionN{15}{Open Problems}{11:30am--12:00pm}{XXX}{XXX}{XXX}
Moderators: A. B. Kahng (UC Los Angeles), B. Preas (Xerox PARC)
\progspace
\mylunch{12:00pm--2:00pm}{(and benchmark competition results)}
\progspace
\myevent{2:00pm}{Workshop adjourns}{}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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{
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\newpage
$~$
\vspace{-0.0in}
\dsep
\header{Travel and Accommodations}
\dsep
PDW '96 is being held at the Sheraton Reston in Reston, Virginia, near
Washington, D.C. The hotel is minutes from Dulles International
Airport (IAD), and 24-hour courtesy shuttles are available from the
airport to the hotel. The area is also served by Washington National
Airport (DCA), about 20 miles away, and Baltimore-Washington
International Airport (BWI), about 50 miles away.
The Sheraton Reston is located at:
\begin{quote}
11810 Sunrise Valley Drive \\
Reston, Virginia 22091 \\
phone: 703--620--9000 \\
fax: 703--860--1594 \\
reservations: 800--392--ROOM
\end{quote}
{\bf Please make your room reservation directly with the Reston
Sheraton hotel.}
Driving directions from Dulles Airport: take the Washington Dulles
Access and Toll Road (route 267) to the Reston Parkway Exit (3). Turn
right at the light after paying toll. Take the next left onto Sunrise
Valley Drive, and continue for a couple blocks to the Sheraton (on
your left).
A block of rooms is being held for the nights of Sunday through
Wednesday (April 14 through April 17). Room rates are \$95 per night
for single occupancy, and \$105 per night for double occupancy. The
number of rooms available at these rates is limited, and they are only
being held through {\bf March 24} (so early registration is highly
recommended).
The Washington D.C. weather tends to be chilly in April, so warm dress
is suggested for the outdoors.
% XXX Check the average D.C. weather with some weather bureau! - GR
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\progspace
\dsep
\header{Sightseeing and Attractions}
\dsep
The Nation's Capitol offers much in the way of sightseeing. The most
popular destinations are located in downtown Washington D.C.,
surrounding several square miles of park area known as the ``National
Mall''. There is no charge to visit the National Memorials located on
the Mall, which include the Washington Monument, where you may ascend
$555$ feet to an observation post; the Lincoln Memorial, whose design
adorns the back of the US penny; the Jefferson Memorial, which
includes a 19-foot bronze statue of Thomas Jefferson; and the Vietnam
Memorial, a long wall of black Indian granite dedicated in 1982.
The Smithsonian Institution (telephone (202) 357-2700) operates a number of
superb museums that flank the National Mall, including:
\mylist
\item Freer Gallery of Art (Asian and 19th and 20th-century American art)
\item Hirshhorn Museum and Sculpture Garden (modern and contemporary art)
\item National Air and Space Museum (history of aviation and space exploration)
\item National Museum of African Art (collection and study of African art)
\item National Museum of American Art (paintings, graphics, and photography)
\item National Museum of American History (technology and culture in America)
\item National Museum of Natural History (history of the natural world)
\item National Portrait Gallery (portraits of distinguished americans)
\item National Postal Museum (history of postal communication and philately)
\item Sackler Gallery of Asian art (from ancient to present)
\end{list}
Other attractions and tours around the D.C. area include (please call the
numbers below for schedules):
\mylist
\item Arlington National Cemetary (703) 697-2131
\item Bureau of Engraving and Printing (202) 622-2000
\item Congressional buildings (202) 225-6827
\item FBI Headquarters (202) 324-3447
\item Library of Congress (202) 707-5000
\item National Aquarium (202) 482-2825
\item National Archives (202) 501-5000
\item National Zoological Park (202) 673-4821
\item The Pentagon (703) 695-1776
\item Supreme Court (202) 479-3030
\item Treasury Department (202) 622-2000
\item The White House (202) 456-7041
\end{list}
There are a number of reasonably priced eating places on the Mall; the
East Wing of National Gallery and the Air and Space Museums offer good
food and a place to sit down after sightseeing. Provisions will be
made for low-cost transportation to and from the Mall and downtown
Washington D.C., so bring your camera and strolling shoes and enjoy
our Nation's Capital!
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\dsep
\header{Workshop Organization}
\dsep
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\def\sss{0.05in}
\begin{center}
\fbox{
\parbox{3.5in}{
\begin{tabbing}
Al\= Al\= \kill
{\bf General Chair:} \\[\s]
\> G. Robins {\it (U. of Virginia)} \\[\sss]
{\bf Technical Program Committee:} \\[0.07in]
\> C. K. Cheng {\it (UC San Diego) } \\[\ss]
\> J. P. Cohoon {\it (U. of Virginia)} \\[\ss]
\> J. Cong ({\it UC Los Angeles}) \\[\ss]
\> A. Domic {\it (Cadence) }\\[\ss]
\> J. Frankle {\it (Xilinx) }\\[\ss]
\> E. Friedman {\it (Rochester)} \\[\ss]
\> D. Hill {\it (Synopsys)} \\[\ss]
\> L. Jones {\it (Motorola)} \\[\ss]
\> A. B. Kahng {\it (UC Los Angeles, Chair)} \\[\ss]
\> Y.-L. Lin {\it (Tsing Hua) } \\[\ss]
\> K. Pister {\it (UC Los Angeles) } \\[\ss]
\> M. Marek-Sadowska {\it (UC Santa Barbara)} \\[\ss]
\> C. Sechen {\it (Washington)} \\[\ss]
\> R.-S. Tsay {\it (Avant!)} \\[\ss]
\> G. Zimmermann \ {\it (Kaiserslautern) }
\end{tabbing}
}
$~~~~~$
\parbox{3.5in}{
\begin{tabbing}
Al\= Al\= \kill
{\bf Steering Committee:} \\[\s]
\> M. Lorenzetti {\it (Mentor Graphics) } \\[\ss]
\> B. Preas {\it (Xerox PARC) } \\[\sss]
{\bf Keynote Address:}\\[\s]
\> C. L. Liu {\it (Illinois)} \\[\sss]
{\bf Benchmarks Co-Chairs:}\\[\s]
\> F. Brglez {\it (NCSU)}\\[\s]
\> W. Swartz {\it (TimberWolf Systems)}\\[\sss]
{\bf Local Arrangements Chair:}\\[\s]
\> M. J. Alexander {\it (U. of Virginia)}\\[\sss]
{\bf Treasurer:}\\[\s]
\> S. B. Souvannavong {\it (HIMA)}\\[\sss]
{\bf Publicity Chair:}\\[\s]
\> J. L. Ganley {\it (Cadence)}\\[\sss]
{\bf Sponsors:}\\[\s]
\> ACM / SIGDA \\[\s]
\> U.S. National Science Foundation \\[\s]
\> Avant! Corporation \\[\s]
\end{tabbing}
}
}
\end{center}
%\vspace{0.1in}
%\begin{center}
%{\tt\large http://www.cs.virginia.edu/$_{\large\bf\tilde{~}}$pdw96/}\\
%{\tt\large pdw96@cs.virginia.edu}
%\end{center}
}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\newpage
$~$
\vspace{-0.5in}
\header{Workshop Registration}
\begin{center}
{\Large\bf Fifth ACM/SIGDA Physical Design Workshop} \\
\vspace{0.1in}
{\large April 15--17, 1996 --- The Sheraton Reston Hotel, Reston, Virginia USA}
\end{center}
\vspace{-0.05in}
Name: \rule{5in}{0.01in} \\
\vspace{-0.05in}
Company/University: \rule{4.1in}{0.01in} \\
\vspace{-0.05in}
Title: \rule{5.07in}{0.01in} \\
\vspace{-0.05in}
Address: \rule{4.9in}{0.01in} \\
\vspace{-0.05in}
City: \rule{3in}{0.01in} State: \rule{1.65in}{0.01in} \\
\vspace{-0.05in}
Phone: \rule{2in}{0.01in} Email: \rule{2.48in}{0.01in}
\vspace{0.3in}
\header{Registration Fees (Includes All Meals)}
\begin{center}
\begin{tabular}{ccc}
\vspace{0.1in}
& Advance (Through April 1) & Late (After April 1) and On-Site \\
\vspace{0.1in}
ACM Members & \mybox \$355 & \mybox \$440 \\
\vspace{0.1in}
Non-ACM members & \mybox \$455 & \mybox \$540 \\
\vspace{0.1in}
Students & \mybox \$250 & \mybox \$250
\end{tabular}
\end{center}
\vspace{0.1in}
ACM Membership Number: \rule{4.15in}{0.01in}
\vspace{0.01in}
Dietary restrictions, if any: \rule{4.18in}{0.01in}
\vspace{0.01in}
Special needs: \rule{5.0in}{0.01in} \\
The registration fee includes the workshop proceedings and all meals (i.e., 3
breakfasts, 3 lunches, and 2 dinners), refreshments during breaks, and a
reception on Sunday evening. The total
number of attendees is limited (registrations will be returned if the workshop
is oversubscribed).
{\bf Note: Hotel reservations must be made directly with the Sheraton (see
above).}
The only acceptable forms of payment are checks (personal, company,
and certified/bank checks) in US funds drawn on a US bank and made
payable to ``Physical Design Workshop 1996'' (credit cards {\bf will
not} be accepted). Payment must accompany your registration. No FAX
or Email registrations will be processed.
{\bf Please mail your payment (checks only) along with this
registration form to: }
\begin{quote}
Sally Souvannavong, Treasurer\\
1996 ACM/SIGDA Physical Design Workshop \\
Department of Computer Science \\
Thornton Hall \\
University of Virginia \\
Charlottesville, VA 22903-2442 USA \\ $~$\\
Phone: (804) 982-2200 \\
Email: pdw96@cs.virginia.edu
\end{quote}
Cancellations must be in writing and must be received by March 31, 1996.
\end{document}
=============================================================================
Article: 2983
Steve Wiseman (steve@sj.co.uk) wrote:
: A couple of years back, OCCAM was being touted as the language that would
: compile well to both opcodes and silicon. There was never any question of
: bolting on extensions to permit parallel-aware versions of the language,
: they 'just existed'. (and worked, cleanly, not a bodge in sight)
: Having used the language a _lot_ in embedded work, and now using VHDL
: for a living, I miss the clean nature of OCCAM. Things that used to be
: easy are now damn hard, not for any clear reason, more because VHDL feels
: that it was never designed to compile to silicon. It's a fine simulation
: language, but, as an efficient synthesis tool, I'm losing patience with
: it.
: This may be because I'm targetting FPGAs, and _care_ about gate counts,
: depths of logic, the immense pain of 'just dropping yet another pipeline
: stage' into a complex state machine, you name it, it's hard.
: There were projects going on into OCCAM compilers to silicon, anyone
: know what happened to them? Is it simply that OCCAM wasn't C, so 'must be
: bad' or for a real reason?
: Rant over.
: Steve
: Steve Wiseman, Senior H/W Engineer, SJ Research Ltd, Cambridge, England.
: steve@sj.co.uk +44 (0) 1223 416715
The projects still exist, or at least some do. See for instance:
http://www.comlab.ox.ac.uk/oucl/hwcomp.html
which describes the work on hardware compilation going on in the Oxford
University Computing Laboratory. It's no coincidence that Oxford University
has a long history of work on sensible languages for parallel programming
and also chose a version of occam for use as a hardware description
language. You may be interested to know that they also "target FPGAs, and
_care_ about gate counts...".
As regards public acceptance, you may be right, it might simply be that
"OCCAM wasn't C", although it's probably more a case of "Not Invented There"
i.e. on the other side of the atlantic.
I should probably say that I'm an ex-employee of both Inmos and OUCL, so I
might not be completely impartial...
Anthony Stansfield.
Article: 2984
In article <4hpbpo$4o2@newsstand.cit.cornell.edu>
gbrown@anise.ee.cornell.edu "Geoffrey Brown" writes:
<big snip>
>> In fact Ian Page at Oxford and my group at Cornell have languages
>> similar to occam (Ian has lately taken the politically astute path
>> of making his syntax look more like C). In my group we are compiling for
>> data acquisition applications where the primary goal is to move
>> data around and perform accurate timing, but not to perform lots of
>> computation on the data. FPGA's are great for parallel control and
>> moving data around, but pretty poor for arithmetic intensive
>> applications.
>>
>> Geoffrey Brown
Could you post a fragment in your language?
--
Tim Eccles
Article: 2985Hi folks! if we emulate x86 architecture using fpga chips, and thereby make use of many more execution units than are available on a single chip pentium, do you think we can build a much more powerful x86 machine ? Thanx...ravindra.Article: 2986
Hi --- I'm wondering if anyone has used the Actel FPGA series...specifically the ACT2 family and the TA161 logic element. The TA161 is supposed to be a mimic of the 74161 standard MSI device. We're using this device and have discovered that the RCO output goes high for about 2 ns on the 0111 to 1000 transition (7 to 8) as well as the regular pulse on the 1111 (F) count. Our application is using these elements for a 32 bit counter, and so has 4 elements sequenced. We're also using the RCO output to clock a flipflop for interrrupt generation after the first 2 stages. The false RCO pulse causes our simulation to give bogus results. Has anyone had any experience with this device and/or problem before? Any insight would be appreciated. Please send e-mail to starfire2@earthlink.net. Thanks DaveArticle: 2987
Hi --- I'm wondering if anyone has used the Actel FPGA series...specifically the ACT2 family and the TA161 logic element. The TA161 is supposed to be a mimic of the 74161 standard MSI device. We're using this device and have discovered that the RCO output goes high for about 2 ns on the 0111 to 1000 transition (7 to 8) as well as the regular pulse on the 1111 (F) count. Our application is using these elements for a 32 bit counter, and so has 4 elements sequenced. We're also using the RCO output to clock a flipflop for interrrupt generation after the first 2 stages. The false RCO pulse causes our simulation to give bogus results. Has anyone had any experience with this device and/or problem before? Any insight would be appreciated. Please send e-mail to starfire2@earthlink.net. Thanks DaveArticle: 2988
Call Global Engineering Documents at (800)854-7179 and request JESD3-C. This will get you the document describing the JEDEC file format for PLDs. You can expect to pay about $60.00. Good Luck, ErichArticle: 2989
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Article: 2990
In article <826306777snz@tile.demon.co.uk>, Tim@tile.demon.co.uk says...
>
>In article <4hpbpo$4o2@newsstand.cit.cornell.edu>
> gbrown@anise.ee.cornell.edu "Geoffrey Brown" writes:
>
><big snip>
>
>>> In fact Ian Page at Oxford and my group at Cornell have languages
>>> similar to occam (Ian has lately taken the politically astute path
>>> of making his syntax look more like C). In my group we are compiling
for
>>> data acquisition applications where the primary goal is to move
>>> data around and perform accurate timing, but not to perform lots of
>>> computation on the data. FPGA's are great for parallel control and
>>> moving data around, but pretty poor for arithmetic intensive
>>> applications.
>>>
>>> Geoffrey Brown
>
>Could you post a fragment in your language?
>
>--
>Tim Eccles
Sure -- here's a two place buffer. This example assumes
an environment with two channels -- one input, one output.
The protocols for the channels are short (16 bits). In general
we could have something like {int : 4, int : 20} for a channel
that passes a 4 bit integer and a 20 bit integer simultaneously
(short is equivalent to "int : 16"). The example shows local scoping,
parallel and sequential composition,
and iteration. Iterative and conditional constructs can have multiple
guarded processes (here iteration has one).
Our compiler spits out AHDL (for altera parts) or EDIF for Xilinx 6200,
Motorola MPA, and others. We also have a source level debugger that
allows scripting in TCL or the usual WYSIWYG with breakpoints, watched
variables, etc.
externi chan in of {short}; // Channel from PC
externo chan out of {short}; // Channel to PC
chan mid of {short};
par
:: a: { short x;
do
:: in?x ->
mid!x
od
}
:: b: { short x;
do
:: mid?x ->
out!x
od
}
rap
Article: 2991David F. Spencer (starfire2@earthlink.net) wrote: : Hi --- : I'm wondering if anyone has used the Actel FPGA series...specifically : the ACT2 family and the TA161 logic element. : The TA161 is supposed to be a mimic of the 74161 standard MSI device. : We're using this device and have discovered that the RCO output goes : high for about 2 ns on the 0111 to 1000 transition (7 to 8) as well as : the regular pulse on the 1111 (F) count. Our application is using these : elements for a 32 bit counter, and so has 4 elements sequenced. We're : also using the RCO output to clock a flipflop for interrrupt generation : after the first 2 stages. The false RCO pulse causes our simulation to : give bogus results. : Has anyone had any experience with this device and/or problem before? : Any insight would be appreciated. I beleive that even a 74161 can exhibit the static hazard to which you refer. For your example, the proper way to use the "TC" output of a 74161 is to synchronously enable the setting of a flop. If you must set the flop in the same cycle that "TC" asserts, then you'll have to decode an output of 14 to enable the synchronous set. Hope that helps, Mike Budwey budwey@sequoia.comArticle: 2992
In article <4hqg63$bj1@chile.it.earthlink.net>, "David F. Spencer" <starfire2@earthlink.net> wrote: > Hi --- > > I'm wondering if anyone has used the Actel FPGA series...specifically > the ACT2 family and the TA161 logic element. > > The TA161 is supposed to be a mimic of the 74161 standard MSI device. > I has always ( i.e. since 1969 when this circuit was born as the Fairchild 9316, and I was its applications guy ) been considered bad practice to use the Terminal Count ( or Ripple CarrY ) output for anything else but as a synchronous control signal. You cascade these counters by connecting the TC output to the next Count Enable Trickle ( CET )input, throughout the chain. If this limits the frequency, a faster way is to use the first TC output to drive all downstream CEP inputs in parallel, and use the second TC in the conventional way, connect it to the next CET inputs. The second device's CET input must be permanently active. CEP = Count enable parallel ( i.e. it does not gate TC ) CET = Count enable trickle, i.e. it affects TC. Be grateful to Actel that their decoding is so poor that it showed up in the simulation, otherwise it might have shown up only in your later production. Peter Alfke, Xilinx Applications ( Good Samaritan in this case )Article: 2993
> Steve, this is a clear case of confusing semantics. C vs. HDL
>
> You want to be able to access the bits of a fundamental data type.
> But the [] operator works on arrays.
I agree.
If we went with the int13 thought I'd still like to be able to say
int13 a,b,c;
bit *d,*e,*f;
d=(bit *)&a;
e=(bit *)&b;
f=(bit *)&c;
c[5] = a[4] & b[7];
(the above could be bad code I don't have complier to test it with:)
This would be in keeping with C as is except a new type - bit.
> #include <stdio.h>
>
> typedef struct { int value:13; } int13;
>
> int main()
> {
> int13 a,b,c;
>
> a.value = 8000;
> b.value = 200;
> c.value = a.value + b.value;
> printf("%d\n",c.value);
> return 0;
> }
This is almost good, the code below is more in line.
#include <stdio.h>
typedef struct { int dummy_bits:19;int bits:13; } int13;
int main()
{
int13 a,b,c;
a.bits = 14;
b.bits = 5;
c.bits = a.bits + b.bits;
printf("a = %d, b = %d, c = %d\n",a.bits,b.bits,c.bits);
return 0;
}
This prints
a = 14, b = 5, c = 19
> : This is fine for new programs but I want to be able to port the
> : "billions and billions" of lines of code already out there.
>
> Steve,
>
> Abandon all hope of porting compute-intensive code to reconfigurable
> machines. I've looked at a lot of integer-oriented, compute-intensive
> algorithms, and although you can often get whiz-bang speed-ups using
> FPGAs, you can't do it from the C code written for a CPU. The more
> compute-critical something is, the more people pound on it, and the
> more machine-specific the code gets.
Never give up hope:) I believe it is something that has to be done
and so I will work to do it (not the most qualified but ..). I should
have said HDLs don't decribe programs (a complier/library thing I'm
sure). The world wants programs to run on machines. You can twist
HDLs to complie to programs but OCCUM is not C, even FORTRAN or BASIC
are not C and that is the way the world is today. C is what people feel
most comfortable with and I think it is what reconfigurable computing
has to address to grow.
Steve Casselman
Article: 2994
--
Why don't people like VHDL?
Why do people want to use C to program FPGAs?
Why have so many languages been written that are great but no one cares?
Why do people use VHDL if it really does suck?
Having spent a great deal of time (unpaid) writing my own language
(XL) for FPGAs, I've had to think about this. I enjoy writing FPGA
programs in XL, but what I really like is being able to change the
syntax, add features and basically muck around with code generation.
I've always wanted to somehow automate design, and building code
generators gives you power. For example, I've spent weeks
designing and debugging multipliers on FPGAs. It took one day to
code multiply into XL.
But I don't expect anyone to use XL.
I tell people its pseudo code, besides then I would have to document
it, and all it's little quirks (or fix them).
XL was actually written as a imtermediate form of a C to xnf compiler,
but we never finished the C compiler.
We have been using it for over 4 years now in various forms. XL
feels like a C syntax assembler for FPGAs. It is very direct and
tries to stay close to the spirit of C. (It is also generally bug free)
We discoved a few guiding principles in doing this, such as:
- If it is hard to explain, the syntax is wrong.
- You can only have one rule, per concept. An example is timimg. If
we say "all statements run in parallel", you can remember that.
- Code generators produce less bugs than people. XL generates logic
for communication, and memory access.
- Code generators produce more efficient code than programmers. Just
because no one has time to screw around optimizing something that
works.
In XL functions, loops, and operators work basically as
you (we) would expect, except that everthing tries to run in parallel.
Here is an example of XL:
#include "stdmath.xh" /* points to a bunch of XNF macros */
void /* function returns nothing */
parallel /* keyword parallel indicate function runs in parallel*/
fun0(); /* with calling function. */
int32 a,b,c,d,e,f,g,h; /* use half a 4010 */
fun0() /* when fun0() is called a state bit called fun0 is
forced to 1*/
{
int4 x; /* 4 bit signed var called x (builds register named x) */
x=0; /* x is forced to 0 when fun0 is called (builds mux) */
a=1; /* all these statements run in parallel */
b=2;
c=3;
d=4;
: /* the isolated colon says "wait one clock", then */
/* enable the next set of statements */
/* the colon actually creates a register, and a new bit */
/* of state. The new state bit is called fun0_1 */
e=5; /* then these statements run */
f=6;
g=7;
h=8;
while(x<10) /* for some number of clocks (builds a comparator) */
{
:y=((a+b)+(c+d))+((e+f)+(g+h)); /* builds an adder tree as shown */
x++; /* y is assigned on same clock as */
/* x is incremented */
}
; /* here if while condition failed */
then; /* had to invent keyword "then" to
force the thread to wait until the
while exited */
:x=1; /* wait a clock then force x to 1 */
:x=2; /* wait a clock then force x to 2 */
:x=3; /* wait a clock then force x to 3 */
}
The big difference is timing. All statements between colons execute on
the same clock.
Since this is not "C", it cannot expect to be adopted outside of
fanatics. And this is good, because there is no
reason to have to control the timing for purposes of executing
software in FPGAs. If you are designing FPGAs to run software, you
need a C compiler for FPGAs. It is as simple as that. You need
a good optimizing compiler, that can generate XNF. What you really
want to do is to make your C code go fast.
Besides its role as the universal solvent for computer algorithms,
C also has some really unique advantages as an HDL.
C lacks absolute timing. This means that a compiler can remove
clock ticks. I don't think a VHDL user would be very happy if his
compiler did that, but a C programmer would be delighted.
In fact, a compiler can uncover all the parallism
inherent in a function, then map it into whatever hardware the
compiler is aware of.
Lets list what is good about vanilla C as an HDL for FPGA software
- Its software
- Easy to test and dbug algorithms.
- No timing to figure out.
- Build state machines with C keywords.
- It is the best way to document your work.
- There is no reason a C algorithm can't run as fast as the same
algorithm coded in schematic capture.
- Multiple C programs (threads) can run in parallel making C a
parallel language by definition.
- Inherent support for compiled CPUs
What's wrong with it
- Its not VHDL, and all hardware guys use VHDL or will in the future
- real men use schematic capture
- no control over timing (other than sequential ordering)
- no one sells a C to XNF compiler
- no one executes software in FPGAs
Oh well -
Brad Taylor
/=============================<>=====================================\
| Brad Taylor blt@emf.net |
\=============================<>=====================================/
Article: 2995Anyone out there figured out how to make one of these little boxes that interface between an RS232 port and the serial input and control ports of the Altera 8000 series FPGAs ?. cheers MikeArticle: 2996
Doug Shade wrote: > Are there erasable serial PROMs for the Xilinx > family? Atmel makes serial configuration EEPROMs which are compatible with the Xilinx PROMs. With some clever programming, they can be used directly in place of Altera configuration PROMs as well. _-_rune_-_Article: 2997
What sort of problems are people having in creating pfpga implementation using C, VHDL, and OCCAM? Is one language better than another? Are different languages better for something, like pipelined implementations? thanks, marcArticle: 2998
Dave Galloway <drg@cs.toronto.edu> wrote: > > a = input; > b = a + 6; > a++; > c = a; > >and input has the value 3, then the results should be a = 4, b = 9 and c = 4 >in any language that is like C. A compiler (even tmcc, which is pretty >simple) can find the low level parallelism in those statements, and >generate a circuit that produces the three correct results in parallel, in >one clock cycle. Stefan Ludwig <ludwig@inf.ethz.ch> wrote: >Yes, you're right of course. I was trying to say, that I think it's hard >to write parallel programs in a sequential language. Even though the compiler >might catch all the parallelism that is there. Maybe I'm wrong and the quality >of the produced hardware is as good as when you'd use a parallel language like >VHDL. There are several kinds of parallelism. The low-level "these N statements can all be computed in the same clock cycle" type can be handled fairly easily. The quality of the generated hardware depends on how good the compiler is, and it should be fairly independent of the source language. High-level parallelism needs a different approach. You often want a number of independent threads in the circuit, say: one handling a bus interface, one talking to an I/O interface, and one doing some computing. The tmcc compiler handles this by letting you compile multiple C programs, one for each thread, which can talk to each other through shared variables. It isn't the most flexible solution, but it is the cleanest I could think of from the C point of view. Tmcc web page: http://www.eecg.toronto.edu/EECG/RESEARCH/tmcc/tmccArticle: 2999
We are looking for experienced digital hardware designers with a background in FPGA/CPLD design, digital video, memory control logic (including VRAM and preferrably newer technologies such as SDRAM, RAMBUS, or WRAM). Familiarity with schematic capture, PCB layout, FPGA place and route, and timing simulation software expected. Asic design experience and good analog skills a definite plus. Displaytech is the world's leading supplier of ferroelectric liquid crystal microdisplay engines to be used in the next generation of head mounted displays, CRT replacements, and wearable computers. Resumes via email, or snail mail to Human Resources at the address below. -- Rainer M. Malzbender Voice: (303) 449-8933 Displaytech, Inc. Fax: (303) 449-8934 2200 Central Ave. Boulder, CO 80301 Net: rainer@displaytech.com
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