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I am trying to find www sites which offer information including; historical information, modulation methods and details of coding of the information for Ethernet and Global Positioning Systems Please forward all responses to; roger@mrad.com.au thanks in advance, Roger.Article: 3101
In article <4iv52t$d4o@pcsi.pcsi.cirrus.com>, EPV <EPV@pcsi.cirrus.com> writes: > I have implemented delta sigma D/A which involves feeding back an adder's output to > its input and filtering the the MSB output to generate an analog value proportional > to the the input. How would one go about the inverse if that is even the right way > to put it? Block diagrams of sigma-delta A/Ds contain D/As and blocks called > decimation filters. I am still confused as to what the analog values could possibly > mean to to a digital input pin I am guessing the signal are differentiated and > perhaps mixed with an oversampling frequency then you get some kind of freq or pwm > bit stream. I know, I am rambling. I am posting here because I want put this in a > Lattice 1016 which are very easy to use by the way. > We have done Delta Sigma A/D in both microcontrollers, and PLD's. and PLD's coupledto MicroControllers... The simplest delta A/D is a D Flipflip, and an integrator,in a closed loop. The clock samples the D in ( integrator Out ) every cycle, and the Q feedback provided go-up go-down feedback. By totaling the Q Hi time, over a known period, you get the AVERAGE voltage needed to balance the integrator. Typical counters are 14-18 bits, one runs as the sampling timer, the other totals HI;s on the Q output. The PLD we used was ATMEL ATV750, designed to work with a 80C52. To put the whole thing intoa PLD needs quite a few resgisters eg for 16 bits 1 FF for Delta Feedback 16 T flipflops for TImebase counter 16 T flipflops for Totalising COunter 16 D flipflops for Latch of Totalise This is single bit A/d with a high freq clock. You could also try a FLASH A/D ( low res = 6 bits ), and chase remnant charge measurement if you want more resolution bandwidth. - regards - jim granville.Article: 3102
Jim Banks (jbanks@hpqtdzo.sqf.hp.com) wrote: : Have the defaults on makebits changed in 5.2 to produce different : length files? I received two prompts replies from Xilinx on this subject. The following one explains all. >From Xilinx. The default options were changed for makebits between version 5.1 and version 5.2. The default options for makebits 5.2 is: -lc=aligned_lc. The default options for makebits 5.1/5.0 is: -lc=aligned_done. The usage for makebits 5.2 still shows the default options as -lc=aligned_done though it is -lc=aligned_lc. This change in default options accounts for the difference in the length count that you are seeing. To fix the problem, explicitly specify the length count option on the command line: makebits <design> -lc=aligned_done. This should return the length count to its previous value. -------------- The error would appear to be in the online help for makebits. Thanks for the quick replies, Jim Banks. -- *************** __ ************************************************** ************* / / ************ Jim Banks * *********** / / ********* HP Queensferry Telecom Operation * ********* / /___ ______ ******* email: jbanks@hpsqf.sqf.hp.com * ******** / __ // __ / ****** Mail: Station Road * ******** / / / // /_/ / ****** South Queensferry * ********* /_/ /_// ____/ ******* West Lothian, EH30 9TG * ********** / / ********* Scotland * ************ / / *********** Telnet: 313-2949 (+44-131-331-7949)* ************* /_/ ****************************************************Article: 3103
Does anyone know of books with demo HDL software bundled? I am a long time designer of mixed-mode circuits, but have never been exposed to HDLs except ABEL, so am probably a beginner at this. Thanks, Douglas L. Datwyler datwyler@aros.netArticle: 3104
If you're looking for proven PCI FPGA designs, you should check out ATT ORCA FPGAs. We have had success running them at 33MHz. Our designs have been customized for maximum operating frequency and minimal size, so they'll work in most PCI compliant FPGA and ASIC technologies. Most companies selling PCI cores do not target to FPGA architectures and as a result don't run at speed and have high gate counts. Stan Hodge <stb@dnaco.net> wrote: >Hi, >With all the schedual slips at major silicon vendors who are doing PCI >implementations, I am wondering if the FPGA vendors are providing hard >proved macro's which will be compadiable from the start? Anyone have >experience with the major vendors PCI support? Good / Bad / zero? > Thanks, > Stan Hodge > Grimes Aerospace > stb@dnaco.netArticle: 3105
In article <4jpkog$m19@zeppo.mrad.com.au> roger@mrad.com.au writes: (Crossposted to comp.dsp,comp.ai,comp.arch,comp.multimedia, comp.arch.fpga,comp.realtime,comp.robotics,comp.speech, comp.sys.transputer,sci.electronics,sci.image.processing) >I am trying to find www sites which offer information including; >historical information, modulation methods and details of coding of the >information for Ethernet and Global Positioning Systems Gee folks, is this at last our first piece of genuinely off-topic net Spam? Well at least he isn't claiming to have pictures of anyone... George Brims ************************************************************ A sig file son? Oh that's just a sort of bumper sticker for the information superhighwayArticle: 3106
We are just getting to grips with PROCapture & XACT, and someone I work with needs to do the following : 1) An 8bit x 1 two`s-complement multiplier in 8 blocks (?). 2) A serial subtractor (two`s complement) with 2x 36bit input busses and a 36bit output bus. Any ideas ? Thanks.Article: 3107
Call for Papers 2nd Notice
CONFERENCE: Photonics East 96 -- SPIE
November 18-22 1996, Boston MA.
"Reconfigurable Technology for Rapid
Product Development & Computing"
Program Chairs:
John Schewel, Virtual Computer Corp. jas@vcc.com
Peter Athanas, Virginia Polytech. Institute athanas@vt.edu
V. Michael Bove, Jr. MIT Media Laboratory vmb@media.mit.edu
Bradley Fawcett, Xilinx Inc. brad.fawcett@xilinx.com
Philp J. Kuekes, Hewlett Packard Laboratories pjk@hplric.hpl.hp.com
(pending confirmation)
_____________________________________________________________________________
ANNOUNCEMENT AND CALL FOR PAPERS
_____________________________________________________________________________
This conference is part of SPIE's International Symposium
To be held as part of Photonics East '96
Boston, Massachusetts USA
November 18-22 1995
Design engineers of both hardware and software are finding
ways to breakthrough current computation and product development
bottlenecks through the use of reconfigurable technology. This
conference focuses on two areas utilizing reconfigurable technology:
1) rapid product development
2) reconfigurable computing
Reconfigurable technologies are new and valuable tools for both
the design and maunfacturing engineer. With the ever-changing needs
in the marketplace and growing worldwide competition, manufacturers
must continually search for methods which accelerate the time to market.
Current reconfigurable hardware platforms enable the use of this technology
for electronic design in rapid product development and implementation.
This conference will present papers that illustrate applications
and techniques for using reconfigurable technology in the design
and manufacturing cycles; as well as high preformance computing.
Papers are solicited in the following and related areas:
- - reconfigurable digital & analog components, and their use in
the product development cycle
- - applications and platforms utilizing reconfigurable
technology for rapid product development & high performance computing
- - applications utilizing reconfigurable technology for image
and signal processing, communication and data processing.
Schedule
Paper Abstracts Due from Authors: April 8, 1996
Notice of acceptance: April 30, 1996
Manuscripts Due from Authors: August 26, 1996
Article: 3108
I've managed to pass many an hour attempting to develop an XBLOX design
targeted for an XC4005E. After reaching the point where there was no
apparent reason for it not to work, I discovered that the actual routing
as seen in the .LCA file was suspect. I've since heard from a couple of
other users that XBLOX often does not synthesize correctly.
Does anyone else out there have any experience with XBLOX, good, bad,
or horrible? I'm using XACT 5.2 and Orcad 386+ .
David Cole
rainman@indra.com
Article: 3109David G Cole wrote: > > I've managed to pass many an hour attempting to develop an XBLOX design > targeted for an XC4005E. After reaching the point where there was no > apparent reason for it not to work, I discovered that the actual routing > as seen in the .LCA file was suspect. I've since heard from a couple of > other users that XBLOX often does not synthesize correctly. > > Does anyone else out there have any experience with XBLOX, good, bad, > or horrible? I'm using XACT 5.2 and Orcad 386+ . > > David Cole > rainman@indra.com We've used it in small doses with a 3090A design, with XACT 5.1.1 and Viewlogic and not had any problems, however YMMV! -- Regards AndyG ------------------------------------------------------------------------ Terry Pratchett's 'Wyrd Sisters' on stage in Leeds - April 23-27 check out http://ourworld.compuserve.com/homepages/Whitkirk for details, or e-mail 73064.1273@compuserve.com ------------------------------------------------------------------------Article: 3110
lii, you point in the direction of at&t, but you're talking about your own product (logic innovations). why not make that clear from the start? phil On Tue, 2 Apr 1996 news@logici.com wrote: > If you're looking for proven PCI FPGA designs, you should check out > ATT ORCA FPGAs. We have had success running them at 33MHz. > Our designs have been customized for maximum operating frequency > and minimal size, so they'll work in most PCI compliant FPGA and ASIC > technologies. Most companies selling PCI cores do not target to > FPGA architectures and as a result don't run at speed and have high > gate counts. > > Stan Hodge <stb@dnaco.net> wrote: > > >Hi, > > >With all the schedual slips at major silicon vendors who are doing PCI > >implementations, I am wondering if the FPGA vendors are providing hard > >proved macro's which will be compadiable from the start? Anyone have > >experience with the major vendors PCI support? Good / Bad / zero?Article: 3111
David G Cole (rainman@indra.com) wrote: : : Does anyone else out there have any experience with XBLOX, good, bad, : or horrible? I'm using XACT 5.2 and Orcad 386+ . : : David Cole : rainman@indra.com : I've used it for a few 4000 designs including a 4005. I didn't have any problems with Xblox. Though because of the extra level of abstraction I did find it harder to find some types of design entry errors. I used it with the Intergraph Aceplus schematic capture, I even managed to mix up some Abel blocks with the Xblox schematics. Maybe there are problems with the 4000E software - I believe this is still at the beta stage. -- ****************************************************************************** * Phil Layton, Senior R & D Engineer * * BBC Research & Development Department * * Kingswood Warren, Tadworth, Surrey KT20 6NP, UK * * * ******************************************************************************Article: 3112
Hi PCI-experts, can someone explain me how one can address a FPGA-PCI-interface. I don't know if I'm expressing myself correctly so I'm gone explain what I'm trying to ask : I've build a PCI interface for a FPGA. If I'd like to transfer data to the PCI-interface. Somehow I have to tell the softwareprogram on what address I have to put the data in. (the address where the FPGA-PCI-interface is). So I assume it's the base-address assigned to the PCI-interface. How is a base address assigned to a PCI-interface ? I mean, if I make a base-address-register, what are the rules for assigning an address to the FPGA-PCI-interface ? What's the use of the mandatory header registers 'Device ID','Vendor ID' ? And how do you read those registers. Is it an I/O command one have to perform ? Thanks in advance -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 3113
: Does anyone else out there have any experience with XBLOX, good, bad, : or horrible? I'm using XACT 5.2 and Orcad 386+ . I found an XBLOX bug in September. I had an OBUFT with the T pin inverted. As part of the XBLOX optimization, it changed the OBUFT to an OUTFFT (that was OK), and it tried to push the INV to the output of the gate driving the OUTFFT's T input. This optimization is OK as long as that output can be inverted. In my case, the signal came from an IBUF; the output of the IBUF can't take an INV parameter. Instead of synthesizing an inverter, XBLOX just forgot about it! The Xilinx technical support person verified that the latest software (in September) still had the bug. --- Joe -- +===============================================================+ + Joe Samson (313) 994-1200 x2878 + + Research Engineer, ERIM + + P.O. Box 134001 email samson@erim.org + + Ann Arbor, MI 48113-4001 + +===============================================================+Article: 3114
Here is a wrap-up: Jim Banks raised a flag when a design recompiled with XACT 5.2 gave a different length-count value than the same design had given previously, when it was compiled with a prior version of the Xilinx software. It is important to note that, in spite of the length-count difference, both files resulted in a properly functioning part. The question is: why did Xilinx change the default length-count algorithm between XACT 5.1 and 5.2, and why ( the hell ) was this little change not communicated properly to all users? Since I ( together with Chuck Erickson ) was the driving force behind the change, I will answer the first question, and leave the second one as a living embarrassment. The issue that led to the change is described on the last page of the Xilinx app note "FPGA Configuration Guidelines" of Oct 94. It deals the appropriate length-count value for byte-parallel configuration. ( For byte serial configuration, the length count can be any value, as long as it is high enough, and there never was any problem with that.) For byte parallel configuration, it is mandatory ( well, make that: highly desirable in order to avoid possible problems that might lead to frustration and calls to the Xilinx Hotline ) that all action, from detecting the length-count match to the real end of the configuration process ( reaching "F" in the drawing on page 2-29 of the Xilinx data book ), all occurs within the same byte. Therefore it matters where the byte boundary is, and the length-count value is calculated appropriately In the "old days" prior to 5.2, the length-count calculation algorithm calculated a value that made "DONE go High" at the end of the last byte. This did work for most cases, but created problems with some parallel interfaces driving certain daisy-chains. About 2 years ago, we suggested a smarter way of calculating length count: Make sure that the "beginning of the end", the detection of "length-count match" occurs at the first bit of the last byte, then there will always be enough CCLK pulses to finish configuration. That's obviously a cleaner and simpler algorithm. This new method was called "Length Count Aligned" ( -lc=aligned_lc in computerese) and was first offered as the non-default option, because we did not want to upset the user community that had used the old "DONE-aligned" ( -lc=aligned_done) calculation, successfully in almost all cases, for ten years. When 5.2 was released, Xilinx had gained enough confidence to make "Length-count aligned" the default option, giving you the old "DONE" aligned option as the non-default. We had not heard about any problems since then, and all the old questions, and needs for length-count padding, have disappeared. So this was a success. But it means that the default length-count value changed between 5.1 and 5.2, and it would have been appropriate to inform the world about it more clearly. Mea culpa. Peter Alfke Xilinx Applications.Article: 3115
In article <BILLMS.96Mar5082356@nixon.icsl.ucla.edu>, Bill Mangione- Smith <billms@nixon.icsl.ucla.edu> writes >In article <r9qohqcqzco.fsf@fester.cs.washington.edu> Paul Franklin ><paul@cs.washington.edu> writes: > > If you guys are really serious about setting up another fpga group... > >I'm not, I'm convinced its a bad idea. The traffic here doesn't >warrent it. > >Bill Just adding my twopenneth, I also do not believe splitting the group is a good idea, after all, as others have said it is a low volume newsgroup which makes it quite easy to sort through for articles of interest. Also which group would questions pertaining to which manufacturers and which software be directed to, the answers to these questions are useful to both groups I believe, this could generate a lot of crossposting which would be counter productive. Regards -- Stephen BellArticle: 3116
There's a thread going over on comp.arch ("dataflow machines") that I
think is relevant to the FPGA computing language discussion going
on here. Example quotes:
>
> It looks, from the sidelines where I sit, as if the compiler people
>take source code, convert it to a dataflow model where they optimise and
>generally tinker a great deal, and then laboriously convert that to
>sequential code on output. Then the microprocessor people take that
>sequential code and, even more laboriously, convert it back into dataflow
>stuff, and execute that.
(amolitor@blefscu.network.com)
> As I say above, I keep hoping that there is a better way to walk the
> graph - but the Von Neuman traversal of the dataflow graph is really a
> pretty efficient way to do so. Or, rather, it is general and
> fundamental - it walks the graph with one "locus of attention" at any
> time. Who said that computer science has three numbers: 0, 1, and
> many? If you are going to walk the graph with many "locii of
> atention", how many do you provide? 2? 4? 8?
(glew@ichips.intel.com)
Rather than do a bunch of unauthorized crossposting, I'm just
directing your attention over there. But then anyone seriously interested
in FPGA computing architectures always reads comp.arch anyway, right? ;->
--Mike
--
Mike Butts, Portland, Oregon mbutts@netcom.com
Article: 3117In article <peter-0404961028190001@appsmac-1.xilinx.com>, peter@xilinx.com (Peter Alfke) wrote: > Here is a wrap-up: I made a dumb and misleading typo: It should be: ( For bit-serial configuration, the length count can be any value, as long as it is high enough, and there never was any problem with that.) I had typed "byte-serial", which makes no sense at all. Sorry. Peter AlfkeArticle: 3118
I'm looking for an HDL or VHDL implementation that runs on a PC platform, preferably on Win95. I need to design and simulate the implementation of a few parallel algorithms. Can anybody point me to a package that I can obtain without resorting to a second mortgage ? Thanks... AlbertoArticle: 3119
hi, I am looking for some models to help me develop ISA Plug & Play functionality on an FPGA. Any and all pointers are welcome. muzo standard disclaimerArticle: 3120
datwyler@aros.net (Douglas L. Datwyler) writes: >Does anyone know of books with demo HDL software bundled? I am a long time >designer of mixed-mode circuits, but have never been exposed to HDLs except >ABEL, so am probably a beginner at this. >Thanks, >Douglas L. Datwyler >datwyler@aros.net take a look at http://Literary.COM/mkp/pages/2704/index.html I think it is what you are looking for LoucasArticle: 3121
Article: 3122
Dear Colleague,
Below is the final program for the 1996 Physical Design Workshop.
This year's program will emphasize deep-submicron and
high-performance issues, and will also feature a special track on
micro electromechanical systems (MEMS), chaired by Ken Gabriel of ARPA
and Ken Pister of UCLA. The Keynote address will be delivered by
Professor C. L. Liu of the University of Illinois at Urbana-Champaign.
PDW'96 is co-sponsored the U.S. National Science Foundation; for
more information, please see:
http://www.cs.virginia.edu/~pdw96/
Thanks,
Gabe
======================================================
Name: Prof. Gabriel Robins
General Chair, PDW'96
U.S. Mail: Department of Computer Science
Thornton Hall
University of Virginia
Charlottesville, VA 22903-2442
Phone: (804) 982-2207
FAX: (804) 982-2214
E-mail: robins@cs.virginia.edu
WWW: http://www.cs.virginia.edu/~robins/
======================================================
=============================================================================
FINAL PROGRAM
Fifth ACM/SIGDA Physical Design Workshop
April 15-17, 1996 - The Sheraton Reston Hotel, Reston, Virginia USA
http://www.cs.virginia.edu/~pdw96/
The ACM/SIGDA Physical Design Workshop (PDW'96) provides a relaxed
atmosphere for exchange of ideas and promotes research in critical
subareas of physical design for VLSI systems.
This year's workshop emphasizes deep-submicron and high-performance
issues, and also provides a special focus on opportunities in CAD for
micro electromechanical systems (MEMS). There are four outstanding
panel sessions:
(1) future needs and directions for deep-submicron physical design,
(2) physical design needs for MEMS,
(3) manufacturing and yield issues in physical design, and
(4) critical disconnects in design views, data modeling, and back-end
flows (e.g., for physical verification).
There are also many outstanding technical paper sessions.
Free-flowing discussion will be promoted through the limited workshop
attendance, the poster session and the "open commentary" mechanism in
each technical session, as well as a concluding open problems session.
During the workshop, a benchmarks competition will occur in the areas
of netlist partitioning and performance-driven cell placement.
=============================================================================
SUNDAY, APRIL 14
=============================================================================
6:00pm-8:30pm: Registration
(the registration desk will also be open 8:00am-5:00pm on Monday
and 8:00am-12:00pm on Tuesday)
7:00pm-8:30pm: Reception (refreshments provided)
=============================================================================
MONDAY, APRIL 15
=============================================================================
8:30am-8:40am: Welcome
8:40am-10:00am: Session 1, Timing-Driven Interconnect Resynthesis
Session Chair: E. S. Kuh (UC Berkeley)
Interconnect Layout Optimization by Simultaneous Steiner Tree
Construction and Buffer Insertion, T. Okamoto and J. Cong (UC Los Angeles)
Simultaneous Routing and Buffer Insertion for High Performance
Interconnect, J. Lillis, C.-K. Cheng and T.-T. Y. Lin (UC San Diego)
Timing Optimization by Redundancy Addition/Removal, L. A. Entrena, E. Olias
and J. Uceda (U. Carlos III of Madrid and U. Politecnica of Madrid)
Open Commentary - Moderators: D. D. Hill (Synopsys),
P. Suaris (Interconnectix)
10:00am-10:20am: Break (refreshments provided)
10:20am-12:00pm: Session 2, Interconnect Optimization
Session Chair: C. L. Liu (U. Illinois Urbana-Champaign)
Optimal Wire-Sizing Formula Under the Elmore Delay Model,
C.-P. Chen, Y.-P. Chen and D. F. Wong (U. Texas Austin)
Reducing Coupled Noise During Routing, A. Vittal and M. Marek-Sadowska
(UC Santa Barbara)
Simultaneous Transistor and Interconnect Sizing Using General
Dominance Property, J. Cong and L. He (UC Los Angeles)
Hierarchical Clock-Network Optimization, D. Lehther, S. Pullela,
D. Blaauw and S. Ganguly (Somerset Design Center, Motorola)
Open Commentary - Moderators: D. D. Hill (Synopsys),
M. Lorenzetti (Mentor)
12:00pm-2:00pm: Lunch
Workshop Keynote Address: Prof. C. L. Liu, U. Illinois Urbana-Champaign
Algorithmic Aspects of Physical Design of VLSI Circuits
2:00pm-2:45pm: Session 3, A Tutorial Overview of MEMS
Speaker: K. J. Gabriel (ARPA)
2:45pm-3:00pm: Break
3:00pm-4:15pm: Session 4, Physical Design for MEMS
Session Chair: K. J. Gabriel (ARPA)
Physical Design for Surface Micromachined MEMS, G. K. Fedder and
T. Mukherjee (Carnegie-Mellon U.)
Consolidated Micromechanical Element Library, R. Mahadevan and
A. Cowen (MCNC)
Synthesis and Simulation for MEMS Design, E. C. Berg, N. R. Lo,
J. N. Simon, H. J. Lee and K. S. J. Pister (UC Los Angeles)
4:15pm-4:30pm: Break (refreshments provided)
4:30pm-6:00pm: Session 5, Panel: Physical Design Needs for MEMS
Moderator: K. S. J. Pister (UC Los Angeles)
Panelists include:
S. F. Bart (Analog Devices)
G. K. Fedder (Carnegie-Mellon U.)
K. J. Gabriel (ARPA)
I. Getreu (Analogy)
R. Grafton (NSF)
R. Harr (ARPA)
R. Mahadevan (MCNC)
J. E. Tanner (Tanner Research)
6:00pm-8:00pm: Dinner
8:00pm-9:30pm: Session 6, Panel: Deep-Submicron Physical Design:
Future Needs and Directions
Moderator: N. Mokhoff (Managing Editor, EE Times)
Panelists include:
T. C. Lee (President/CEO, Neo Paradigm Labs)
L. Scheffer (Architect, Cadence)
W. Vercruysse (UltraSPARC III CAD Manager, Sun)
M. Wiesel (Design Manager, Intel)
T. Yin (VP R&D, Avant! Corporation)
=============================================================================
TUESDAY, APRIL 16
=============================================================================
8:30am-9:50am: Session 7, Partitioning
Session chair: D. F. Wong (U. Texas Austin)
VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement
Techniques, S. Dutt and W. Deng (U. Minnesota and LSI Logic)
A Hybrid Multilevel/Genetic Approach for Circuit Partitioning,
C. J. Alpert, L. Hagen and A. B. Kahng (UC Los Angeles and Cadence)
Min-Cut Replication for Delay Reduction, J. Hwang and A. El Gamal
(Xilinx and Stanford U.)
Open Commentary - Moderators: J. Frankle (Xilinx),
G. Zimmermann (U. Kaiserslautern)
9:30am-10:10am: Break refreshments provided)
10:10am-11:50am: Session 8, Topics in Hierarchical Design
Session Chair: M. Sarrafzedah (Northwestern U.)
Two-Dimensional Datapath Regularity Extraction, R. X. T. Nijssen and
J. A. G. Jess (TU Eindhoven)
Hierarchical Net Length Estimation, W. Hebgen and G. Zimmermann
(U. Kaiserslautern)
Exploring the Design Space for Building-Block Placements Considering
Area, Aspect Ratio, Path Delay and Routing Congestion, H. Esbensen and
E. S. Kuh (UC Berkeley)
Genetic Simulated Annealing and Application to Non-Slicing Floorplan
Design, S. Koakutsu, M. Kang and W. W.-M. Dai (Chiba U. and UC Santa Cruz)
Open Commentary - Moderators: L. Scheffer (Cadence),
T. Yin (Avant! Corporation)
11:50pm-1:30pm: Lunch
1:30pm-3:00pm: Session 9, Poster Session
Physical Layout for Three-Dimensional FPGAs, M. J. Alexander, J. P.
Cohoon, J. L. Colflesh, J. Karro, E. L. Peters and G. Robins (U. of Virginia)
Efficient Area Minimization for Dynamic CMOS Circuits, B. Basaran
and R. A. Rutenbar (Carnegie-Mellon U.)
A Fast Technique for Timing-Driven Placement Re-engineering,
M. Hossain, B. Thumma and S. Ashtaputre (Compass Design Automation)
Over-the-Cell Routing with Vertical Floating Pins, I. Peters, P. Molitor
and M. Weber (U. Halle and Deuretzbacher Research GmbH)
Congestion- Balanced Placement for FPGAs, Y. Sun, R. Gupta and C. L. Liu
(Altera and U. Illinois Urbana-Champaign)
Fanout Problems in FPGA, K.-H. Tsai, M. Marek-Sadowska and S. Kaptanoglu
(UC Santa Barbara and Actel)
Performance-Driven Layout Synthesis: Optimal Pairing & Chaining
A. J. Velasco, X. Marin, J. Reira, R. Peset and J. Carrabina
(U. Autonoma de Barcelona and Philips Research Labs Eindhoven)
Clock-Delayed Domino for Adder and Random Logic Design, G. Yee and
C. Sechen (U. Washington)
3:00pm-4:00pm: Session 10, Manufacturing/Yield Issues I
Session Chair: Eby G. Friedman (U. Rochester)
Layout Design for Yield and Reliability, K. P. Wang, M. Marek-Sadowska
and W. Maly (UC Santa Barbara and Carnegie-Mellon U.)
Yield Optimization in Physical Design, V. K. R. Chiluvuri (Motorola)
(invited survey paper)
4:00pm-4:15pm: Break
4:15pm-5:45pm: Session 11, Panel: Manufacturing/Yield Issues II
Moderator: L. G. Jones (Motorola)
Panelists include:
V. K. R. Chiluvuri (Motorola)
I. Koren (U. Massachusetts Amherst)
J. Burns (IBM Watson Research Center)
W. Maly (Carnegie-Mellon U.)
5:45pm-7:30pm: Dinner
7:30pm-8:00pm: Session 12a, Design Views in Routing
Session Chair: B. T. Preas (Xerox PARC)
A Gridless Multi-Layer Channel Router Based on Combined Constraint Graph
and Tile Expansion Approach, H.-P. Tseng and C. Sechen (U. Washington)
A Multi-Layer Chip-Level Global Router, L.-C. E. Liu and C. Sechen
(U. Washington)
8:00pm-9:30pm: Session 12b, Panel: Design Views, Data Modeling and Flows:
Critical Disconnects
Moderator: A. B. Kahng (UC Los Angeles)
Panelists include:
W. W.-M. Dai (UC Santa Cruz, VP Ultima Interconnect Technologies)
L. G. Jones (Motorola)
D. Lapotin (IBM Austin Research Center)
E. Nequist (VP R&D, Cooper & Chyan)
R. Rohrer (Fellow, Avant! Corporation)
C. Palesko (VP, Savantage)
=============================================================================
WEDNESDAY, APRIL 17
=============================================================================
8:30am-9:50am: Session 13, Performance-Driven Design
Session Chair: M. Marek-Sadowska (UC Santa Barbara)
A Graph-Based Delay Budgeting Algorithm for Large Scale Timing-Driven
Placement Problems, G. E. Tellez, D. A. Knol and M. Sarrafzadeh
(Northwestern U.)
Reduced Sensitivity of Clock Skew Scheduling to Technology Variations,
J. L. Neves and E. G. Friedman (U. Rochester)
Multi-Layer Pin Assignment for Macro Cell Circuits, L.-C. E. Liu and
C. Sechen (U. Washington)
Open Commentary - Moderator: J. Cong (UC Los Angeles)
9:50pm-10:10pm: Break (refreshments provided)
10:10am-11:30am: Session 14, Topics in Layout
Session Chair: D. D. Hill (Synopsis)
Constraint Relaxation in Graph-Based Compaction, S.-K. Dong, P. Pan,
C. Y. Lo and C. L. Liu (Silicon Graphics, Clarkson U., Lucent Technologies,
U. Illinois)
An O(n) Algorithm for Transistor Stacking with Performance Constraints,
B. Basaran and R. A. Rutenbar (Carnegie-Mellon U.)
Efficient Standard Cell Generation When Diffusion Strapping is Required,
B. Guan and C. Sechen (Silicon Graphics and U. Washington)
Open Commentary - Moderator: D. D. Hill (Synopsys),
E. G. Friedman (U. Rochester)
11:30am-12:00pm: Session 15, Open Problems
Moderators: A. B. Kahng (UC Los Angeles), B. T. Preas (Xerox PARC)
12:00pm-2:00pm: Lunch (and benchmark competition results)
2:00pm: Workshop adjourns
=============================================================================
TRAVEL AND ACCOMODATIONS
=============================================================================
PDW '96 is being held at the Sheraton Reston in Reston, Virginia, near
Washington, D.C. The hotel is minutes from Dulles International
Airport (IAD), and 24-hour courtesy shuttles are available from the
airport to the hotel. The area is also served by Washington National
Airport (DCA), about 20 miles away, and Baltimore-Washington
International Airport (BWI), about 50 miles away.
The Sheraton Reston is located at:
11810 Sunrise Valley Drive
Reston, Virginia 22091
phone: 703-620-9000
fax: 703-860-1594
reservations: 800-392-ROOM
*** Please make your room reservation directly with the Reston ***
*** Sheraton hotel at the phone number above. ***
Room prices are $95 per night for single occupancy, and $105 per night
for double occupancy.
Driving directions from Dulles Airport: take the Washington Dulles
Access and Toll Road (route 267) to the Reston Parkway Exit (3). Turn
right at the light after paying toll. Take the next left onto Sunrise
Valley Drive, and continue for a couple blocks to the Sheraton (on
your left).
The Washington D.C. evening weather tends to be chilly in April, so
warm dress is suggested for the outdoors.
=============================================================================
SIGHTSEEING AND ATTRACTIONS
=============================================================================
The Nation's Capitol offers much in the way of sightseeing. The most
popular destinations are located in downtown Washington D.C.,
surrounding several square miles of park area known as the "National
Mall." There is no charge to visit the National Memorials located on
the Mall, which include the Washington Monument, where you may ascend
555 feet to an observation post; the Lincoln Memorial, whose design
adorns the back of the US penny; the Jefferson Memorial, which
includes a 19-foot bronze statue of Thomas Jefferson; and the Vietnam
Memorial, a long wall of black Indian granite dedicated in 1982.
The Smithsonian Institution (telephone (202) 357-2700) operates a
number of superb museums that flank the National Mall, including:
Freer Gallery of Art (Asian and 19th and 20th-century American art)
Hirshhorn Museum and Sculpture Garden (modern and contemporary art)
National Air and Space Museum (history of aviation and space exploration)
National Museum of African Art (collection and study of African art)
National Museum of American Art (paintings, graphics, and photography)
National Museum of American History (technology and culture in America)
National Museum of Natural History (history of the natural world)
National Portrait Gallery (portraits of distinguished Americans)
National Postal Museum (history of postal communication and philately)
Sackler Gallery of Asian art (from ancient to present)
Other attractions and tours around the D.C. area include (please call
the numbers below for schedules):
Arlington National Cemetary (703) 697-2131
Bureau of Engraving and Printing (202) 622-2000
Congressional buildings (202) 225-6827
FBI Headquarters (202) 324-3447
Library of Congress (202) 707-5000
National Aquarium (202) 482-2825
National Archives (202) 501-5000
National Zoological Park (202) 673-4821
The Pentagon (703) 695-1776
Supreme Court (202) 479-3030
Treasury Department (202) 622-2000
The White House (202) 456-7041
There are a number of reasonably priced eating places on the Mall; the
East Wing of National Gallery and the Air and Space Museums offer good
food and a place to sit down after sightseeing. Provisions will be
made for low-cost transportation to and from the Mall and downtown
Washington D.C., so bring your camera and strolling shoes and enjoy
our Nation's Capital!
=============================================================================
WORKSHOP ORGANIZATION
=============================================================================
General Chair:
G. Robins (U. of Virginia)
Technical Program Committee:
C. K. Cheng (UC San Diego)
J. P. Cohoon (U. of Virginia)
J. Cong (UC Los Angeles)
A. Domic (Cadence)
J. Frankle (Xilinx)
E. Friedman (Rochester)
D. Hill (Synopsys)
L. Jones (Motorola)
A. B. Kahng (UC Los Angeles, Chair)
Y.-L. Lin (Tsing Hua)
K. Pister (UC Los Angeles)
M. Marek-Sadowska (UC Santa Barbara)
C. Sechen (Washington)
R.-S. Tsay (Avant!)
G. Zimmermann (Kaiserslautern)
Steering Committee:
M. Lorenzetti (Mentor Graphics)
B. Preas (Xerox PARC)
Keynote Address:
C. L. Liu (Illinois)
Benchmarks Co-Chairs:
F. Brglez (NCSU)
W. Swartz (TimberWolf Systems)
Local Arrangements Chair:
M. J. Alexander (U. of Virginia)
Treasurer:
S. B. Souvannavong (HIMA)
Publicity Chair:
J. L. Ganley (Cadence)
Sponsors:
ACM / SIGDA
U.S. National Science Foundation
Avant! Corporation
=============================================================================
WORKSHOP REGISTRATION
=============================================================================
Fifth ACM/SIGDA Physical Design Workshop
April 15-17, 1996 - The Sheraton Reston Hotel, Reston, Virginia USA
Name: _______________________________________________________________
Company/University: _________________________________________________
Title: ______________________________________________________________
Address: ____________________________________________________________
City: _________________________________________ State: ______________
Phone: ____________________________ Email: __________________________
Registration Fees (Includes All Meals)
Advance (Through April 1) Late (After April 1/On-Site)
ACM Members __ $355 __ $440
Non-ACM __ $455 __ $540
Students __ $250 __ $250
ACM Membership Number: _____________________________
Dietary restrictions, if any: ______________________
Special needs: _____________________________________
The registration fee includes the workshop proceedings and all meals
(i.e., 3 breakfasts, 3 lunches, and 2 dinners), refreshments during
breaks, and a reception on Sunday evening. The total number of
attendees is limited (registrations will be returned if the workshop
is oversubscribed).
*** Note: Hotel reservations must be made directly with the Sheraton ***
*** Call (703) 620-9000 to make a room reservation at the Sheraton. ***
The only acceptable forms of payment are checks (personal, company,
and certified/bank checks) in US funds drawn on a US bank and made
payable to "Physical Design Workshop 1996" (credit cards will not be
accepted). Payment must accompany your registration. No FAX or Email
registrations will be processed.
Please mail your payment (checks only) along with this registration form to:
Sally Souvannavong, Treasurer
1996 ACM/SIGDA Physical Design Workshop
Department of Computer Science
Thornton Hall
University of Virginia
Charlottesville, VA 22903-2442 USA
Phone: (804) 982-2200
Email: pdw96@cs.virginia.edu
=============================================================================
Article: 3123In article <DpGL62.6Lu@mv.mv.com>, Alberto C Moreira <alberto@moreira.mv.com> wrote: >I'm looking for an HDL or VHDL implementation that runs on a PC platform, >preferably on Win95. I need to design and simulate the implementation of >a few parallel algorithms. Can anybody point me to a package that I can >obtain without resorting to a second mortgage ? Thanks... > >Alberto > > > Look at Model Technologies. They have a neat VHDL simulator on PC V-System. Silos has the same for Verilog HDL on PC. Alex Koegel DSPC IsraelArticle: 3124
muzok@msn.com wrote: > I am looking for some models to help me develop ISA Plug & Play > functionality on an FPGA. Both Xilinx and AT&T have detailed applications notes for this. Xilinx has one that includes schematics. Xilinx: http://www.xilinx.com AT&T: http://www.attme.com/fpga/index.htm
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