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XESS has released more material for the "FPGA Workout II"
text and the HTML has been slightly reformatted.
The DOS-based hypertext of "FPGA Workout II" can be downloaded
from ftp.vnet.net. Go to directory pub/xess/hyperdoc.
A chapter detailing the construction of a simple UART with
FIFO buffers can be found in the compressed executable file
comm.exe.
The URL for "FPGA Workout II" is
ftp://ftp.vnet.net/pub/xess/hyperdoc/html/fpgawk2.htm
There are currently five chapters covering the following topics:
+ detailed architecture of the EPX780 FPGA
+ syntax manual for the PLDasm HDL
+ JTAG fundamentals and use with the EPX780
+ a configuration circuit for the EPX780
+ buffered UART communications with the EPX780
--
|| Dave Van den Bout ||
|| Xess Corporation ||
Article: 1476jean@cis.nctu.edu.tw (Lin Feng Ming) wrote: >Beser, >We are wondering where the IOBUF is and how to use it ? > >Should we instantiate it each time we need or it can be auto instantiated >(inserted) by the Synopsys FPGA Compiler ? > >By the way, Since we use the Synopsys SGE as our interface editor, >and if we must instantiate it each time we need, is there any >IOBUF.sym that we can use ? > Hello, First let me tell you the version I am using, it is XSI version v3.2b, and XMAKE version 5.1.0. IOBUF is a XC4000 primitive and as the XSI guide (August 94) says all primitives and macros are located in the XSI-supplied libraries. To use this component, yes you have to instantiate it in your VHDL code. I am not familiar with Synopsys SGE interface, I think you should check it with Synopsys if there is any IOBUF.sym that you can use. BTW, I sent you an email today which has an example of how you can use the IOBUF component and how to instantiate it. Hope that helps, Good luck! Yuce BESER (speaking for myself)Article: 1477
I am a university lecturer with interest in the FPGA implementation of computationally intensive algorithms. I am trying to find out information on general-purpose multiple FPGA processing platforms. I have been informed that Metalithic Systems Inc., Utah, supply such a product. I would greatly appreciate anyone who could forward information on this company and its products or indeed any other comparable product. Thanks in advance. Liam. (email: liamm@iscm.ulst.ac.uk)Article: 1478
I've tried asking Xilinx this question with little success: has anyone heard about the timetable for releasing an OrCAD version of the 5200 tools? So far I only have the Viewlogic prerelease. ATdhvaannkcseArticle: 1479
I am looking for a digital input board for a PC (ISA, EISA, PCI, VLB?), any bus will do... I have a 20 MHz, 12 bit A to D, and I need to capture a megabyte or so at a time. It would be preferable for the data acquisition board to have a Lab Window's driver. Any one have any suggestions? Data Translation: No board in the line up (at the time being) Datel: overkill for what I need Pentek: only VME boards Image Technology: Can't fine their current number Please respond by email. MIKE -- Michael Hoffberg /.\ Argonne god of a bitch hoffberg@phebos.aps.anl.gov // \\ Nationa spelled backwards mike@anl.gov //_O_\\ Lab is dog - anonymous Standard Disclaimer Applies /__| |__\ (yes, it is still there)Article: 1480
an222663@anon.penet.fi wrote: >Hello, > I want to simulate the whole circuite I has designed using Orcad or > Viewlogic. I have common chips with Xilinx devices. I would like to > do a "timing" simulation, but I'm not sure if this is possible. > > Could anybody help me? > > Thanks in advance. > > Q. I've done board level functional and timing simulations using Viewsim and SmartModels from Logic Automation (I believe Synopsis bought them). They have models for Xilinx, Altera, and numerous other PLD devices. -- andrew -- Andrew Wheeler WWW: http://vxdwww.lvld.hp.com/home/arw Hewlett-Packard ^^^^^^^^^^^^^ hp internal ^^^^^^^^^^^^^ MXD R&D Systems Division Tel: 1.970.679.3756 e-mail: wheeler@hpisla.lvld.hp.com Fax: 1.970.679.5952Article: 1481
Has anyone used the PS series parts from Prototype Solutions for ASIC emulation in FPGAs? They stack FPGAs in a tower and do all metal routing from "any pin to any pin." Comments? -- Vince Dugar <>< | >>>> "I am, therefore I think." <<<< Boulder, Colorado | All comments here are mine -- they are Vince_Dugar@stortek.com | not representative of Storage Technology.Article: 1482
Just trying to see if I can post something -- -- DanielArticle: 1483
The CADmazing Solutions web site : http://www.cadmazing.com/cadmazing has been considerably updated. Please point your web browsers to the above URL for: - A Comprehensive Updated list of DA-Related Pointers on the Web - New Consulting Career Opportunities - Consultants' Overview - Updated Services Page We are also getting ready for a bigger release in August, which would include : - Consultant Registration Forms to match your skills with our requirements - Papers published on the web - Information about visiting the Silicon Valley - Product Information - World Wide Web Gateway webmaster@cadmazing.comArticle: 1484
In article <3spigr$khd@milo.mcs.anl.gov> hoffberg@hera.aps.anl.gov (Mike Hoffberg) writes: >I am looking for a digital input board for a PC (ISA, EISA, PCI, >VLB?), any bus will do... > >I have a 20 MHz, 12 bit A to D, and I need to capture a megabyte or so >at a time. It would be preferable for the data acquisition board to >have a Lab Window's driver. > >Any one have any suggestions? > > >MIKE >-- >Michael Hoffberg /.\ Argonne god of a bitch >hoffberg@phebos.aps.anl.gov // \\ Nationa spelled backwards >mike@anl.gov //_O_\\ Lab is dog - anonymous >Standard Disclaimer Applies /__| |__\ (yes, it is still there) HI. Emulation Technology has recently been getting an abnormal amount of press on their ET-1Megpluss. It is a logic analyzer which can be configured as 64 chans @ 25MHz, or 32 chans @ 50MHz. Base config is 16 chans @ 25MHz. Memory is 1Meg, so it looks like this exactly meets your needs. Prices start $6295. (408)982-0660 The above is from an article in ECN April-95, p132. I have no association with ET Inc. All the Best, Philip Freidin fliptron@netcom.comArticle: 1485
David J Starr (dstarr@world.std.com) wrote:
: Thanks for you input. What do you mean by "redundant gates"? Could
: you elaborate?
: David J. Starr
___
A -------------\ \
| |-- X { = A or (B and C) }
__ +--/__/
B --| \ |
| |---+
C --|__/ | ___
+--\ \
| |-- Y { = D or (B and C) }
D -------------/__/
This may be mapped as 3 function generators (1.5 CLBs) because the output of
the "and" gate is needed in two places, so it may not be merged into the
following logic. If the "and" gate is duplicated, one for each following "or"
gate, each "and" gate can be merged with the following "or" gate.
I say "may" because I have not tried it. For this trivial example, it's
possible the tools will find the obvious implementation because it is a single
CLB, but for larger cases it is definitely worth putting in the redundant
gates.
The rule of thumb is to include any redundant gates which are needed to allow
the logic to be partitioned into CLBs with each gate in one and only one CLB.
Inverters can be ignored.
--Murdo
Article: 1486Andrew Wheeler wrote Logic Automation has models for Xilinx, Altera and other PLD devices. I would like to know if they have models for FPGA devices. My first question wasn't polite enough: I want to simulate a circuit which includes XILINX FPGA's devices & other commercial devices (HARRIS & MOSEL). Is this possible? Thanks for your help. Q. ---------------------------------------------------------------------------- To find out more about the anon service, send mail to help@anon.penet.fi. If you reply to this message, your message WILL be *automatically* anonymized and you are allocated an anon id. Read the help file to prevent this. Please report any problems, inappropriate use etc. to admin@anon.penet.fi.Article: 1487
Is anyone out there backannotating post place and route timing from Actel, or Synopsis to Leapfrog? I have managed to get an SDF file that looks pretty close to what is needed, but the simulator gives me a lot of "Out of scope" errors. Any advice and hints are welcome. William WilsonArticle: 1488
I know PCMCIA interfaces are being developed with FPGAs. Xilinx has an ap note on specifically that. A PCMCIA application that I am currently developing should use DMA, execpt current PCMCIA host adaptor chips do not support DMA transfer. Future versions will however. I was wondering if it was possible to reconfigure an FPGA at runtime to adapt to whatever features the host adaptor supports? If so, could this lead to a reconfigurable bus interface? Rolande >Still look'n for God<Article: 1489
Geir Olav Berg (g-o-berg@dircon.co.uk) wrote: : Does anybody know if Lattice Semiconductors has got a WWW page somewhere ? I believe I found a little bit of info under http://www.ikn.com.Article: 1490
Merci. That makes good sense. David J. StarrArticle: 1491
I need to find some information reguarding a comparison of VHDL and verilog. I saw something here a while ago but did not think to get it. I would like to see a list of the plus's and minus's of both. -JoeArticle: 1492
Hi All, can anyone suggest some elegant RTL-code for an 8-bit ripple counter? Or know of a good VHDL repository where I could get one? I want to synthesise it onto Actel/Xilinx with Autologic (Mentor 8.2_5). Thanks in advance, Geoff Rubner. gbr@sn2.ee.umist.ac.ukArticle: 1493
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / The 3rd Annual ESNUG User DAC Awards:
_] [_ Sleep Deprivation, MacGyver & DAC '95
- or -
"One Engineer's Review of DAC'95 in San Francisco, CA, June 12-16, 1995"
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
[ Check out http://techweb.cmp.com/eet/docs/eetff.html (EE Times
Interactive) tomorrow or the July 3 hard copy of EE Times for a
photo of the DAC freebies & the awards they received! - John ]
It's amazing what the mildly hallucingenic effect five days worth of sleep
deprivation can do to the engineering mind. I remember in college psychology
there was some question as to whether humans actually dream in color or not.
By my fourth day of getting only 50% of my normal amount of sleep at DAC, not
only did the demos start breathing and exhibiting 3-D properties, I could now
personally attest that we do dream (or at least sleep walk) in color. It was
then I started pondering the big questions...
Why do engineers count by going "0, 1, 2..." instead of "1, 2, 3..."? Is
it possible to build a single pin chip with power, ground, input and output
all time multiplexed? Would "MacGyver", "Batman", "James Bond", and "Dr.Who"
suddenly all become glamorless technerds if they owned up to having an
engineering background? Instead of a circuit built on the assuption that
every question can be answered with a "yes" or a "no" (a binary system), what
would it look like if we based it on "yes", "no", or "no answer" (a trinary
system)? If engineers are so smart, why are they in the middle class? What
if there were no hypothetical questions?
Then I hit upon the one question that I could answer: "What were the ESNUG
User DAC awards this year?"
BIGGEST SURPRIZE AT DAC: Silerity. At first, I thought Alain Hanover (CEO
of ViewLogic) bought Silerity just as part of the deal to get Will Herman
back on board at ViewLogic. But after looking at the Silerity PathBlazer I
was surprized that there was real value there. What I saw was a datapath
compiler that, through brute force, went through all the datapath part and
layout permutations to produce an optimal final design. Cool! Runner up:
Mentor buying Exemplar. (Rumor was MGC might buy IST. IST is focused
primarily in VHDL and is still at the start-up stage. Exemplar is well known
in Verilog and VHDL in both the PC and UNIX worlds. Good choice Exemplar.)
WEIRDEST PRE-DAC IMAGE: Before DAC, ArcSys sent a postcard to customers with
pictures of six people in a "Name The Great Thinkers" contest. The odd thing
was that one "great thinker" appeared to be Lizzie Bordon, a famous ax
murderer from Massachusetts who killed her father and stepmother. Another
appeared to be Machiavelli, author of a book advocating gaining power via
cunning and ruthlessness with no regard to morality (and, incidentally, was
reputed to be the favorite bedside reader of Hitler, Stalin, and Mussolini!)
MOST TROUBLED HEIR APPARENT: SpeedSim. With high speed Chronologics falling
into disarray, Verilog vendors like Intergraph, Frontline, and Simucad have
been salivating at taking second place in the Verilog simulator market. It
appears that SpeedSim's super fast cycle based Verilog racehorse is the heir
apparent, but it's under a dark cloud. Synopsys has been heavily hinting
that they're working on a cycle based simulator of their own, but won't say
if it is Verilog, VHDL, or both.
BIGGEST CINDERELLA AT DAC: The IC place and route companies. With all the
engineering conferences chanting the mantra of "deeeeep suuuub miiiicroooon",
the usually ignored IC place and route companies like ArcSys, Cooper & Chyan,
ISS plus parts of Mentor and Cadence have suddenly come out of the closet
telling mainstream engineers: "Look at me! I'm hot technology!" The grand
pappy of all IC place and route, the once public domain TimberWolf, even made
its commercial debut at this year's DAC.
FIRST TO HACK DACNET AWARD: Unknown. An unidentified PCB EDA vendor managed
to hack DACnet's internal mailing list, get a partial listing of DACnet
account names and send junk e-mail every day promoting their wares. (I can't
get confirmation as to exactly which company did this, because most people
ignored the e-mail infomercial after the first day.) Despite this, a lot of
people enjoyed having the ability to check their secure home e-mail via
DACnet. Afterwards, the DACnet people forwarded the leftover e-mail in our
conference acounts to our home accounts. (A class act!)
BIGGEST LIE AT DAC: The NTT "Consortium." Angry attendees reported that
through Harmonix, Nippon Telegraph & Telephone (NTT), Japan's version of
AT&T, tried to create the image that there was a new "consortium" promoting
their NTT proprietary C-like SFL language as an industry standard in
reconfigurable computers. What angered the researchers at the meeting was
that they were indirectly told that the company with the money (NTT) would
control the "consortium." Also, all technical issues where handled in a hand
waving fashion. One researcher said: "Harmonix/NTT never mentioned the
problems of a reconfigurable logic operating system (the biggest sticking
point in the concept today) nor described how they were going to solve the
dynamic place and route problems, time-based partitioning, nor anything else.
These people were going to decide the industry standard for reconfigurable
computing?!?"
WHAT ENGINEERS TALKED ABOUT: This was the year for the fruity niche tool.
Other than GLOBEtrotter's licence management and admin tools, there was no
one hot EDA "toy" that everyone raved. What people saw was heavily
influenced by what they wanted to see.
The power junkies were seen shooting up around the Epic Design booth on their
'Mill products, Mentor for the Lsim Power Analyst, Systems Science for their
PowerSim and PowerFault, plus Synopsys for their rumored power tools.
The engineering Survivalists saw the world shortage of foundry capacity as a
bad sign and sought out the foundry-independent ASIC solutions offered by
SiArch, Mentor, Compass, Cascade, Sagantec, Aspec, and Meta-Software.
The I-don't-want-learn-another-damned-tool ASIC designers gravitated to the
tools made for them. Synplicity provided a simple, one button FPGA synthesis
tool that took all of 30 seconds to learn and run. Interconnectrix offered a
pricey PCB place and route tool that took in constraints in EE terms (instead
of geometric rules of thumb) to build PCB's that passed timing and signal
integrity specs. HLD Systems offered a general floorplanner that hooks
rather nicely into the Synopsys environment eliminating the need to learn the
25 or so ASIC specific floorplanners. Intellitech offered a general purpose
foundry/synthesis independent BSDL file generator.
Engineer members of the "Glowing Path Pure RTL Level Design" cult sought out
Synopsys HDL Advisor to help them write and analyze their RTL source code for
synthesis *before* synthesis, InterHDL for VeriLint (a killer Verilog syntax
checker) plus their V-to-V (a two way Verilog/VHDL translator) and Cadence's
newly announced RTL level floorplanner called SiliconQuest. Cultists also
noted that Leda pushed a universal VHDL source encrypter while Chronologics
pushed a universal Verilog model encrypter.
Pugilistic engineers said: "Looks like AT&T Design Automation is going to get
into some interesting fist fights with Chrysalis and Abstract Hardware in the
formal verification market, and LogicVision in the BIST market."
A few EDA vendors themselves happily noticed that although Microsoft had a
booth at DAC last year, they didn't this year. (They figured that a 2
billion dollar industry was chump change as far as Bill Gates was concerned.)
MOST CURIOUS NEW COMPANY AWARD: Savantage. These guys created a tool that
looks at a design as a bunch of raw dies and juggles partitioning through the
packaging, PCB, heat exchanger, connector, bonding, assembly, backplane and
enclosure issues with an eye on costs. A manufacturing engineer's dream.
BEST USE OF TERRAIN FOR A DAC PARTY: Synopsys took 400+ customers to
Fisherman's Warf in trolley cars to jump on a boat ride to Alcatraz. (After
having crashed three of Synopsys's DAC parties over the years, I was
personally kind of uneasy when, this time, they sent me an invitation to
visit a prison...) Anyway, we were given a great guided tour of the island
prison and then fed a yummy dinner on a evening cruise in San Francisco bay.
Even anticipating that the customers might get cold on the boat, Synopsys
gave us white sweaters tastefully embossed with a subdued "SYNOPSYS" in the
fabric! (The only down side was after dinner when the ferry was maneuvering
underneath the Golden Gate Bridge with a full moon and a fantastic view of
San Francisco at night. I really didn't want to be next to three engineers
from Data General plus two Synopsys R&D types. I wanted my girlfriend!)
Runner Up: Quickturn took customers for the best night view of the city, the
52nd floor of the Bank of America Building. The jazz band was excellent and
having their own home brew of HDL ICE beer was a hoot!
BEST CONGRESSIONAL JUNKETEER: Yatin Trivedi. Yatin, in a move that would
embarrass even the most corrupt congressman, managed to not only get himself
on the Design Acceleration sponsored harbor cruise, he got his wife, his kid,
his business partner and his business parter's wife on board!
WORST PLANNED DAC PARTY: The Official DAC "Cruise The Mediterranean" party.
Like a fool I thought we'd have a boat ride, but it just turned out to be one
HUGE room with food, beer and music. I did like seeing all the EDA vendors
and customers there, but thought it odd that at a conference which is 95%
male, they had a band playing slow dance music. Then I remembered: "Oh, yea!
That's right. We're in San Francisco!"
PANEL WITH THE MOST POLITICAL INTRIGUE: For a few months the Users Society
for Electronic Design Automation (USE/DA) has been surveying EDA customers
about proposed changes in the way EDA tools are sold. When USE/DA tried to
have a lunch panel on Monday at DAC to discuss the results with the CEOs of
the Big Four EDA companies, the DAC Committee nixed the idea for fear of
stealing from Ron Collett's panel on Tuesday. They wouldn't list the USE/DA
panel in any schedule and forbid the use of signs directing engineers to
where the USE/DA lunch panel was. Plus, they asked the CEOs not to attend!
At the last minute, Collett put an engineer from IBM to represent foundries
plus one of his unknown clients from Siemens to represent user views on his
Tuesday panel. (That is, no USE/DA people who have been working on these
issues were invited.) Despite the intrigue, the Monday USE/DA panel drew
CEOs Wally Rhines (of Mentor) and Aart De Geus (of Synopsys) along with 200
people as an audience. Interestingly, we found some real working data from
polling the audience; customers prefered a model of having all tools always
available to use as needed and to pay later on a per use basis (as opposed to
the PC shrink wrap sales model.)
WORST YET MOST ENTERTAINING DAC PANEL: Collett's five EDA CEOs DAC panel.
The panel consisted of Collett baiting each of the CEOs with embarrassing
issues they had dealt with throughout the year. At any moment I expected the
CEOs to pull out whiffle ball bats and start hitting each other. (Most
attendees voiced dual reactions of thinking the panel was a complete waste of
time, yet also very entertaining.) Richard Goering did a great write-up of
it on page 29 of the June 19th issue of EE Times. One fun quote left out,
though, was Alain Hanover (CEO of ViewLogic) on his rebellious Chronologic:
"Our founding forefathers guaranteed us the right to life, liberty, the
pursuit of happiness and the right to sue each other."
PANEL WITH THE MOST TECHNICAL PROBLEMS: The EE Times Forum. Although this
won best panel last year with its hand held electronic voter boxes that
engineers used to provide immediate feedback to the panelest's statements,
this year the voting boxes went haywire. The first indication was in the
supposed demographics of the audience. Polling indicated that they were
about 50% Synopsys, 50% Mentor, 50% Cadence, 50% Viewlogic and 58% Intergraph
users. (This is virtually impossible.) The second tip off was that no
matter what the panelists said they all got a 2.8 to 2.9 score. (Scoring
went from 1 for "lame" to 5 for "fantastic!".) "After seeing Penny Herscher
of Synopsys get a 2.9 for a great answer, I knew the voting boxes were
broken," said Cadence Marketing bigwig Tony Zingale, "I was tempted to
announce all Cadence software was now free." (I'm not sure whether Tony was
trying to get positive or negative responses from customers with this offer.)
Keeping in the spirit of technical difficulties on the EE Times DAC Forum,
attendees were given inadvertently defective pins that, when you pressed hard
while writing, the spring loaded guts would unexpectedly explode out the back
of the pin! (They make for great office joke pins!)
EDA SEGMENT WITH THE MOST SPYING: ESDA companies. My first impression of
Escalade was Michiel Ligthart whining: "Half of my demos today were given
to Synopsys employees." Yet, the very next day, I laughed finding Michiel
watching the demo of his competitor, Summit Design. (I'm sure he found out
that Summit was adding more pure Verilog features plus beefing up its test
tool.) I'm also sure that the Cadence and Synopsys employees watching the
i-Logix demo noted that i-Logix had added a Motiff style GUI, graphical
simulation that runs with vaguely defined descriptions, and how to generate
different styles of Verilog/VHDL/C code from one behavioral description
(useful for HW/SW codesign.) Runner up: the IC place and route companies.
MOST ENTERTAINING FLOOR SHOW: Compass Design hired a professional comedian
who told submicron jokes that were so corny they were good. Two were: "If a
clock tree falls alone in the woods, does it make a glitch?" and "When I was
young I got into some trouble. My father tied me to VSS. I was grounded
for life." Runner Up: Quickturn did a skit where an engineer was going
to leap off a building to his death because of design verification problems.
Even when the predictable Quickturn Man came to save the day, the customers
in the audience kept yelling: "Jump! Jump! Jump!"
MOST CONTENT-FREE FLOOR SHOW: Either Hewlett-Packard workstations or HP
Developers or HP EEsof (tells you how memorable the sales pitch was) managed
to continuously draw noticeably large crowds for their talks. Quietly asking
some of the crowd why this was such a draw, I got: "Shhh! We just want the
T-shirt!" (Later, I asked engineers what they remembered from the HP
presentation; no one could remember one quote or even what the talk was on!)
"WHERE'S THE BEEF?" AWARD: Cadence. They didn't have a customer party and
even though their exhibit booth was big, their demo suite was two cubicals in
size! Quite a few people were surprized how Cadence appeared to be backing
out of DAC, the various EDA committees like CFI, EDAC, VIUF, and OVI, and the
EDA industry in general. (I guess you don't need this presence to sell
design services instead of design products.)
MOST IMPROVED EDA COMPANY: Mentor Graphics. Watch out Cadence, Synopsys and
Viewlogic! Quite a few engineers noticed that Mentor Graphics now appeared
to be serious about mainstream EDA tools by offering a "real" VHDL simulator
plus adding full Verilog support for their simulation, synthesis and FPGA
synthesis offerings. Adding Verilog allows Mentor to sell to customers who
would have normally not given them the time of day. (Also, Mentor won the
Best Demo Suite Area award with their open tables, free food & soft drinks.)
MOST DISAPPOINTING DAC FREEBIE: ViewLogic's T-shirt. ViewLogic used to be so
hip and with the times with their DAC freebies. The year of the L.A. riots,
ViewLogic gave out baseball bats. The year that the U.S. sponsored the World
Cup in soccer, ViewLogic gave out soccer balls. This year, ViewLogic joined
the ranks of the mundane in giving out bland, white T-shirts. Blah.
BACK TO THE "REAL" WORLD: Checking my answering machine the morning after
DAC, I found out that my girlfriend had phoned the management of EE Times,
because she hadn't heard from me in a week and was worried. The front page
news in the San Francisco Chronicle that day was the mayor "blessing" the new
public toilets on Market street. In the weekend section, the "25th Annual
Lesbian, Gay, Bisexual and Transgender Pride" parade was scheduled on
Father's Day. I thought to myself: "Gosh, it's great to be back in the real
world!" and then happily daydreamed of what the freebies would be like at
next year's DAC in the notoriously decadent city of Las Vegas...
- John Cooley
part-time EDA industry gadfly
full-time contract ASIC/FPGA designer
P.S. If you thought this review was on-the-money or out-to-lunch, please tell
me. I love getting frank, honest feedback from fellow engineers.
P.P.S. In replying, *please* don't copy back this entire article; a 14,400
baud modem attached to a 386 on a sheep farm can handle only so much! :^)
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3567 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 1494
Geoff Rubner <gbr@sn2.ee.umist.ac.uk> writes:
> Hi All,
>
> can anyone suggest some elegant RTL-code for an 8-bit
> ripple counter? Or know of a good VHDL repository where
> I could get one?
>
> I want to synthesise it onto Actel/Xilinx with Autologic (Mentor 8.2_5).
>
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY adder IS
PORT (a,b : IN std_ulogic_vector( 7 DOWNTO 0);
cin : IN std_ulogic;
s : OUT std_ulogic_vector(7 DOWNTO 0);
cout : OUT std_ulogic);
END adder;
ARCHITECTURE ripple OF adder IS
SIGNAL c : std_ulogic_vector(7 DOWNTO 0);
BEGIN
s <= (a XOR b) XOR (c(6 DOWNTO 0) & cin);
c <= ((a XOR b) AND (C(6 DOWNTO 0) & cin)) OR
(a AND b);
cout <= c(7);
END ripple;
You even may make it more general using a generic for the
width of the operands.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY adder IS
GENERIC (width : natural := 8)
PORT (a,b : IN std_ulogic_vector( width-1 DOWNTO 0);
cin : IN std_ulogic;
s : OUT std_ulogic_vector(width-1 DOWNTO 0);
cout : OUT std_ulogic);
END adder;
ARCHITECTURE ripple OF adder IS
SIGNAL c : std_ulogic_vector(width-1 DOWNTO 0);
BEGIN
s <= (a XOR b) XOR (c(width-2 DOWNTO 0) & cin);
c <= ((a XOR b) AND (C(width-2 DOWNTO 0) & cin)) OR
(a AND b);
cout <= c(width-1);
END ripple;
Regards,
Egbert Molenkamp
Dept. of Computer Science
University of Twente
PO Box 217
7500 AE Enschede
the Netherlands
email: molenkam@cs.utwente.nl
Article: 1495Have any of you used Xilinx PCI macros? What has been your experiences? Thanks for your feedback. Chuck Gollnick Arnet CorporationArticle: 1496
With Altera's EPC1213 PROMs being quoted as 12+ week delivery I needed an alternative for my EPF8636 based product. Xilinx EPROMs/PROMs can be used for the EPF8636 and smaller devices. The EPF81188 and EPF81500 would require multiple Xilinx devices. By adding nine (9) one's (1's) to the beginning of the binary PROM data, the Xilinx part appears to the FPGA to be an Altera part. Because of this difference Altera parts probably cannot be used with Xilinx FPGA's. I write a QBASIC program to do the conversion. Anyone interested in details should request details via e-mail as I am not a normal Internet news group user. My e-mail address is 75022.3707@CompuServe.Com. My name is Scott Taylor. -- Scott Taylor, DSP Systems Inc.Article: 1497
-- Scott Taylor, DSP Systems Inc.Article: 1498
SECOND INTERNATIONAL SYMPOSIUM ON
ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS
Sponsored by:
The IEEE Computer Society Technical Committee on VLSI
The IEICE Technical Group on VLSI Design
in cooperation with:
IFIP WG 10.5
The University of Aizu, Japan
AIZU-WAKAMATSU, FUKUSHIMA, JAPAN
MARCH 18 - 21, 1996
***********************
* CALL FOR PAPERS *
***********************
The Second International Symposium on Advanced Research in Asynchronous
Circuits and Systems is being organized as a forum for disseminating
advanced research results on asynchronous circuit and system design.
A major goal of this symposium is to articulate emerging focal areass,
and thereby foster research growth. Special emphasis will
be given to industrial applications and mature CAD tools. To this end,
papers are being sought on all aspects of asynchronous circuit and system
design, as well as in the following focal areas (in no specific order of
priority):
--- Industrial Applications of Asynchronous Design
--- Hybrid Synchro-Asynchronous Systems
--- CAD Tools for Asynchronous Design
--- Testing/Design-for-Testability of Asynchronous Circuits
--- Noise Immunity in Asynchronous Digital Circuits
--- Low-Power Techniques
--- High Performance Asynchronous Circuits
--- Hazard-Free Logic Synthesis and Optimization
--- Design of Asynchronous State Machines
--- Metastability and Related Issues
--- Formal Methods for Asynchronous Design
--- Petri-Nets, Trace Theory and Related Formalisms
--- High-Level Synthesis of Asynchronous Circuits and Systems
--- Asynchronous Design in Commercial HDL Environment
--- Verification of Asynchronous Circuits and Systems
--- Asynchronous Datapath and Processor Design
--- Practical Design Examples
--- Future Trends (Optical Computing, Neural Networks, Nanotechnology, etc.)
Submissions:
--------------
Submitted papers should be no more than 15 pages in 11-point font (or
equivalent) with a 60-word abstract, and should include a cover page with
authors' physical and e-mail addresses, phone and FAX numbers. Prospective
authors should submit papers by October 10, 1995 in one of the following forms:
(1) Send six single-sided copies of the manuscript with a cover-page to:
Alexander Taubin (Async96)
THE UNIVERSITY OF AIZU
Tsuruga, Ikki-machi, Aizu-Wakamatsu City
Fukushima, 965-80 Japan
(2) Email compressed Postscript(tm) files to "async96@u-aizu.ac.jp".
Accepted papers will appear in a published proceedings.
Important Dates:
----------------
------------------------------------------------
Papers due: October 10, 1995
Notification of acceptance by: December 1, 1995
Final Version by: January 5, 1996
------------------------------------------------
Information : from the University of Aizu
e-mail : async96@u-aizu.ac.jp
Phone : (+81) 242 37 2557
Fax : (+81) 242 37 2744
on the World Wide Web at URL: http://www.u-aizu.ac.jp/async96/
Symposium Officers
------------------
General Chair
Tosiyasu Kunii (The University of Aizu, Japan, kunii@u-aizu.ac.jp)
Conference Co-Chairs:
Takashi Nanya (Tokyo Institute of Technology, Japan,
nanya@cs.titech.ac.jp, tel. +81-3-5734-3041, fax: +81-3-5734-2817)
Alex Kondratyev (The University of Aizu, Japan, kondraty@u-aizu.ac.jp,
tel. +81-242-37-2557, fax: +81-242-37-2744)
Program Co-Chairs:
Luciano Lavagno (Politecnico di Torino, Italy, Cadence Berkeley, USA,
lavagno@polv2k.polito.it, tel. +39-11-5644150, fax: +39-11-5644099)
Alexander Taubin (The University of Aizu, Japan, taubin@u-aizu.ac.jp,
tel. +81-242-37-2572, fax: +81-242-37-2744)
Publication Chair:
Takeshi Yoshimura (NEC, Japan, yoshi@swl.cl.nec.co.jp)
Publicity Chair:
Fumiyasu Hirose (Fujitsu Laboratories Ltd, Japan, hirose@flab.fujitsu.co.jp)
Finance/Registration Chair :
Kazuaki Yamauchi (The University of Aizu, Japan, yamauchi@u-aizu.ac.jp)
Local Arrangement Chair:
Yuko Kesen (The University of Aizu, Japan, kesen@u-aizu.ac.jp).
Tutorial/CAD booth Chair:
Michael Kishinevsky (The University of Aizu,Japan, kishinev@u-aizu.ac.jp)
Industry relations:
Tsuneo Ikedo (The University of Aizu, Japan, ikedo@u-aizu.ac.jp)
Masatoshi Sekine (Toshiba, Japan, sekine@srd.ull.rdc.toshiba.co.jp)
US industry representative/chair:
Alan Davis (University of Utah, USA, ald@endo.cs.utah.edu)
US academy representative/chair:
Erik Brunvand (University of Utah, USA, elb@telemark.cs.utah.edu)
European representative/chair :
Steve Furber (University of Manchester,UK, sfurber@cs.man.ac.uk)
Program Committee:
------------------
Kunihiro Asada (Japan) Vyacheslav Marakhovsky (Japan)
Graham Birtwistle (UK) Charles Molnar (USA)
Steven Burns (USA) Steven Nowick (USA)
Tam-Anh Chu (USA) Takuji Okamoto (Japan)
Jordi Cortadella (Spain) Martin Rem (The Netherlands)
David Dill (USA) Jens Sparso (Denmark)
Jo Ebergen (Canada) Robert Sproull (USA)
Ran Ginossar (Israel) Pasupathy Subrahmanyam (USA)
Ganesh Gopalakrishnan (USA) Jan Tijmen Udding (The Netherlands)
Mark Greenstreet (Canada) Stephen Unger (USA)
Mark Josephs (UK) Peter Vanbekbergen (USA)
Sadatoshi Kumagai (Japan) Kees van Berkel (The Netherlands)
Bill Lin (Belgium) Victor Varshavsky (Japan)
Alain Martin (USA) Alex Yakovlev (UK)
Tomohiro Yoneda (Japan)
--
Kind regards
Alexander Taubin
THE UNIVERSITY OF AIZU phone +81-242-37-2572 (office)
Tsuruga, Ikki-machi, Aizu-Wakamatsu City fax +81-242-37-2744
Fukushima, 965-80 Japan e-mail taubin@u-aizu.ac.jp
---- <A HREF="http://www.u-aizu.ac.jp/~taubin/">------------------------
Article: 1499Comp.Arch.FPGA Reflector Monday, 3 July 1995 Volume 01 : Number 268 In this issue: 1: "Xilinx PROMs with Altera FPGAs" from Scott Taylor <75022.3707@CompuServe.COM> Info on subscribing/unsubscribing and posting is at the end of the digest. ---------------------------------------------------------------------- Message: 1 From: Scott Taylor <75022.3707@CompuServe.COM> Date: 1 Jul 1995 06:05:54 GMT Subject: Xilinx PROMs with Altera FPGAs With Altera's EPC1213 PROMs being quoted as 12+ week delivery I needed an alternative for my EPF8636 based product. Xilinx EPROMs/PROMs can be used for the EPF8636 and smaller devices. The EPF81188 and EPF81500 would require multiple Xilinx devices. By adding nine (9) one's (1's) to the beginning of the binary PROM data, the Xilinx part appears to the FPGA to be an Altera part. Because of this difference Altera parts probably cannot be used with Xilinx FPGA's. I write a QBASIC program to do the conversion. Anyone interested in details should request details via e-mail as I am not a normal Internet news group user. My e-mail address is 75022.3707@CompuServe.Com. My name is Scott Taylor. - -- Scott Taylor, DSP Systems Inc. ------------------------------ End of Comp.Arch.FPGA Reflector V1 #268 *************************************** ============================================================================= The preceding was forwarded by the Comp.Arch.FPGA reflector, a service of the Center for Computing Sciences. All opinions are those of the authors. Subscription info. can be found by mailing comp-arch-fpga-request@super.org. A daemon will auto-reply. To post to comp.arch.fpga via this reflector, send your message to comp-arch-fpga@super.org. Problems with the list should be sent to comp-arch-fpga-owner@super.org. =============================================================================
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