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In article <803513923snz@mgnelect.co.uk>, Gush Bhumbra <GUSH@mgnelect.co.uk> writes: > In article <3rp1k7$t4a@lantana.singnet.com.sg> > eddie@merlion.singnet.com.sg "q" writes: > > > I am going through some LATTICE eqns., and trying to understand the > > logic, without having the Lattice manual. Could somebody using Lattice > > explain to me the foll. queries : > To continue with lattice questions, does any body know how to create different clock signals. I am using the PDS stater kit software. What I want is to load data in two different groups of latch inputs, addressed using one dedicated input, and both groups of pins connected to the same bus. Reading the data sheet, it seems that it is possible to define two IOCLks. The software does not allow to edit the clock cell. Thanks Jose RestrepoArticle: 1501
I'm looking for a low-power 22v10-type PLD. I've looked at AMD, Lattice, etc., and the best they seem to have are 'zero-power' (devices that power themselves down internally after some period of inactivity) or 'quarter-power' devices. Still, the best I've seen for 100% macrocell utilization (that's a whopping 10 for a 22v10) at 1-2MHz is somewhere around 10-15mA, neglecting I/O current (that is, assuming all high-impedance loads). I could probably do what I want to do in HC CMOS with well under 5mA, although it would take at least 3 or 4 devices. Is there anything out there that's lower-power than what I've found. Thanks, Jay Kubicky jkubicky@cco.caltech.eduArticle: 1502
I/O clocks have to be defined in "dedicated clock GLB" (see Lattice data book, family arch. desc.), where you can generate whatever clock scheme you like. That clock signal is then routed to all I/O pins. Clock cells are only for taking the signal inside the device, not to include any logic equations. Hope this helps. VeikkoArticle: 1503
In article <3t9u4g$h4n@gap.cco.caltech.edu> jkubicky@cco.caltech.edu (Joseph J. Kubicky) writes: >From: jkubicky@cco.caltech.edu (Joseph J. Kubicky) >Subject: Who makes low-power 22v10-type PLDs? >Date: 3 Jul 1995 23:22:56 GMT >I'm looking for a low-power 22v10-type PLD. I've looked at >AMD, Lattice, etc., and the best they seem to have are >'zero-power' (devices that power themselves down internally >after some period of inactivity) or 'quarter-power' devices. ... >Is there anything >out there that's lower-power than what I've found. >Thanks, >Jay Kubicky >jkubicky@cco.caltech.edu I've been looking for similar solutions, although my applications are, for all intents and purposes, DC. With a battery-powered operation, I'd like to see very low consumption. Erik Blake -------------------------------------------------------------------------- Icefield Instruments Inc. tel: (403) 633-4264 P.O. Box 5567 fax: (403) 633-4217 Whitehorse, Yukon CANADA Y1A 5H4 e-mail: icefield@yknet.yk.caArticle: 1504
Logic Automation (now Logic Modeling/Synopsys) has models for FPGAs PLDs,CPLDs,memories, peripheral devices, microprocessors, etc. We have subscribed to them for 12,000 dollars a seat. Good Luck. From: Kayvon Irani Lear Astronics Corp. 3400 Airport Ave. Santa Monica, Ca 90405 (310)915-6000 Ext. 3696 (310)915-8369 FaxArticle: 1505
>Joseph J. Kubicky wrote >I'm looking for a low-power 22v10-type PLD. I've looked at >AMD, Lattice, etc., and the best they seem to have are >'zero-power' (devices that pow themselves down internally >after some period of inactivity) or 'quarter-power' devices. >Still, the best I've seen for 100% macrocell utilization >(that's a whopping 10 for a 22v10) at 1-2MHz is somewhere >around 10-15mA, neglecting I/O current (that is, assuming >all high-impedance loads). I could probably do what I >want to do in HC CMOS with well under 5mA, although it >would take at least 3 or 4 devices. Is there anything >out there that's lower-power than what I've found. >Erik Blake replies >I've been looking for similar solutions, although my applications are, for all >intents and purposes, DC. With a battery-powered operation, I'd like to see >very low consumption. At the Icc area, all 'z' PLD designs use a sleep/wake mux system, and this gives Icc's in the mA/MHz region. eg Philips 18V8Z is 0,5mA/MHz, Atmel ATF22V10B is appx 1mA / MHz, new ATMEL ATF1500 1mA / MHz (32 regs) Thus for the numbers above, (1-2MHz), you should expect under 5mA from a good part. These postings raise a good point. The PLD vendors are obsessed with SPEED and SPEED, and Icc is only just becomming a spec they bother paying attention to. The low _COST_ of these parts now could allow replacement of many MSI devices, it is a pity their specs let them down, and have not revised with the prices. There are also other factors, yet to dawn on the PLD designers - we can live in hope that they learn from other disciplines.... 1) To include hystersis on the Inputs, allowing PLD's to implement delays, oscillators and input filtering. This also lowers RFI, and reduces clk errors, by ensuring single transistions from slow edges. I have seen the 'Z' wakeup parts completely MISS a slow transisition! 2) RFI is not even being talked about, so it may be a while before that is factored into chip designs. I believe there is a clear demand from more market areas, and this may even be possible from one die design, with different diffusions.. a) The traditional SPEED market, with its steep price curve, but tight constraints on PCB and input slew rates, and poor noise immunity. b) A larger, untapped, Low Power / Low RFI market, with controlled edges, low Icc, and hystersis on the IO lines. This would also have better noise immunity, and allow single sided PCB designs. c) TTL MSI replacement - this requires smarter pinout allocations. d) Industrial and Programmer / Tester IO - this would need a simple PLD - configurable for end use, but with Higher voltage, and higher Iol, and a high IO pin count. e) Configurable MicroSlave, for serial port additions to low end uC. Target is all products with separate Display / button PCB. A simple SPI or i2c bus interface should be built in, allowing user pgm control of pin polarity, IO mix, Pullups, IO type, RST type. Any PLD chip designers care to comment ? ===== Mandeno Granville FAX +64 9 6301 720, 128 Grange Rd Auckland 3 NZ ====== * Developers and suppliers of serious MicroController Embedded Control Tools * * x51 C, Pascal & Modula-2 Compilers, Simulators, Emulators & FLASH Pgmrs * * Contact : Jim Granville . Email above. *Article: 1506
icefield@yknet.yk.ca (Erik Blake) writes: >>I'm looking for a low-power 22v10-type PLD. I've looked at >>AMD, Lattice, etc., and the best they seem to have are >>'zero-power' (devices that power themselves down internally >>after some period of inactivity) or 'quarter-power' devices. >... >>Is there anything >>out there that's lower-power than what I've found. So far as I can tell, the Intel (now Altera) Flexlogic (now Flashlogic) devices give you what you want. The only trouble is that they are perhaps bigger than you feel like paying for. For example, the 740Z takes 1mA/MHz with an intercept at 0mA/0MHz This chip has the equivalent of 4 x 24V10 on it and is one-time programmable eprom + sram. Another device in the Intel book is the iPLD22V10L-5 which is exactly what you want. However, Altera don't seem to be making it. (PLEASE tell me that they are really!) John WallikerArticle: 1507
Anyone know where to find a description of AHDL, Altera's HDL? Thanks.Article: 1508
Hello,
I'm detecting a curious behaviour of Synopsys Simulator V3.3a for HP-platforms.
This simulator tends to break down when complex VHDL descriptions are simulated.
For example the following message occurs:
***Internal system error. Cannot recover.
FAULT CONTEXT
Program : 'vhdlsim'
Release : '3.3a'
Architecture : 'hp700'
Phase : Run-time
Last UI Command : run
Simulation Time : 15 NS
FAULT ID:
''
A step-by-step debugging shows that this abnormal behaviour comes into being when
step 270 at simulator time 15 ns is executed.
The same error messages occurs for example within a process containing an edge-expression
and two signal assignments. When this process is broken into two - one signal assignment per
process - than I can by-pass this error.
So far this error occurs in context with large VHDL programs and so I couldn't write a small
VHDL program which reproduce this error message.
Therefore I use this chance to ask if this error is known - perhaps in another context - and
if any work-arounds does exist?
It is possible to reinstall Simulator V3.2a and to use Synthesis tools V3.3a?
In hope to hear from anybody I say a lot of thanks in advance
Hans Joerg
Article: 1509Hi I'm looking for information on the JEDEC file format thats used by programmers to program 16v8, 20v8, 22v10 etc. A reference to a datasheet, application note, FTP site will be much appreciated. Thanks BushyArticle: 1510
I'm looking for FPGA modules with multiple PCI mezzanine slots and compatibility with 6u VME form factor. Does anyone know of vendors that might make this? Thanks in advance, Jason Gomez GTE email: jason.gomez@msmail.mtv.gtegsc.comArticle: 1511
I'm looking for FPGA modules with multiple PCI mezzanine slots and compatibility with 6u VME form factor. Does anyone know of vendors that might make this? Thanks in advance, Jason Gomez GTE email: jason.gomez@msmail.mtv.gtegsc.comArticle: 1512
Hi! What are the best books/internet resources to learn about VHDL/FPGA/PLDs etc. I have university-level knowledge of digital electronics but never took any VLSI / Design Automation courses. What about S/W? If I bought the $99 Warp for VHDL synthesis of PLDs, can I learn something? Thanks. RaviArticle: 1513
Look in one of the data books. The AMD or Lattice usually have good pictures that also describe the fuse/bitmaps for the simple devices. My AMD/MMI Handbook is a classic for that stuff. :-) Also, if you can get a copy of the early source code for PALASM(tm) or another PLD tool, you can read the code and figure out the bitmaps from there. Sorry, I don't know of an FTP site offhand. Read the comp.arch.fpga FAQ for some clues. The JEDEC file format itself is pretty simple, mostly. But each device has it's own fuse semantics. As for any bigger devices, forget it. Most of those bitmaps are proprietary. --R. Vireday In article <CMILLS.7.00066CF5@eleceng.uct.ac.za> Bushy <CMILLS@eleceng.uct.ac.za> wrote: > Hi > > I'm looking for information on the JEDEC file format thats used by programmers > to program 16v8, 20v8, 22v10 etc. > > A reference to a datasheet, application note, FTP site will be much > appreciated. > > Thanks > Bushy >Article: 1514
In article <3tg2ml$pin@news.jf.intel.com>, Richard Vireday <Richard_Vireday@ccm.jf.intel.com> wrote: >Also, if you can get a copy of the early source code >for PALASM(tm) or another PLD tool, you can read the >code and figure out the bitmaps from there. Sorry, >I don't know of an FTP site offhand. Read the comp.arch.fpga >FAQ for some clues. nic.funet.fi, in /pub/cae/AMD - see PALASM and PLPL. -adrian >>Article: 1515
(Apologies if you've seen this before, I don't think it made it outside the
building last time though...)
Bristol University - Partners in Advanced Computer Technology
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
PACT is a non-profit making research centre for collaborative academic/
industrial projects. Based in Central Bristol PACT provides a pleasant and
stimulating work environment, bringing together researchers from both University
and Industry in partnerships that can more effectively exploit the experience of
both groups.
PACT is currently involved in a collaborative European ESPRIT project in
the area of hardware/software codesign for embedded microprocessor systems. The
project is especially interested in the the development of systems containing
both microprocessors and ASICS or FPGAs.
PACT's role in the project is to help design suitable development tools
for such systems, with particular emphasis on the software development
environment and its integration with the hardware design and simulation tools.
PACT will also be involved in the specification of libraries containing
both hardware and software components, and in verifying the behaviour of
systems constructed using such libraries.
PACT is seeking to recruit one person to join the small team currently
working on this project. The successful applicant will be responsible for
producing a number of demonstration applications using the new tools under
development at PACT. He or she will also be expected to provide feedback
to other team members on the effectiveness of these tools, and to suggest ways
in which they could be improved.
The successful applicant will have some influence on the choice of applications
to be studied. PACT is, however, particularly interested in examining those
areas which coincide with the interests of other groups within PACT, such as:
- Digital Video
- 2D and 3D Graphics
- Digital Signal Processing
- Computer Network Protocols
The work will involve a mixture of both hardware and software development,
consequently applications are invited from candidates with a background in
either hardware or software, coupled with an interest in the other discipline.
Candidates should be able to demonstrate a knowledge of one or more of the
above application areas. A knowledge of C, occam, and/or VHDL will be an
advantage. Experience with a functional programming language may also be useful.
The initial contract will be for a period of 12 to 18 months. Applications are
welcome from recent graduates and/or PhDs interested in gaining experience of
working in the kind of mixed industrial/academic research environment offered
by PACT. Remuneration will be negotiable, based on experience. Applications can
only be considered from candidates who do not require a work permit for the U.K.
Please apply by e-mail, or send/fax your application, including CV and
background information to : Anthony Stansfield, PACT, 10 Priory Rd.,
Clifton, BRISTOL, BS8 1TU
e-mail: ais@pact.srf.ac.uk
Fax +44 (117) 970 7171
(for background information about PACT, see http://talisker.pact.srf.ac.uk/ )
Article: 1516neal@ctd.comsat.com (Neal Becker) wrote: >Anyone know where to find a description of AHDL, Altera's HDL? > >Thanks. Try calling Altera and asking for their AHDL manual. It is pretty short and very understandable. - Russell Petersen petersr@crackle.ee.byu.eduArticle: 1517
This guy should be net-nuked! Not only is he sleazy enough to misuse the newsgroup - which is bad enough - but he is too cowardly to face up to the consequences of his actions - which is much worse. > Although Olga has never seen a newsgroup nor heard of "net-etiquette," > she believes that helping others exceeds the cost of angering those who feel > the net should not be used in this fashion. Excuse me? Helping people? They are procuring! What kind of image are they giving engineers anyway? > IHA (I humbly ask) that you not flame the postmaster of this site. I humbly ask that you get off the pla-net! Catherine Gyselinck ---------------------------- MPB Technologies | Speak softly but carry | gcat@dorval.mpbtech.qc.ca | a +6 two-handed sword | tel: (514) 683-1490 ---------------------------- fax: (514) 683-1727Article: 1518
The University of California, Berkeley, announces two
intensive short courses in San Francisco/Burlingame:
I. "CHEMICAL VAPOR DEPOSITION (CVD) FOR SILICON
INTEGRATED CIRCUITS",
September 11-13, 1995 at the San Francisco Airport,
Burlingame, California
This course is intended to give you a fundamental,
practical understanding of CVD as it applies to
IC fabrication. It also serves as an update for
process Engineers with a background in CVD.
Topics covered: Fundamentals of CVD; Mathematical Modeling
of CVD Processes; Thermal CVD---Epitaxial Silicon and
Polysilicon Films; Thermal CVD---Polysilicon and Dielectric
Films; Thermal CVD---Conducting Films; Thermal CVD---
Selective Deposition of Conducting Films, Barrier
Films; Plasma-Enhanced CVD; CVD Reactors---Atmospheric
and Low Pressure Systems; CVD Reactors---Single-Wafer and
Multichamber Systems.
INSTRUCTORS:
Dennis W. Hess, Ph.D., Professor and Chairman of the Chemical
Engineering Dept., Lehigh University, Bethlehem, PA
Ted Kamins, Ph.D., Project Leader at Hewlett-Packard, Palo
Alto, CA
Arthur Sherman, Ph.D., Consultant in CVD, Palo Alto, CA
FEE: $995
-----------------------------------------------------------
II. "ELECTROSTATIC DISCHARGE (ESD)
IN INTEGRATED CIRCUITS"
October 9-10, 1995, at the San Francisco Airport,
Burlingame, California
This course is for circuit designers, process development
engineers and product/reliability engineers. While most
protection techniques presented emphasize CMOS technology,
the material is applicable to engineers working on other
technologies.
Topics covered: ESD in ICs; Testing for ESD; Basics of
ESD Protection; Failure Modes and Characterization;
CMOS ESD Input Protection; Transmission Line Pulsing;
Wafer Level Monitor; Device Physics; CMOS Output Protection;
Process Effects; Internal Protection; CDM Phenomena
and Protection; Bipolar/BiCMOS Protection; Failure Analysis
Tools; Device and Circuit Simulations; Electrical Overstress;
Case Studies.
INSTRUCTORS:
Ajith Amerasekera, Ph.D., Senior Member of Technical Staff,
Texas Instruments, Dallas, TX
Charvaka Duvvury (course organizer), Ph.D., Senior Member
of the Technical Staff, Texas Instruments, Dallas, TX
Gadi Krieger, Ph.D., President of QualiTau, Inc., Sunnyvale,
CA
Timothy J. Maloney, Ph.D., Senior Staff Engineer, Intel
Corporation, Santa Clara
Tom Polgreen, Ph.D., Staff Modeling Engineer, Dallas
Semiconductor, Dallas, TX.
UC Berkeley Faculty Advisor: Chenming Hu, Professor
of Electrical Engineering and Computer Sciences, UC Berkeley
--------------------------------------------------------
FURTHER INFORMATION:
Reply with your POSTAL ADDRESS and we will send you
a descriptive brochure.
In your message, please mention "CVD/ESD courses".
Article: 1519
UC BERKELEY EXTENSION ANNOUNCES
4 Summer Short Courses at the San Francisco Airport
1. "TESTING ASICS, BGAS, KNOWN GOOD DIE (KGD) AND
MULTICHIP MODULES" August 2-4, 1995 (2.1 ceu)
Topics covered: dynamic simulation at CAE, scan testing
testing laminates, environmental stress screening (ESS)
Instructor: Robert Hanson, M.S.E.E., AmeriCom Services,
a test and manufacturing consulting company. Mr. Hanson
has extensive experience designing test hardware and
operation/test software.
2. "SURFACE MOUNT ASSEMBLY AND FINE PITCH" August 8-9, 1995
(1.4 ceu)
Topics covered: introduction to SMT/FPT, SMT/FPT
components, SMT substrates, types of SMT/FPT assemblies,
design for manufacturability, SMT process details,
typical defects and inspection, rework/repair, starting
an SMT operation.
Instructor: Charles Hutchins, Ph.D., an independent
consultant recognized worldwide for his experience in SMT.
He has been President of the Surface Mount Technology
Association, and is the author of 30 technical papers
and the textbook "Understanding and Using Surface Mount
and Fine Pitch Technology."
3. "BALL GRID ARRAY (BGA)/FLIP CHIP AND CHIP ON BOARD (COB)
TECHNOLOGIES" August 10-11, 1995 (1.4 ceu)
Topics covered: background, package types, properties
and characteristics, chip attachment and interconnection,
interconnection materials, printed wiring board design
and specification, second level assembly, process control,
reliability, future technology directions.
Instructor: Charles E. Bauer, Ph.D., Managing Director
of TechLead Corporation, an engineering and management
services company. He has more than 17 years experience
in electronics packaging, interconnection and assembly
from printed wiring boards, ceramic hybrids and IC
metallization to multichip modules, micropackaging,
smart cards and most recently PCMCIA design and assembly.
4. "MULTICHIP MODULE (MCM) DESIGN" August 14-16 (2.1 ceu)
Topics covered; introduction, materials, resistor design,
thick film, thin film, MCM technology, CAD, thermal
management, assembly processes, screening techniques.
Instructor, Al Krum, M.S.E.E., a manager at Hughes
Aircraft where he has more than 20 years experience
in design, test and manufacturing of microelectronic
packaging, including hybrids and multichip modules.
He is the author of numerous papers in the field, and
holds 2 patents.
For a brochure describing these courses in detail please
contact us as follows:
e-mail to: course@garnet.berkeley.edu
fax to: 510-643-8683 (att: Engineering)
write to: Continuing Education in Engineering
UC Berkeley Extension
2223 Fulton St.
Berkeley, CA 94720
please specify "microelectronic packaging and test courses"
Article: 1520Geoff Rubner <gbr@sn2.ee.umist.ac.uk> wrote: >Hi All, >can anyone suggest some elegant RTL-code for an 8-bit >ripple counter? Or know of a good VHDL repository where >I could get one? >I want to synthesise it onto Actel/Xilinx with Autologic (Mentor 8.2_5). >Thanks in advance, >Geoff Rubner. >gbr@sn2.ee.umist.ac.uk If you want to use Actel chips, you could probably do much worse than use ActGen to generate the module for you. The results will probably be much better than whatever you can get with a VHDL description. Of course, I might be wrong... Nacho de los Rios 100611.1036@compuserve.comArticle: 1521
I want to apologize for the annoyance caused by yesterday's anonymous posting to this group. The posting did not originate from our site, but rather was sent to the automated (majordomo) mailing list server for comp.arch.fpga, which in turn forwarded it on to the newsgroup. We have taken steps to try to prevent this problem in the future. -jeff ------ Jeffrey Arnold IDA Center for Computing Sciences (formerly the Supercomputing Research Center) 17100 Science Dr. Bowie, MD 20715 email: jma@super.orgArticle: 1522
Hello out there, as the subject states I have trouble reading EDIF files with the Altera MAX+plus II software. I tried to feed it with an third party EDIF file. It warns about some things like or1, or2 and such differing from the LFM file. When I change the vendor the complains change. The final error is Error: I/O error can't open file 'c:\....\proj.cnf' The help says this would be due to write protected disk or disk full. But this should be false because there are about 50 MByte left. I also tried to feed an EDIF file generated by the very same software in. But then the compiler complains it can't find some 'delay' design files. I never used those explicitly thus they must have been inserted by the compiler. Now I don't know where they should come from. Anyone having expeiences at this field? Thanks Sure, I should consider asking Altera -- well I did. I mailed to the Altera hotline, but all I get from there is an automatic response telling me my that my question is scheduled. /JerryArticle: 1523
Hi, Is it possible to design and simulate connected tri-state outputs using Abel5. For example, connecting to an 8-bit bus using multiple 74HC373's, and only allowing one 373 at a time to access bus via the output enable lines. My code for the criteria defined, compiles but will not let me do a simulation, halts totally. I need to know if I am missunderstanding the software or I am doing something very silly. The final design will implented using fpga's for Actel. Before anyone suggests it, I know and can implement a solution using Actel Orcad library and defining a schematic to represent the design. I have already waited a week for Abel technical support people to get back to me with a solution, so any help from anyone would be greatly welcomed Herbert Larbie (Forgive the typos)Article: 1524
NOW AVAILABLE: 1995 COMPUTER BUYER'S GUIDE, Version 1.3. From computer systems to multimedia, software to communications, and video to printers, this guide includes comprehensive coverage of all computer hardware and software products. The guide gives you thorough evaluations, buying advice, and valuable tips. It also shows you the best products for each category of computer hardware and software. A must for anyone planning a high-tech purchase! For a FREE demo, download the following file: ftp://ftp.coast.net/SimTel/win3/info/95cbg13.zip To install the guide, unZIP the file and run SETUP.EXE in Windows. NOTE: Requires Windows 3.1 or higher. Shareware. Uploaded by Computer Help Publications. Computer Help Publications 76413.1613@CompuServe.COM -- Computer Help Publications 76413.1613@CompuServe.COM
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