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Just a followup to the question about IO registers. I found the same problem but worked around it crudely by hand placing the registers in the IO cells using the floorplan editor. Interestingly what happened is the the report file and timing analyser saw this correctly but turning on the fan-in display in the floorplan editor showed no connection to the IO register. The combinatorial logic feeding it was show as connecting direct to the IO pin. Note that I am only evaluating the Altera tools but the addition of the floorplan editor is a real boon The auto-place tools are now much better but will not get my design to the 66-75Mhz target speeds. The last time I evaluted them I was only trying for 50 MHz. The only real beef I have is with the input registers. When using these the timing analyser shows the need for 5-6 nsec. of hold time; very difficult to guarantee with fast CMOS logic. _________________________________________________________________________ Dr. Richard Filipkiewicz phone: +44 171 700 3301 Algorithmics Ltd. fax: +44 171 700 3400 3 Drayton Park email: rick@algor.co.uk London N5 1NU EnglandArticle: 1601
In article <3v2msn$j85@moorgate.algor.co.uk>,
Rick Filipkiewicz <rick@news.algor.co.uk> wrote:
>
>The only real beef I have is with the input registers. When using
>these the timing analyser shows the need for 5-6 nsec. of hold time;
>very difficult to guarantee with fast CMOS logic.
It is always a good idea to put input flops in the core (not IOC flops)
in order to reduce the hold time. The reason is that clock from dedicated
input has longer delay time (7-8 ns) to reach IOC flops than that of input
signals (2-3 ns).
> _________________________________________________________________________
>
> Dr. Richard Filipkiewicz phone: +44 171 700 3301
> Algorithmics Ltd. fax: +44 171 700 3400
> 3 Drayton Park email: rick@algor.co.uk
> London N5 1NU
> England
Best Regards,
--------------------- My opinion only ------------------------------------------
Qian Zhang Bell-Northern Research, Ltd Ph.: (613) 765-2485
H/W System Modelling P.O. Box 3511, Station C Fax: (613) 763-4222
Ottawa, Ontario, Canada, K1Y 4H7 Email : qzhang@bnr.ca
--------------------------------------------------------------------------------
Article: 1602>>In article <3uh2ms$ba@yama.mcc.ac.uk> mkh@sn2.ee.umist.ac.uk (VLSI) writes: >>>From: mkh@sn2.ee.umist.ac.uk (VLSI) >>>Subject: ACTEL PLACE AND ROUTE >>>Date: 18 Jul 1995 19:40:12 GMT >> >>>Please could you tell me how you add critical (fast/medium/non-critical) >>>properties to NETS on ACTEL Designs on Mentor. >> >>>The Action Logic System (ALS) manual is of no help at all. On the PC you can add a file called <job>.crt which contains a list of critical nets of the form: DEF top. NET LBUS1/$1N11;;CRT:F. NET LBUS1/$1N9;;CRT:F. END. The file has to be in the same directory as for example the .ipf file that defines the pin out. Note that in the above example LBUS1/$1N11 is a net name from a Viewlogic system. MikeArticle: 1603
Net criticality can be done in Mentor by selecting the net in the schematic and adding a property. The property name is ALSCRT and the value is either:Article: 1604
Net criticality can be done in Mentor by selecting the net in the schematic and adding a property. The property name is ALSCRT and the value is either: F for fast critical M medium critical U for default. This app note is available from the Actel Action Fax: 1-800-262-1062. Document number: 5302 - JEFF WETCH wetch@actel.com Actel Field Application EngineerArticle: 1605
What does <anyone> think of Lattice, esp via their PDS+ tools for Viewlogic? We're thinking of going that way. Any pitfals? Raves? Thanks! -- ---------------- James Bock, Engineer e-mail: jim@pccrd.mv.com En Technology, Inc. 78 Elm St., POB 657 TEL: 603/863-1904 Newport, NH 03773-0657 FAX: 603/863-9310 --Entropy isn't what it used to be.Article: 1606
In article <DCBtzF.7sM@mv.mv.com>, Jim Bock <jim@pccrd.mv.com> writes: |> What does <anyone> think of Lattice, esp via their PDS+ |> tools for Viewlogic? We're thinking of going that way. |> |> Any pitfals? Raves? |> |> Thanks! |> |> |> -- |> ---------------- |> James Bock, Engineer e-mail: jim@pccrd.mv.com |> En Technology, Inc. |> 78 Elm St., POB 657 TEL: 603/863-1904 |> Newport, NH 03773-0657 FAX: 603/863-9310 |> |> --Entropy isn't what it used to be. |> I have been using Lattice HDPLDs (1024,1032,1048) for the past 3 years. I like the price/performance of these parts. My design environment is DATA I/O Synario. The front end design is schematic and ABLE, with the back end simulation being the SILOS III verilog simulator. The Lattice "device kit" for Synario and Lattice PDS+ ABLE work well with Synario, but I have never used Viewlogic with the Lattice parts. A "rave" would be the verilog simulator. It is both easy to use and very powerful. I try to stay away from VIEWSIM as much as possible....... Bill Banzhof email: bill@xlnt.com XLNT Designs TEL: 619-487-9320 15050 Avenue of Science FAX: 619-487-9768 Suite 200 WEB: http://www.xlnt.com San Diego, CA 92121Article: 1607
NeoCAD's Timing Wizard will output the message: "xxx circuit loops found and disabled." for each asynchronous circuit loop it encounters while analyzing the timing preferences for a design. The Timing Wizard defines an asynchronous loop as any CLB output that has a path to itself from its input(s) via combinational logic and/or transparent latches. The number of loops detected is a function of the design and its timing preferences, and can get quite large in combinational circuits that contain buses in data paths that are cyclic. The loops in your test design may not be detected due to the design's timing preferences, CLB programming, or the presence of synchronous logic. Walt Manaker Xilinx, Inc.Article: 1608
In <3v33ki$1328@usenetw1.news.prodigy.com> CQEM17A@prodigy.com (Jeff Wetch) writes: >Net criticality can be done in Mentor by selecting the net in the >schematic >and adding a property. The property name is ALSCRT Of course. That's exactly what I would have named that property. NOT! Why not CRITICALITY? Chuck Gollnick ArnetArticle: 1609
Peter Fenn <peterf@electrosolv.co.za> wrote: > > Hi > Anyone out there with feedback/comment/critism of Xilinx EPLD's? > I need to make decision whether to use Altera or Xilinx in a new design. > I am already using Xilinx XC3195A FPGA's but need fast CPLD/EPLD devices on the same board > > Thanks- > PETER FENN. In my (albeit limited) experience with both Altera and Xilinx parts (Xilinx FPGA, altera PLD), you are probably better off to stick with the Xilinx EPLD, as long as one of the available parts suits your design. The reason for this is simply that the Altera development system (Maxplus II) is not as good as the Xilinx software (IMHO), and the added expense of buying the development system, and learning to drive the different environment is probably not worth the trouble. Of course, if what you're doing won't fit in the Xilinx parts, then I guess you'll have to buy the Altera software. At least it's real easy to use. :) In terms of capability, the Altera PLDs and Xilinx EPLDs are fairly well matched (price/performance), but Altera seems to have a wider range with more big parts. Cheers, Craig Jackson, Technical Officer, Orroral Geodetic Observatory.Article: 1610
In <DB9pqx.A33@gpu.utcc.utoronto.ca>, ravi@gpu.utcc.utoronto.ca (r. bansal) writes: > >Hi! > >What are the best books/internet resources to learn about VHDL/FPGA/PLDs etc. >I have university-level knowledge of digital electronics but never took >any VLSI / Design Automation courses. What about S/W? If I bought the $99 >Warp for VHDL synthesis of PLDs, can I learn something? > >Thanks. >Ravi > > There is a VHDL book by Fred Perry that is pretty good, I think it is called 'VHDL Design'. I use the Cypress Warp compiler and have not had any problems at all. The packaged simulator, 'Nova', is however the worst simulator I have ever used, but it is still possible to simulate your design with a lot of work. Warp comes with around 50 sample VHDL programs and library VHDL source code for standard logic functions. (IO's, buffers, counters, and standard 74xxx logic chips) There is also a VHDL compiler by Green Mountain that is supposed to be good and cheap. Their WWW page is 'http://together.net/!thibault/' Good luck. Tom Harrah harrah1@ibm.netArticle: 1611
> There is a VHDL book by Fred Perry that is pretty good, I think > it is called 'VHDL Design'. I think you mean Douglas Perry, and "VHDL". Actually, I think it's dreadful! AshleyArticle: 1612
Can anyone tell me whether CUPL Expert is worth purchasing? I am looking for a decent package that will support PLDs and CPLDs from multiple manufacturers... Particularly the MACH, and possibly Altera or Cypress. I realize I can get free or low cost software from each of these manufacturers, but then I am locked into their product. Any help would be appreciated!Article: 1613
The: > ESNUG guy writes: > > P.S. Keep those letters with checks for / cans of dog food coming! > I must admit I don't understand this "dog food for Joe Costello" thing. Seems to me we should be sending feta cheese, olives, anchovies, ... things like that. Those are the primary ingredients for Geek food, aren't they? ......never mind. -- R.E.Vreeland TRW Space & Engineering Group, Timecards and hardware. Fighting entropy, authenticating myself, just foolin' around. Support the Constitution of the United States. That includes Amendments 2, 9 and 10 as much as any others.Article: 1614
Hey Pete; When was the last time you designed a board on Allergo ?? Rel 1.0..?? Intimately involved...in your dreams. How bout, if I send some Meow Mix to PCD.. Later Pete +++++++++++++++++++++++++++++++++++++++++++++++++ Louis T. Dallara http://www.waterw.com/~ldallara/index.html ldallara@waterw.com ldallara@resd.vf.ge.com +++++++++++++++++++++++++++++++++++++++++++++++++ > > From: pwaddell@mfi.com (Pete Waddell) > > >John, as Editor-in-Chief of Printed Circuit Design magazine I'm intimately > >familiar with all of the Cadence Allegro, Composer (Concept) and BoardQuest > >products. I alerted my associates upon hearing about your dog food drive > >for Joe Costello and we laughed so hard we cried. (John, you've outdone > >yourself this time!) I passed the hat around and collected $24.00, three > >washers, and one homemade Mentor POG disk for our beloved Joe. Please tell > >Joe we cheerfully wish him "Bon Appetit!" > > > > - Pete Waddell, Editor-in-Chief > > Printed Circuit Design magazine > > From: "Anonymous" at Digital Equipment Corporation > > >John, enclosed is a check for $11.00 to buy a 20 lb bag of "Kibbles'N Bits" > >as marked on your order form. Could you please take a marker & relabel the > >bag as "Quibbles On Bits" in "honor" of Cadence's decision to drop support > >of DEC platforms after protracted negotiations? Thanks for the relabeling! > > In reference to my stating that I'll personally collect and deliver all the > dogfood to Cadence Chelmsford, Jeff Markham (markham@cadence.com) replied: > > >I'll make sure the dobermans are aware of your delivery. > > > > - Jeff Markham, Cadence Design Systems > > This explains much if Cadence has Dobermans wandering the hallways as part > of some sort of bizzare employee discipline/retention plan! :^) > > - John Cooley > the ESNUG guy > > P.S. Keep those letters with checks for / cans of dog food coming! > >=========================================================================== > Trapped trying to figure out a Synopsys bug? Want to hear how 3661 other > users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)! > > !!! "It's not a BUG, jcooley@world.std.com > /o o\ / it's a FEATURE!" (508) 429-4357 > ( > ) > \ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys, > _] [_ Verilog, VHDL and numerous Design Methodologies. > > Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 > Legal Disclaimer: "As always, anything said here is only opinion."Article: 1615
We are looking for PLD's ( FLASH or GAL) with HYSTERSIS on the Input lines, does anyone know of any brand that offers this feature in a variant of 16V8, 20V8, 18V8, EP610 etc ? Seems all suppliers are ignoring an important market segment here in the rush for the last nS. We have many application areas where a 25-50nS low RFI PLD + Hystersis could be very well applied. Thanks for any suggestions. jim granville.Article: 1616
Anybody works designing hardware algorithms with FIR and IIR filters for video processing ? Email: santi@glup.eleinf.uv.es Santiago Felici Castell.Article: 1617
About a month ago I think I read about somebody that built a complete 16 bit processor with vga display and keyboard driver in 4 Xilinx FPGA's. It came with GIF's showing the casing and layout. I seem to have lost the files. Can somebody please point me in the right direction? Please e-mail me at pbadenh@firga.sun.ac.za Thanks PeetArticle: 1618
Yep, I designed a 5X5 convolution filter into an ORCA 2C04 using a distributed arithmetic approach. It has 5 parallel inputs of 8 bits each, and internally converts the 5 bytes into 5 serial bit streams which are fed to a bunch of FIR filters that sum to a 12 bit output. With an 80 MHz system clock, the throughput is 10 Million convolutions per second. Total gate count is about 3000 gates (it uses 75% of the nominal 4000 gate device). The design is done in VHDL with Exemplar, but uses a number of hand designed hard macros for high speed. I can give this design out freely, but you need a VHDL compiler and ORCA foundry to make sense of the hard macros. John McCluskey J-Squared Technologies J.McCluskey@ieee.org (don't bother trying to reply to this post, the return mail path is broken) use the ieee address above.Article: 1619
I wish to implement some dual port memory with standard SRAM and a PLD. I would be interested in knowing some strategies others have used for this purpose. Appreciate any input you provide. Rolande Kendal < Still look'n for God >Article: 1620
Peet Badenhorst (pbadenh@firga.sun.ac.za) wrote: : About a month ago I think I read about somebody that built a complete 16 : bit processor with vga display and keyboard driver in 4 Xilinx FPGA's. : It came with GIF's showing the casing and layout. I seem to have lost the : files. : Can somebody please point me in the right direction? : Please e-mail me at pbadenh@firga.sun.ac.za : Thanks Peet please post ! Thanks. Marco -- Marco Schmidt schmidt@peanuts.informatik.uni-tuebingen.de kunz@irc http://wsiserv.informatik.uni-tuebingen.de/~schmidtArticle: 1621
In article <3voo9r$98n@steel.interlog.com> kendal@interlog.com (Rolande Kendal) writes: >I wish to implement some dual port memory with standard SRAM and a PLD. > >I would be interested in knowing some strategies others have used for this purpose. > >Appreciate any input you provide. > >Rolande Kendal < Still look'n for God > > True (tm) Dual Port RAM requires sepparate address and data paths to the memory, and memory cells that can support two transactions at the same time. If the memory primative you are using cant support this, then what you end up with is an interesting engineering challenge. Your posting implies this because you request 'standard' RAM plus logic. Typically you will need to evaluate the agregate bandwidth that you need from each port, add them together and thats the minimum bandwidth you will need from your memory. The logic you build will have to arbitrate between the two requesters. You have to deal with contention, and hogging from either side. If the two requesters live in different clock domains, then your arbiter has a non-zero probability of going metastable. If the memory is synchronous, then you will be switching clocks too, which is not good under any circumstance. If the RAM is async (most RAMs except the most recent are async) you will need to create write logic for each port, managed by the arbiter. Any memory that needs an arbiter between it and the requester adds the complication that the memory may not be be ready when the requester asks for it. An easy example: Two requesters each running off the same clock, at 10MHz, Synchronous RAM, and the requesters dont mind waiting till the end of the cycle for the data. soln. build a memory that cycles in 50nS, and give a 50ns slice to each requester. no need for arbitration. Slightly harder: Two requesters, same clock, 40MHz, one needs to do sequential access only, and sweeps thru memory, doing a transfer every 25nS, the other does random accesses, and takes 8 clocks per transfer. soln. Use VDRAM Harder still: Two requesters, different clocks, 100nS cycle time for one, and 250nS cycle time for the other. Both need to be serviced in 1 cycle (100 or 250nS), neither does back to back transfers. Soln. use 20MHz clock (lock to 100nS system) to run a two stage arbiter, and use 50nS RAMs, and some pipelining. Extra Credit: Eight requesters, all on their own clocks, nominally 66MHz, but not phase locked. All can make burst requests, and all can tollerate latency upto 1/6 th of a maximum length burst, and all can have their burst terminated and restarted. Soln. This is what I get paid for :-) Some others options include prefetching data during idle time, to avoid contention (only works if you can predict addresses (i.e. in a FIFO application)), or use a small amount of real dual port memory to handle mailbox/semaphore type stuff, and move the arbitration from the hardware domain back to the host software (many applications are like this). Or, use the new Xilinx XC4000E series that has beautiful highspeed dual port memory, with a synchronous interface for writing, and an async or sync interface for reading. enough for now, it's 4:30 AM, and it's time I went to bed. All the best Philip Freidin fliptron@netcom.comArticle: 1622
Has anyone found a way to use the register input mux without having to make a macro? (Using NeoCad 6.1.1 software).Article: 1623
double sided surface mountArticle: 1624
I'm considering using double sided surface mount PCB and would very much appreciate any info/ pros & cons that anyone can provide.
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