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YIKES! Today's the deadline to get the early registration rates for this
year's SNUG meeting at the Red Lion Hotel in San Jose, California coming up
in 5 1/2 weeks (Weds-Thurs-Fri on March 22-24)! (About 325 (+/-) users get
together here to discuss Synopsys horror & success stories then. A lot of
people also attend the Open Verilog Conference the following Mon-Tues-Weds
March 27-29 and get weekend airfare rates.) SNUG rates are:
On or Before Feb. 17 After Feb. 17th
-------------------- ---------------
SNUG registration: $100.00 $150.00
SNUG tutorials: $50.00 per $75.00 per
To register for SNUG call (800) 344-SNUG, FAX (503) 690-6906 or e-mail
"designinfo@synopsys.com" -- Personal checks, VISA, Mastercard and American
Express all accepted (although I personally don't recommend sending credit
card info via e-mail. Phone instead.)
---- ---- ---- ----
Synopsys is also doing something they're describing as "Mini-DACs" all over
the country the next few weeks. This is a good opportunity to actually see
some of their current & new tools at a site near you (and then you can tell
me if you thought my review on DesignSource & HDL Advisor was on-the-money
or not!) Bellow is the schedule for their Mini-DAC's in the American
Southeast:
Synopsys American Southeast "Mini-DAC" Schedule
-----------------------------------------------
Austin, TX Feb 21: Austin Convention Center (3rd and Red River)
Dallas, TX Feb 23: Harvey Bristol Suites (Coit and LBJ)
RTP, NC Feb 28: Radisson Governors Inn (NC 54 and I-40)
Atlanta, GA March 2: Atlanta Civic and Cultural Center
(6400 Sugarloaf Pkwy)
Orlando, FL March 7: Embassy Suites (8100 Lake Avenue)
Ft. Lauderdale, FL March 9: Sheraton Executive Port Hotel
(2440 West Cypress Creek)
If you're interested in going to a Synopsys "Mini-DAC" near you, call your
local Synopsys FAE real SOON (or you might miss it) and he'll get you in.
- John Cooley
the ESNUG guy
P.S. For you Austin, Texas Synopsys Users: I'll actually be at your
Mini-DAC to meet you and the Synopsys field staff there this upcoming
Tuesday. I look forward to meeting *ya'll* face-to-face.
See! -- I'm already getting my Southern twang ready! :^)
-----------------------------------------------------------------------------
__)) "Glass ceilings? Name ANY goat farmer who's made it into management!"
/_ oo
(_ \ Holliston Poor Farm - John Cooley
%// \" Holliston, MA 01746-6222 part time Sheep & Goat Farmer
%%% $ jcooley@world.std.com full time contract ASIC & FPGA Designer
Detailed SNUG info follows
-------
Welcome to SNUG 1995
Synopsys invites you to the Fifth Annual Synopsys Users Group (SNUG=81)
Conference at the Red Lion Hotel in San Jose, California, on March
22-24, 1995.
What is SNUG?
SNUG is an open forum that provides Synopsys' users an opportunity to
exchange ideas, discuss problems and explore solutions. It also gives
users a chance to meet with Synopsys executives, developers and
application engineers.
The program is highly technical and developed by users with an emphasis
on customer issues. The SNUG Technical Program Committee is
responsible for the content of all breakout sessions. If you would
like to participate in this process, contact Jeff Flieder at the
address shown below.
Why is it important?
SNUG provides a unique opportunity to meet other Synopsys users. The
program is designed to address a variety of design issues. User
breakout sessions provide unique solutions to various design problems.
ASIC vendor sessions provide specific techniques for building
successful chips. EDA tool vendor presentations explore other EDA
products which leverage Synopsys High-Level Design tools.
What's new this year?
SNUG 1995 is the site of the First Annual Design Competition. This
competition gives you an opportunity to match your design skills
against other Synopsys users. Winners will share their design tricks
with you.
You will also get a sneak preview of upcoming Synopsys Solutions, and a
chance to examine some third party products as well.
Feel free to pass this program on to any of your colleagues who are
familiar with Synopsys. This year's program promises to be extremely
exciting. Don't miss it!
Jeff Flieder
SNUG Technical Program Chair
(719)528-7718, fax (719)528-7635
fmicos!splinter!flieder@uunet.uu.net
Ken Nelsen
Synopsys Applications
(415)694-1771, fax (415)694-1864
knelsen@synopsys.com
Schedule
Wednesday, March 22
Tutorial registration 12:00 - 2:00
Tutorial sessions 2:00 - 5:00
Welcoming cocktail party/Synopsys new product 5:00 - 7:00
fair
Thursday, March 23
General session registration / breakfast 7:30 - 9:00
Welcome / agenda 9:00 - 9:15
Synopsys Direction (Aart de Geuss, President) 9:15 - 9:45
Breakout sessions 10:00 - 11:30
Topics include: User sessions, Design competition
Lunch 11:45 - 1:00
Breakout sessions 1:15 - 2:45
Topics include: User sessions, Design competition
Breakout sessions 3:00 - 4:30
Topics include: User sessions, Design competition
Services Round Tables 4:45 - 5:15
Keynote Speaker 5:30 - 6:15
Wrap-up 6:15 - 6:30
Cocktail party/EDA tool vendor fair 6:30 - 8:30
Friday, March 24
Tutorial registration / breakfast 7:00 - 8:00
Tutorial sessions 8:00 - 11:30
Detailed Description: General Session
Thursday, March 23
SNUG Keynote Speaker - John Gage of Sun
John Gage works for Bill Joy, the Chief Technical Officer of Sun,
and is responsible for Sun's reelationships with the world scientific
and public policy communities, international scientific institutions
and groups developing new forms of scientific research involving
computing.
He is on scientific and advisory panels of the United States National
Science Foundation, the US Congress Office of Technology Assessment,
the European Institute of Technology and the United States National
Academy of Sciences. He has recently been appointed to the US National
Research Council Mathematical Sciences Education Board.
He is a member of ACM, IEEE, SIAM, AMS, AAAS, and SMPTE.
He attended the Harvard Business School and the Harvard Graduate
School of Public Policy. He did doctoral work in economics and
mathematics at the University of Berkeley at the same time as Bill Joy.
Gage subsequently left Berkeley with Joy start Sun in 1982.
Gage is on the Board of Directors of Unicode, an industry consortium
of IBM, Microsoft, Apple, Novell, Sun, GO Corporation, and others
to provide multilingual capability in all world scripts for all
documents and applications.
User Breakout Sessions
These sessions are always the hit of the conference. Hear Synopsys
users' experiences on specific topics. Each user breakout session will
consist of two presentations, thirty minutes each, with another thirty
minutes for questions and answers.
Preliminary topics include:
Design Compiler Breakout
Synthesis strategy examples will be presented in this session.
Design Reuse Breakout
This session provides real examples about how to effectively implement
design reuse.
Design Compiler Breakout
Synthesis strategy examples will be presented in this session.
Test Synthesis Breakout
With the increasing complexity of current ASIC designs, you need to
design-in testability from the beginning of your design cycle. This
session will focus on design-for-test issues in high level design.
Submicron Design Breakout
The quality of a synthesized design is only as good as the timing
accuracy of the models being used in the synthesis process. This
session explores real world techniques for accurately modeling and
building a submicron design.
Simulation and Verification Breakout
This session is intended to explore different verification techniques
through different phases of the design cycle.
Semiconductor Vendor Sessions
Back by popular demand! Feedback from last year's sessions was very
positive. This year we will expand to two sessions. This gives you an
opportunity to hear about the latest technologies available from the
semiconductor vendors and their recommended customer design flow using
Synopsys tools.
EDA Tool Vendor Sessions
New this year! These sessions have a format similar to the
semiconductor sessions. They are an opportunity to see other EDA
vendors show how they can help you leverage your high level design
tools from Synopsys.
Design Competition Sessions
New this year! These sessions provide you with an opportunity to work
with other high level designers and compete to see who can build the
best design. Due to hardware limitations, the competition
participation will be limited. Teams will be formed on a first come,
first serve basis. A $1000 prize will be awarded to the winning team.
Sign up for the competition when you register. Participants will be
notified of final team composition and details as soon as they become
available.
Services Round Tables
Meet members of Synopsys' services staff face to face. Confirmed topics
include:
Surfing the Internet
Find out what tools are available to help you explore the Internet, and
get a glimpse into the future of automated customer services.
The Support Center Summit
Meet with members of Support Center, and discuss ways for you to work
together more effectively.
Half-Day Tutorials Wednesday, March 22
New for SNUG '95: Speed Optimization Symposium
This session is intended for experienced synthesis users who are
interested in a comprehensive methodology for speed based optimization
using Design Compiler. A "Baseline" methodology for speed optimization
will be presented and then a panel of various experts from Synopsys
will discuss their favorite tricks for optimizing high performance
designs. This session is repeated on Friday.
New for SNUG '95: Behavioral Synthesis Using VHDL
This session is intended for any synthesis user interested in
behavioral synthesis. Hardware designers are frustrated with lengthy
IC design cycles for increasingly complex, data-intensive, algorithmic
applications. This tutorial will show you how to enter your design
specifications at the behavioral level and use Behavioral Compiler to
explore implementation alternatives and determine the optimal
architecture. Content is the same as the tutorial on Friday, but
examples are presented in VHDL.
VHDL Synthesis Techniques and Recommendations
This tutorial will present a wide range of VHDL synthesis coding styles
and issues. Caveats based on real-world VHDL synthesis models will be
explored in full detail. Topics will be presented in the following
areas: VHDL synthesis fundamentals, importance of VHDL coding styles,
relying on hardware design experiences, disparities between efficient
simulation models and optimum synthesized hardware, potential
simulation and synthesis mismatches, and VHDL coding style differences
between targeted CMOS and FPGA technologies.
Pins-Out Verification
This tutorial was first offered at EuroSNUG in August. "Pins-out"
verification offers a solution to the problem of ensuring ASICs are
right the first time. As the complexity of ASICs increases, validation
of functionality and the trading off of design parameters becomes more
difficult.
First time right design depends on correct interactions between the
ASIC and surrounding subsystems. Thus, it is important to simulate the
IC in its system context; in other words, pins-out. This tutorial
introduces the pins-out methodology and shows its benefits.
Friday, March 24
New for SNUG '95: Speed Optimization Symposium
This session is intended for experienced synthesis users who are
interested in a comprehensive methodology for speed-based optimization
using Design Compiler. A "Baseline" methodology for speed optimization
will be presented and then a panel of various experts from Synopsys
will discuss their favorite tricks for optimizing high performance
designs. This session is a repeat of the Wednesday session.
New for SNUG '95: Behavioral Synthesis Using Verilog
This session is intended for any synthesis user interested in
behavioral synthesis. Hardware designers are frustrated with lengthy
IC design cycles for increasingly complex, data-intensive algorithmic
applications. This tutorial will show you how to enter your design
specifications at the behavioral level and use Behavioral Compiler to
explore implementation alternatives and determine the optimal
architecture. Content is the same as the tutorial on Wednesday, but
examples are presented in Verilog.
New for SNUG '95: DSP Design Techniques using COSSAP
This session reviews DSP basics and applications. It provides a good
overview of DSP issues and particularly focuses on the COSSAP design
methodology to solve these issues. This session is intended for the
designer who is new to using EDA tools for solving DSP applications.
It is not intended for the designer who is proficient in the use of
COSSAP tools.
NOTE: The tutorial "Practical Design Reuse" has been cancelled.
Advance Registration
Please complete a separate registration form for each attendee.
Specify breakout sessions for Thursday, and your choice(s) of
tutorials.
General Session Registration
Registration includes all materials for the general and breakout
sessions. Due to limited space, breakout session sign-up will be done
on a first-come-first-serve basis. Both cocktail parties , breakfasts
on Thursday and Friday, and the Thursday lunch are included.
Tutorial Session Registration
Registration for each tutorial includes the session and all related
course material. Tutorials are available only to general session
registrants. Space is limited - register early!
Early Registration Drawing!
Register early and you become eligible to win a Macintosh laptop! To
qualify for the drawing and to receive the discount rate, your
registration must be received by February 17, 1995. Conference packets
will be mailed to all early registrants. Registrations received after
February 17 will not be eligible for the drawing or discount rates and
will have their conference packets held at the registration desk for
pick-up.
General session: Early registration - $100.00
Late registration - $150.00
Tutorials (per session): Early registration - $50.00 each
Late registration - $75.00 each
Full payment in U.S. dollars must accompany registration. Company and
personal check, VISA, MasterCard, and American Express cards are
accepted. All checks must be made payable to: Synopsys Users Group.
To Register via the WWW:
* Open URL http://www.synopsys.com/events/snug/snug_reg_form.html
* Fill in the form.
* Click on the "Register" button.
For Credit Card Registration:
* call 1-800-388-9125
* e-mail the information to designinfo@synopsys.com
* fax your completed form to SNUG at 503-690-6906
To Register By Mail:
Detach the form and mail it with your check to:
Synopsys
P.O. Box 310
Beaverton, OR 97075-9962
Cancellations/Refunds
A letter of cancellation must be received 7 days prior to the beginning
of the conference to qualify for a refund.
Travel/Housing
Hotel
SNUG attendees receive a special nightly rate of $105/single,
$115/double, $125/triple, or $135/quad on rooms at the Red Lion Hotel.
Call (408) 453-4000 to make yourself reservations; be sure and identify
yourself as part of the Synopsys Users Group to receive this discounted
rate. All reservations should be made as early as possible, but no
later than March 3, 1995. Reservations received after that date will
be on a space and rate availability only.
Air Travel
Synopsys has negotiated an American Airlines discount for SNUG
attendees. You'll receive 5% off the lowest applicable fare or 10% off
if the ticket is purchased 7 days in advance. A Saturday night
stay-over will increase your savings. When you or your travel agent
makes reservations be sure and give the American Airlines agent the
code STAR NBR 02 35 TA to receive the discount.
Car Rental
Hertz has been appointed the official car rental company for SNUG'95.
Special discount rates, with unlimited mileage, start from $35.99 per
day to a weekly rate of $131.99 for a sub-compact to a $43.99 per day
to a weekly rate of $181.99 for a full-size, 4 door sedan. These rates
are guaranteed from March 15th through March 31st. When making
reservations use the SNUG ID number, CV#14168, and Hertz will
automatically compare the SNUG guaranteed rate to other Hertz published
rates to give you the best comparable rate available. For reservations
call Hertz at (800) 654-2240.
SNUG'95 Registration Form
Name:____________________________________________________
Title:___________________________________________________
Company:_________________________________________________
Mailing Address:_________________________________________
_________________________________________________________
Phone:_____________________FAX:__________________________
e-mail Address:__________________________________________
Credit Card Name:____________Credit Card Number:_________
Exp. Date:_______Name Printed on Card:___________________
Signature:_______________________________________________
____ I prefer vegetarian meals
General Registration - $100
Breakout Session Choices (Select one per session plus alternate):
1st Session: first choice #A___, alternate #A____
A1. Design Compiler
A2. Design Reuse
A3. Design Competition
2nd Session: first choice #B___, alternate #B____
B1. Design Compiler
B2. Test Synthesis
B3. Semiconductor Vendor Sessions
B4. EDA Tool Vendor Sessions
B5. Design Competition
3rd Session: first choice #C___, alternate #C____
C1. Sub-micron Design
C2. Simulation and Verification
C3. Semiconductor Vendor Sessions
C4. EDA Tool Vendor Sessions
C5. Design Competition
Wednesday VHDL Based Tutorial Registration - $50
Tutorial Session Choice (Select one): #W____
W1. Speed Optimization Symposium
W2. Behavioral Synthesis Using VHDL
W3. VHDL Synthesis Techniques and Recommendations
W4. Pins-Out Verification
Friday Verilog Based Tutorial Registration - $50
Tutorial Session Choice (Select one): #F____
F1. Speed Optimization Symposium
F2. Behavioral Synthesis Using Verilog
F3. DSP Design Techniques Using COSSAP
Registration Total: $__________
All technical sessions and presentations are subject to change prior to
conference dates.
More Information:
If you have questions or need more information on SNUG'95, please call
1-800-388-9125.
Article: 726The older "obsolete" Xilinx library had something called phfrcomp, which could be used to build a PLL. I've never tried it, so don't ask me for details. -tomArticle: 727
u8011620@cc.nctu.edu.tw wrote: > Hello, > I would like to know something diffrent among them? I was always cunfused > by them all. > In my previous impression, they are: > PAL: programmable AND, fixed OR > PLD: programmable AND, programmable OR > PLA: ???????????? AND, ???????????? OR > GAL=PLD ?? > Please correct the above, Thanks in advance! PLD = programmable logic device (any architecture) PAL = registered trademark of AMD (by purchase of Monolithic Memories) for their line of PLDs (Programmable Array Logic) GAL = registered trademark of Lattice semiconductor for their line of PLDs (Generic Array Logic) PLA = programmable logic array. I've usually seen this term used in ASIC design, and usually means programmable AND and programmable OR. -- ------- Bryan Butler butler@world.std.comArticle: 728
In article <3i284m$koa@debbie.cc.nctu.edu.tw> u8011620@cc.nctu.edu.tw () writes: >Hello, > >I would like to know something diffrent among them? I was always cunfused >by them all. > >In my previous impression, they are: > >PAL: programmable AND, fixed OR Correct! (PAL = Programmable Array Logic) >PLD: programmable AND, programmable OR PLD is a generic name for two-level (AND-OR) logic devices that *include* PALs, GALs, PLAs. (PLD = Programmable Logic Device) >PLA: ???????????? AND, ???????????? OR PLA: programmable AND, Programmable OR (your definition of PLD). (PLA = Programmable Logic Array) >GAL=PLD ?? GALs are PALs with programmable output functions (you need different PALs for registered or nonregistered outputs for example, but only one type of GAL). GALs where first introduced by Lattice (I think). Also generally GALs are electrically eraseable while PALs are not. (there are exceptions though). > >Please correct the above, Thanks in advance! > > Jason > Hope this helps, Mircea -- Mircea R. Stan | "Without immortality the whole world would UMass, ECE Dept. | be nonsense, all of creation an absurdity." Amherst, MA 01003 | Karl F. GaussArticle: 729
In Article <3i355p$a2m@quidnunc.qcktrn.com> biggs@qcktrn.com ( Tom Biggs ) writes: >The older "obsolete" Xilinx library had something called phfrcomp, which >could be used to build a PLL. I've never tried it, so don't ask me for details. > > > -tom > Absolutely you can. I did one in an Altera MAX 7000 a few years ago. There's no reason it couldn't be done in one of the FPGAs as well. The biggest limitation will be that your operating range and resolution may be limited by the FPGA's maximum clock rate in some applications. PHFRCOMP has been obsolete for a while, in fact I don't believe the latest Xilinx SW (V5.0) even supports it. I personally never used it, so I can't attest to how well it works. No matter though, you can just as easily build your own. As it is, many of the larger Xilinx macros can be done better with a little thought. Rolling your own out of the simpler macros and primitives also gives you a fall back position when the next rev calls your favorite macro obsolete. -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 email randraka@ids.net The Andraka Consulting Group is a digital hardware design firm specializing in obtaining the maximum performance from FPGAs. Services include complete design, development, simulation and integration of these devices and the surrounding circuits. We also evaluate, troubleshoot, and improve existing designs. Please call or write for a brochure.Article: 730
In article <D44sFL.G2t@oasis.icl.co.uk>, trev@ss11.wg.icl.co.uk writes... }cking@accutron.ie writes :- }> 1. The FPGA has 5000 internal gates. }> 2. It can run at 250Mhz internaly } ^^^^^^ }250MHz ! Are you sure about this, sounds like a toggle frequency to me, in which case }would I not expect your design to run at this speed. } }Please correct me if I am wrong and let me know who is making such a device. } }Cheers, }T.H. (trev@wg.icl.co.uk) It wouldn't surprise me at all if such a thing exists. Heck, DEC makes entire CPUs that run at 300MHz (the DECchip 21164). --- CarlArticle: 731
Here's a way to generate fractals with video hardware in real time.
First, create a video feedback loop. Do this by aiming the video camera at
the monitor. The monitor and camera settings are important, try the
following general setup: monitor brightness all the way down, or at least
very low (not completely black, obviously). Zoom the camera in so that the
*image* of the monitor on the monitor is about the same size as the monitor
(in other words, aspect ratio close to 1:1). Also, some rotation is
desirable, else you just get a blob that is hard to stabilize. Hint:
turn the monitor upside down, or put it on its side - this is much easier
than trying to mount a camera upside down on a tripod! Oh yeah, tripods are
good.
At this point you should be able to create lots of swirling, spinning stuff.
Try messing with the color, (B&W is usually easier to start with), phase,
focus, zoom, iris, etc. If the camera and or monitor has automatic features,
turn them all off, you get better control that way.
The patterns that you see can exhibit spatiotemporal oscillation and chaos,
and can be quite hypnotic. But there is usually a single fixed point on
screen (that is either stable or unstable, depending on the zoom). To
get more complicated patterns like fractals, you need to mix in another
transform. The simplest way to do this is with a mirror. The setup
should look like this:
monitor
| video camera
| ___
+-->| >___|---+
| | ----------------- |
| | mirror |
| |
+------------------------------------+
The mirror is positioned so that the camera sees *both* the monitor screen
directly, and a reflected view of it. Now you have two transforms of the
image to play with: the non-linear transform provided by the electronics
of the camera+monitor, and the simple reflection of the mirror. With the
setup above I have been able to create colorful, pulsating, fractal ferns,
and some 'jellyfish' like shapes. Quite different from the usual video
feedback fare, because of the break from circular symmetry. Almost like
life-forms.
Another way to do this (that I have not tried yet) is with a video mixer.
Point two cameras at the screen, mix their output together and display
it on the screen. With different rotation angles and zoom setting it
should be possible to create lots of cool visual effects. Unfortunately,
I do not have access to a video mixer, so I can't try this myself. I
have tried to do it with the poor man's video mixer, a half-silvered
mirror. I've been able to get some interesting patterns, but there
are some serious constraints on this method. (Anybody know how
I can get (or build) a cheap video mixer? Doesn't have to be fancy.)
Video feedback is cool in general, and I encourage anybody with a
camcorder to point it at the monitor screen! (Remember to rotate it,
and zoom in to close to 1:1.) It is a great way to demonstrate
nonlinear, self-organizing pattern formation. I have had people
look at the screen and say "where does the pattern come from?"
This is a great excuse to start telling them all about dissipative
structures, reaction-diffusion systems, etc. etc.. Once I even
got a pattern of spiral waves that looks a little like the BZ
reaction. The WWW page with framegrabbed images is, alas, still
"currently under construction" :-(
Tom Holroyd
Program in Complex Systems and the Brain Sciences The basis of
Florida Atlantic University, Boca Raton, FL 33431 USA stability is
tomh@bambi.ccs.fau.edu instability.
The 9th Amendment of the U.S. Constitution:
"The enumeration in the Constitution, of certain rights, shall not be
construed to deny or disparage others retained by the people."
Article: 732Is there anybody who have written verilog models(behavioral or structural) for Xilinx LCAs or CLBs?Article: 733
carl@gergo.tamu.edu (Carl Perkins) writes :- In article <D44sFL.G2t@oasis.icl.co.uk>, trev@ss11.wg.icl.co.uk writes... >}cking@accutron.ie writes :- >}> 1. The FPGA has 5000 internal gates. >}> 2. It can run at 250Mhz internaly >} ^^^^^^ >}250MHz ! Are you sure about this, sounds like a toggle frequency to me, in which case >}would I not expect your design to run at this speed. >} >}Please correct me if I am wrong and let me know who is making such a device. >} >}Cheers, >}T.H. (trev@wg.icl.co.uk) > >It wouldn't surprise me at all if such a thing exists. Heck, DEC makes entire >CPUs that run at 300MHz (the DECchip 21164). > >--- Carl Not in a FPGA though (yet) . Cheers, T.H. (trev@wg.icl.co.uk)Article: 734
In article <3i0atg$t6l@jabba.ess.harris.com> dlanza@witch.ess.harris.com (David Lanza) writes: >In <3htibu$4vv@barnacle.iol.ie> coffey@iol.ie (Aedan Coffey) writes: > >>M. Movahedin (movahed@tumlis.lis.e-technik.tu-muenchen.de) wrote: >>: Hello, > >>: I have synthecized some combinational designs with 5 input and only 1 output >>: with FPGA Compiler from Synopsys, but they are made with more than one CLB in >>: Xilinx. Definitly, for a 5 to 1 combinational logic, only one CLB (XC4000) is >>: enough. >>: What is happening? >>i >If your using Xilinx PPR tool and the FPGA is no full, the router may partition >the design into multiple CLBs although it could fit into one. Check the >report file for occupied CLBs and packed CLBs. Occupied CLBs are those >containing some logic. Packed CLBs are the number of CLBs that the design >could be sqeezed into. The ppr statistics are badly broken, and I filed a bug report on that -- packed CLBs reported 1 packed CLB for 3 FG generators, for example, had 16 RAM16x1 in it and reported "0 packed CLBs" etc... Basically, under current circumstances you can forget all statistics in prr except the "Occupied CLBs" -- and those are not useful for any comparison, as ppr might just decide to partition CLBs if the chip is not full. I wish there were more serious statistics available, which really listed all the data... Packed CLBs is not of much use either, it's computed as follows: max (FFs, FGs) / 2 Which doesn't really take into account stuff like how to partition the design (there might be constraints preventing 2 FFs and 2 FGs in one CLB, other than routability, I think)... It also ignores H-generators, RAM cells, etc... Your best bet is to check the data from the design compiler and look what it has generated... Check out what goes in each cell and try to find what has happened. I've seen ppr optimize away 100's of gates, so the Synopsys FPGA compiler seems to be less than optimal, but all further tools do not generate reliable statistics... Hope this helps, m. -- Michael Gschwind, Institut f. Technische Informatik, TU Wien snail: Treitlstrasse 3-182-2 || A-1040 Wien || Austria email: mike@vlsivie.tuwien.ac.at PGP key available via www (or email) www : URL:http://www.vlsivie.tuwien.ac.at/mike/mike.html phone: +(43)(1)58801 8156 fax: +(43)(1)586 9697 Boycott Whaling!!! Boycott Norway!!! Boycott Norwegian Products!!!Article: 735
> Re: PLA? PAL? PLD? GAL? Calling Dave Greer or Stan Baker! If you're out there, could you post the letter Dave wrote to EE Times a few years back on naming PALs/GALs/CPLDs/FPGAs. A second suggestion is to try DataIO for a primer. I have a second edition copy of "Programmable Logic - A Basic Guide for the Designer" with a 1986 copyright on it. I don't know if they still print this. Finally, try books. "Digital Systems Design with Programmable Logic" by Martin Bolton is one. There are also plenty of others. You could also try full-line programmable vendors for a primer, but they probably emphasize their own products. --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 736
The following is just one of many trivial questions posted here. In article <3i02ch$d85@msunews.cl.msu.edu> jimenez2@oscar.egr.msu.edu (Manuel Alejandro Jimenez-Cede) writes: >I've been looking for technical info about >fpgas (electrical characteristics, timing, pwr diss., packaging, etc.).Does anybody can suggest me where to find the right databooks? >Or at least a way to get info from manufacturers? > Calling all vendors! *Please* post contact information for these people! 800#s, literature request lines, application support numbers, web URLs, list server info, BBs, etc. Step 2 - Can someone collect these on a web site? --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 737
cking@accutron.ie writes (heavily trimmed!):
... <lotsa snipping>
>However, I was wondering if it is possable to use the FPGA to
>generate a fractal image, in *real time*, to display via the
>RAMDAC. I know that such a task is maths intensive, but:
> 1. The FPGA has 5000 internal gates.
> 2. It can run at 250Mhz internaly
^^^^^^
| Stop right there!
A. In order to run at 250 MHz in CMOS, interconnect needs to be
*very* short (no capacitance allowed!). In custom CMOS (e.g. DEC
Alpha, Gennum GenLinx) this is possible with lots of effort. In FPGAs,
this is very, very unrealistic (today).
B. You may very well be able to handcraft small data paths to run
at (maybe) up to 100 MHz. Maybe. But you won't be able to build
big data paths at that cycle rate because of the power required to
run at those rates. FPGA vendors guarantee their AC specs to either
70 or 85 deg junction temp. At 100 MHz, with available packaging, you
will probably hit 85 deg junction at less than 1K gates, given typical
operating environments, design practices, packaging, etc. CMOS slows
down as it warms up. If you want 250 MHz, you're talking custom
layout and/or exotic packaging and cooling.
Almost all the FPGA packages currently offered are cavity-up
configurations, so even heat sinks won't help you. If you have the
time/money to buy dice and do custom packaging, then you'll want to
do custom layout as well. This isn't trivial, even at 0.5u geometries.
But it *is doable*, and it is being done. This just isn't a casual
problem that can tolerate off-the-shelf design components.
If you want to pursue custom CMOS, drop me a line. I know a couple
of designers that can pull it off (250MHz) reliably.
Bob Elkind, Tek TV Products (FPGA and CMOS/Bipolar ASIC designer)
bobe@tv.tv.tek.com
Article: 738In article <D46A3J.80H@world.std.com> butler@world.std.com (Bryan Butler) writes: >u8011620@cc.nctu.edu.tw wrote: >> Hello, > >> I would like to know something diffrent among them? I was always cunfused >> by them all. > >> In my previous impression, they are: > >> PAL: programmable AND, fixed OR >> PLD: programmable AND, programmable OR >> PLA: ???????????? AND, ???????????? OR >> GAL=PLD ?? > >> Please correct the above, Thanks in advance! > >PLD = programmable logic device (any architecture) >PAL = registered trademark of AMD (by purchase of Monolithic Memories) >for their line of PLDs (Programmable Array Logic) >GAL = registered trademark of Lattice semiconductor for their line >of PLDs (Generic Array Logic) >PLA = programmable logic array. I've usually seen this term used in >ASIC design, and usually means programmable AND and programmable OR. > That's what I've thought, but in his book FPGA Workout, 1994, David E. Van den Bout, Ph.D. writes (and I paraphrase): PLA: Developed first and consist of programmable AND and OR arrays. PAL: Developed next and consist of programmable AND and fixed OR arrays. PLD: A PAL with flip-flops added. CPLD: Complex PLD (several PLDs combined into a single IC). He does not acknowledge PAL as being a registered trademark of AMD. Also, he does not mention GALs.Article: 739
In article <3iaqd0$nuh@noao.edu>, Bill Hull <bhull@sunspot.noao.edu> wrote: >In article <D46A3J.80H@world.std.com> butler@world.std.com (Bryan Butler) writes: >>u8011620@cc.nctu.edu.tw wrote: >>> Hello, >> >>> I would like to know something diffrent among them? I was always cunfused >>> by them all. >> >>> In my previous impression, they are: >> >>> PAL: programmable AND, fixed OR >>> PLD: programmable AND, programmable OR >>> PLA: ???????????? AND, ???????????? OR >>> GAL=PLD ?? >> >>> Please correct the above, Thanks in advance! >> >>PLD = programmable logic device (any architecture) >>PAL = registered trademark of AMD (by purchase of Monolithic Memories) >>for their line of PLDs (Programmable Array Logic) >>GAL = registered trademark of Lattice semiconductor for their line >>of PLDs (Generic Array Logic) >>PLA = programmable logic array. I've usually seen this term used in >>ASIC design, and usually means programmable AND and programmable OR. >> > >That's what I've thought, but in his book FPGA Workout, 1994, David E. >Van den Bout, Ph.D. writes (and I paraphrase): > >PLA: Developed first and consist of programmable AND and OR arrays. >PAL: Developed next and consist of programmable AND and fixed OR arrays. >PLD: A PAL with flip-flops added. >CPLD: Complex PLD (several PLDs combined into a single IC). > >He does not acknowledge PAL as being a registered trademark of AMD. >Also, he does not mention GALs. > Well, sure enough PAL is a registered trademark of AMD as can be seen by the trademark they put by it on all their databooks. I have most often seen it used when refering to PLAs with fixed OR connections. Then the term PLD became more prevalent when PAL macrocells were pumped up with flip-flops and extra doo-dads for inverting SOP terms, handling the flip-flop control lines and clocking, and all types of feedback. As for GALs, I've never used them and I thought it was a marketing name for a particular brand of PLD (which looks to be the case). -- || Dave Van den Bout || || Xess Corporation ||Article: 740
XESS Corp. has just released the first chapter of "FPGA Workout II". This chapter covers the EPX780 FPGA architecture and timing. It's a hypertext document that will execute on a DOS machine with a VGA display. If interested, you can retrieve this file via anonymous FTP from ftp.vnet.net in directory pub/xess/hyperdoc. Get the files epxdata.exe and install.txt. -- || Dave Van den Bout || || Xess Corporation ||Article: 741
ATT and Xilinx recently announced (independently) that each company guarantees their AC specifications to 85 degrees C junction temp. Given that a typical 208-pin plastic quad flatpack has a thermal resistance of >30 degrees C per watt in still air, and that a typical ambient air temp for commercial grade applications is 55-70 degrees C, an FPGA design would be limited to 0.5 - 1 watt or less of power before the vendor's AC specs would have to be degraded. Is this interesting to anyone out there? Has anyone found their applications to be constrained to XX number of gates simply because they were running into power (heat) limits? Note that ATT and Xilinx databooks have historically been published with only "ambient" temperature limits at which their AC specs were guaranteed (70 degrees ambient in each of these cases), even though the fundamental limit was junction temperature. It was left to the designers to more or less guess how much heat they could push through a particular package before they reached some unspecified thermal bound at which the AC characteristics would put their design at risk. Both ATT and Xilinx are to be commended for (finally) stating their performance characteristics in unambiguous terms. Does anyone have equivalent commitments from other FPGA vendors? For what its worth, I believe that ATT has always guaranteed their devices to 85 deg junction (they just didn't put it in writing in the data sheet, for some inexplicable reason). I believe Xilinx had (until this announcement) guaranteed their devices to 70 degrees junction, and so the parts tested under the new spec will now be around 5% faster than they had been, a "free" performance enhancement/upgrade. Anyone from ATT, Xilinx, Altera, Motorola, Actel, etc. etc. care to comment? A few weeks ago I posted a questionnaire for FPGA designers concerned about thermal properties, etc. I got absolutely *zero* responses. Am I the only FPGA designer in the world running into power/thermal limits (as opposed to gate count or pin count)? If this is the case, then it will be very difficult for me to arouse interest from FPGA vendors in solving my petty little problems. If I'm *not* the only "high-power" designer out there in the not-so-cold-cold world, then I believe it is in our mutual best interest to share ideas, info about managing power and heat in these little critters while still getting some decent speed out of them, hopefully at a reasonable cost. When's the last time you asked your FPGA vendor for a power estimation tool? Bob Elkind, Tektronix TV Products bobe@tv.tv.tek.comArticle: 742
Has anyone used Cadence FPGA Designer? I read the EE Times article and have general information. User comments would be helpful. Comparisons with Synopsys and/or Exemplar would be interesting. --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 743
>>PLD = programmable logic device (any architecture)
>
>That's what I've thought, but in his book FPGA Workout, 1994, David E.
>Van den Bout, Ph.D. writes (and I paraphrase):
>
>PLD: A PAL with flip-flops added.
It should be noted that the terminology/taxonomy is not completely
agreed upon between everybody. Here at UofT (and elsewhere), we
are defining the term as follows:
PLD = programmable logic device -- includes CPLDs, FPGAs, but not
ROM or RAM, can be one-time or reprogrammable.
The general impression is that PLD shall be an umbrella term to
categorize all types of user-programmable logic. CPLD, FPGA, PAL,
PLA, GAL are all types of PLDs.
Guy Lemieux
University of Toronto
Article: 744In <1995Feb21.210949.27248@jarvis.cs.toronto.edu> lemieux@eecg.toronto.edu (Guy Gerard Lemieux) writes: > >>>PLD = programmable logic device (any architecture) >> >>That's what I've thought, but in his book FPGA Workout, 1994, David E. >>Van den Bout, Ph.D. writes (and I paraphrase): >> >>PLD: A PAL with flip-flops added. > >It should be noted that the terminology/taxonomy is not completely >agreed upon between everybody. Here at UofT (and elsewhere), we >are defining the term as follows: > >PLD = programmable logic device -- includes CPLDs, FPGAs, but not > ROM or RAM, can be one-time or reprogrammable. > >The general impression is that PLD shall be an umbrella term to >categorize all types of user-programmable logic. CPLD, FPGA, PAL, >PLA, GAL are all types of PLDs. > >Guy Lemieux >University of Toronto > The 'commercial' programmable lgic industry also has problems with these definitions. The difference between FPGAs and PLDs/CPLDs is most often mis-represented. PLDs and CPLDs have FIXED routing resources and very (?) predictable timings accordingly. In an FPGA the delay is less predictable (whilst in most cases it can be accurately 'estimated' by static timing analysis tools) as it is a function of the route a net takes through the array. Post-Layout timing in an FPGA will be different than Pre-Layout and because of this, FPGAs have much more in common with ASICs than PLDs from an end user design perspective (both logic and metodology). To classify PLDs and FPGAs together, in anything other than the broadest sense of 'programable' logic, is demeaning to the added flexability that FPGAs offer the designer. Many PLD/CPLD vendors (mis-)market their products as FPGAs to appear to be in both markets (and to raise their ASP) - buyer beware!! Martin MasonArticle: 745
In article <3id386$hfb@elvis.vnet.net> devb@elvis.vnet.net (David Van den Bout) writes: >Well, sure enough PAL is a registered trademark of AMD as can be seen >by the trademark they put by it on all their databooks. I have most As someone else mentioned, MMI invented PALs and trademarked the name. This became AMD's property when they bought MMI. I was there at the time, in the sense of being an AMD employee. >often seen it used when refering to PLAs with fixed OR connections. >Then the term PLD became more prevalent when PAL macrocells were pumped >up with flip-flops and extra doo-dads for inverting SOP terms, handling >the flip-flop control lines and clocking, and all types of feedback. >As for GALs, I've never used them and I thought it was a marketing name >for a particular brand of PLD (which looks to be the case). GAL refers to Lattice's idea for Generic Array Logic. The original PALs were 16R8/16R6/16R4/16L8. Lattice came up with the idea for a single part, 16V8, which not only could replace any of these 4, but could do so with the original fuse map plus a few extra configuration bits. These bits were so easy to calculate that most programmers can do it for you. This allowed the use of GALs even with "legacy" JEDEC files where the source is unavailable. At the same time Lattice introduced another good idea, electrically erasable parts. Some people actually think that GAL means EE, but these are two orthogonal concepts. GAL is an architecture, EE is a device technology. You could have non-EE GALs (although I have never seen any) and EE PALs (AMD has EE 22V10s, as do many others). -- Question Authority, but never shoot back.Article: 746
****************************************************************************** * David L. Carroll Director of Communications * * International Telecommunications Center (ITC) "The only server on the * * Internet dedicated exclusively to telecommunications" * * PHONE:914-353-0311 FAX:914-353-0335 E-mail:dlc@telematrix.com * ****************************************************************************** February 23, 1995 Dear Sirs: This is to inform you that International Telecom Center (ITC), a storefront server devoted exclusively to telecommunications, datacommunications, networking and computer communications has set up a jobs and positions wanted bulletin board. For the next two weeks, starting February 23th, persons searching jobs (and companies seeking to fill positions) are invited to enter their listings on this board free of cost Access ITC at http://www.telematrix.com, then click on the Information Center icon Employment Agency and fill out the form as directed. ITC's server is currently looked at by between 30,000 to 40,000 telecom/datacom/computer professionals every month; more than half these visitors are from Fortune 500 companies. This is, in other words, an excellent opportunity to showcase your stuff for free of cost. But do it soon cause this opportunity ends soon. Good hunting, David Carroll Director of Communications, ITCArticle: 747
Can anyone please tell me if there is a newsgroup available which is dedicated to the topics of micro controllers in general and Motorola's MC683xx family in particular? Many thanks for your help. RolandArticle: 748
Phil Ngai (pngai@mv.us.adobe.com) wrote: > In article <3id386$hfb@elvis.vnet.net> devb@elvis.vnet.net (David Van den Bout) writes: > >Well, sure enough PAL is a registered trademark of AMD as can be seen > >by the trademark they put by it on all their databooks. I have most > As someone else mentioned, MMI invented PALs and trademarked the name. > This became AMD's property when they bought MMI. I was there at the > time, in the sense of being an AMD employee. > >often seen it used when refering to PLAs with fixed OR connections. > >Then the term PLD became more prevalent when PAL macrocells were pumped > >up with flip-flops and extra doo-dads for inverting SOP terms, handling > >the flip-flop control lines and clocking, and all types of feedback. > >As for GALs, I've never used them and I thought it was a marketing name > >for a particular brand of PLD (which looks to be the case). > GAL refers to Lattice's idea for Generic Array Logic. The original PALs > were 16R8/16R6/16R4/16L8. Lattice came up with the idea for a single > part, 16V8, which not only could replace any of these 4, but could do > so with the original fuse map plus a few extra configuration bits. > These bits were so easy to calculate that most programmers can do it > for you. This allowed the use of GALs even with "legacy" JEDEC files > where the source is unavailable. > At the same time Lattice introduced another good idea, electrically > erasable parts. Some people actually think that GAL means EE, but these > are two orthogonal concepts. GAL is an architecture, EE is a device > technology. You could have non-EE GALs (although I have never seen any) Some of the first 22V10s I used from Lattice and VTI were non-eraseable. > and EE PALs (AMD has EE 22V10s, as do many others). > -- > Question Authority, but never shoot back. -- ------- Bryan Butler butler@world.std.comArticle: 749
Tom Holroyd (tomh@bambi.ccs.fau.edu) wrote: : Here's a way to generate fractals with video hardware in real time. : First, create a video feedback loop. Do this by aiming the video camera at : the monitor. The monitor and camera settings are important, try the : following general setup: monitor brightness all the way down, or at least : very low (not completely black, obviously). Zoom the camera in so that the : *image* of the monitor on the monitor is about the same size as the monitor : (in other words, aspect ratio close to 1:1). Also, some rotation is : desirable, else you just get a blob that is hard to stabilize. Hint: : turn the monitor upside down, or put it on its side - this is much easier : than trying to mount a camera upside down on a tripod! Oh yeah, tripods are : good. This is also described at the beginning of Peitgen, Jurgens and Saupe's ``Chaos and Fractals: New Frontiers of Science'' (Springer-Verlag, 1992). : Another way to do this (that I have not tried yet) is with a video mixer. : Point two cameras at the screen, mix their output together and display : it on the screen. With different rotation angles and zoom setting it : should be possible to create lots of cool visual effects. With a single monitor, several cameras and a mixer you should be able to produce the attractor of an iterated function system of similtudes. With several monitors, several cameras and a mixer you get the attractor of a recurrent iterated function system of similtudes. -John Hart --- John C. Hart, Asst. Prof. School of EECS, Wash. St. Univ. Pullman, WA 99164-2752 (509)335-2343 fax:(509)335-3818
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