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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
By popular demand (2 people), I am releasing a new version of my
xilinx utilities. I have placed them at an anonymous FTP site:
esesrv0.fnal.gov /pub/xilinx/awks.zip
The most useful tool is the XFUNC utility which allows you to place
PAL-like logic equations and ROM tables directly on a Viewlogic
schematic. This has been updated to work directly on .wir files so it
can work with NeoCad software and Xilinx software, and, presumably, can
be used with ViewSim. See the more detailed description below.
Other tools include:
xdis Disassmble X4000 LCA files into logic equations
pinout Print X3000 or X4000 Pin Grid Array diagram and pinlist
global Fix XNF files to allow global signals and buses
fanout Print list of signal dependancies
blk Print map of X4000 CLB outputs
long Print map of X4000 Long line usage
Send me Email if you use these utilities and want to be kept informed
of bugs and updates.
========= XFUNC.MAN Help file ==================================
xfunc.awk (xfunc.exe):
Add extended functions to workview schematic files.
This allows you to add function generators (FUNCS), ROMs, and map
attributes to a workview schematic. These can be added either as
schematic symbols or as unattached attributes. The XFUNC program works by
post-processing .wir files and converting FUNC, ROM, and MAP attributes
into symbols that are recognized by WIR2XNF (or other WIR processors).
Xfunc should be run after a schematic change and before WIR2XNF or XMAKE.
It can be added to an XMAKE makefile.
Usage:
Xfunc [-d <wir>] <files> [-all]
<files> A list of files to be processed. Wildcards can be used. If
no file type is specified, then .1 is used.
-all Process all .wir files in the directory.
-d <wir> Specify a directory to find .wir files. Default is .\wir.
Examples:
Xfunc tester.* ! Do all sheets of .\wir\tester
Xfunc -all ! Do all files in .\wir
Xfunc -d \wv\usrlib\wir -all ! Do all files in usrlib
FUNCs: UFUNC, FFUNC, HFUNC
FUNCs are Workview schematic symbols or attibutes that allow
functionality to specified in terms of equations rather than gates. The
FFUNC and HFUNC parts are similar to the X4000 FMAP and HMAP parts: they
specify the contents of a single CLB function generator. The UFUNC is an
unconstrained function generator that can be used in X4000 or X3000
schematics. When used as an attribute, it takes the form:
UFUNC <name>=<equation>
or
UFUNC <name>(<clk>,<cke>,<clr>)=<equation>
<name> is an output signal name and must be a valid viewdraw net name.
<equation> is a logic equation that uses other viewdraw nets.
The second form allows a flip-flop to be added to the output. The <clk>,
<cke>, and <clr> fields are names of nets to be connected to the flip-flop
control signals. If <cke> or <clr> are left blank, they are un-connected.
If <clk> is left blank, it defaults to the name "CLK".
Examples:
UFUNC PARITY=DB0@DB1@DB2@DB3 ! generate 4 bits of XOR parity
UFUNC STATE4(CLK,,RESET)=STATE3*DRDY ! a flip-flop output
UFUNC STATE5()=STATE4*MRDY ! also a FF output with default CLK.
FFUNC ACK=STATE4*/STATE5 ! Ouput mapped with X4000 FMAP.
SYMBOL VERSION:
When used as a schematic symbol, a FUNC looks like this:
_
F= _|-- Basic symbol.
_
F=EN*(SEL*A+/SEL*B) _|-- Symbol with function specified
The part has only one pin - the output pin. Input signals are implied
in the equation and are attached automatically to existing nets with the
same names. The function text is specified as an attribute. It is
entered by selecting the part and executing the Workview CA command. The
text must not contain any spaces. A flip-flop can be added by attaching
a clock attribute (K=), enable attribute (CE=), or clear attribute (RD=).
The FUNC symbol has one advantage over the FUNC attribute: it can accept
other attributes. In particular, it can take a label, BLKNAME, or LOC
attribute.
OPERATORS:
FUNCs can use the following operators in order of increasing precedence:
a?b:c select (translates to a*b+/a*c)
a+b or
a@b xor
a*b and
/a invert
() grouping.
ROMS:
A ROM allows functionality to be specified in terms of vectors. It's
similar to the standard xilinx ROM parts, except that it works on X3000 as
well as X4000, and the inputs are not constrained by function generators.
As with FUNCs, a ROM can be specified as an attribute or a symbol.
As an attribute, the ROM takes the form:
GROM <output>,<inputs>=<vector>
<output> is the output net name.
<inputs> is a list of inputs (address bits) separated by commas.
The list can be a bus of the form A[n:m]. The inputs are
specified from most-significant to least-significant.
<vector> is a hex number that specifies the bit pattern for the rom.
The most significant digit maps to higher addresses as per the
Xilinx ROM part.
As a symbol, the ROM is a 2-pin device. The output pin is a single net.
The input pin is a bus. The vector is specified as an attribute (F=).
The symbol must have a name that starts with the letters GROM.
Examples:
GROM THREE,I[2:0]=08 ! THREE=/I2*I1*I0
GROM SEG0,B3,B2,B1,B0=c7ed ! Top segment on 7-seg display.
MAPs:
MAPs are the same as xilinx standard FMAP,HMAP,and CLBMAPs, except that
they can be specified as unattached attributes. They take the form:
FMAP <output>=<in1>,<in2>,<in3>,<in4>,<Attr>=<value>...
HMAP <output>=<in1>,<in2>,<in3>,<Attr>=<value>...
CLBMAP x,y=a,b,c,d,e,f,k,ec,rd,di,<Attr>=<value>...
NOTES:
1) This is compatible with earlier versions of FUNC that were implemented
as XNF-file processors. FUNCs can now be included in any level of the
heirarchy without requiring them to be viewdraw "Modules". Nets no longer
have to be explicitly drawn - they can exist only as names in a function.
2) The FFUNC part allows a maximum of 4 unique signal names in the
function. If there are more, FUNC.AWK will print a warning message, but
will not declare a fatal error. HFUNC allows a maximum of three unique
names. Usually, two of the inputs to an HFUNC should be from FFUNCs.
4) Reliablility: I have used earlier versions of FFUNC and HFUNC
extensively in several X3000 and X4000 designs. I have ported one of the
X3000 designs to this new version. Basic functionality has been tested
with small test designs.
5) Future plans: I plan to add an optimizer to the GROM parts and extend
the vector format to include "don't care" and binary vectors.
FILES:
xfunc.awk Awk source code.
xfunc.exe Executable
xfunc3k.inc Include files. Copy 3k or 4k version to the design
xfunc4k.inc directory depending on which part you are using.
xfuncneo.inc
xfunc.man This help file
.\wir\*.1i Temporory file used to process wir file.
Article: 751
Roland Welte <100070.3321@CompuServe.COM> writes:
>Can anyone please tell me if there is a newsgroup
>available which is dedicated to the topics of
>micro controllers in general and Motorola's MC683xx
>family in particular?
>Many thanks for your help.
>Roland
try comp.realtime and watch for comp.embedded (the CFV just went out)
jwes@bix.com
Article: 752In article <D4EvC1.M0J@world.std.com> butler@world.std.com (Bryan Butler) writes: >Some of the first 22V10s I used from Lattice and VTI were non-eraseable. Yes, Lattice's marketing department seems to have managed to destroy all meaning for the term GAL. Originally it meant a part that could emulate another part, as illustrated by the table of emulated parts in the 16V8 and 20V8 data sheets. Now it just means another small programmable logic device sold by Lattice. I don't believe there is any difference to the user between a Lattice GAL22V10 and an AMD PALCE22V10. -- Question Authority, but never shoot back.Article: 753
I have a slight problem with the results I am getting when I synthesize a 16x8 VHDL multiplier in Synopsys. It appears that the multiplier and the control logic I need for it should be able to exist happily on a single Xilinx 4010, but I run out of routing resources very quickly. To see if this was a lost cause, I hand placed and routed the multiplier in XDE. The multiplier is very regular and routable; the rest of my logic should be able to fit on the 4010 with it. However, I do not want to do the rest of my logic in XDE or even schematic capture if at all possible. I really want to replace the Synopsys multiplier with mine -- something akin to what Synopsys does with xblox (my own RPM). PPR should then be able to successfully place and route my remaining logic (provided the regular pattern of my multiplier is preserved). I have tried LCA2XNF and then converting the resultant XNF to a Synopsys db file which I then use as a link library. Synopsys complains of no input ports, XNFPREP deletes signals that I think are connected and I end up with useless files. I apologize if this has been covered before or if this is the incorrect group, but I am a casual reader here. Thanks for any help. I have been beating this dead horse for a few weeks now and any suggestions are welcome. -- Cameron McNairy cameron@byu.eduArticle: 754
randraka@ids.net wrote:
: In Article <3i355p$a2m@quidnunc.qcktrn.com>
: biggs@qcktrn.com ( Tom Biggs ) writes:
: >The older "obsolete" Xilinx library had something called phfrcomp, which
: >could be used to build a PLL. I've never tried it, so don't ask me for details.
: >
: Absolutely you can. I did one in an Altera MAX 7000 a few years ago.
: There's no reason it couldn't be done in one of the FPGAs as well. The biggest
: limitation will be that your operating range and resolution may be limited by
: the FPGA's maximum clock rate in some applications.
:
: PHFRCOMP has been obsolete for a while, in fact I don't believe the latest
: Xilinx SW (V5.0) even supports it. I personally never used it, so I can't
: attest to how well it works. No matter though, you can just as easily
: build your own. As it is, many of the larger Xilinx macros can be done better
: with a little thought. Rolling your own out of the simpler macros and
: primitives also gives you a fall back position when the next rev calls your
: favorite macro obsolete.
Me again. The guy who asked the original question. If I understand
correctly, this PHFRCOMP used to implement the phase detector portion of
a phase locked loop. Presumably, it then relied on an external voltage
controlled oscillator in order to generate a clock in sync with the clock
recovered from the Manchester encoded bit stream. I have now an
application note that seems to describe something similar to PHFRCOMP
fairly well.
I understand that the combinatorial delays (especially the 6ns ones in
the slower part that I'm using) will lead to some tradeoffs in accuracy.
However, I really don't think that maximum clock rate should be a problem,
even with the -6 grade part. My operating freqency is only 5MHz.
If my understanding is correct, is there a specific VCO chip that anyone
would recommend? If I'm completely off-base, and you're talking about
some way to implement the entire loop within an FPGA, please let me know.
Regards,
Jeff
--
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Jeff Collins jwcollin@engr.ucdavis.edu
Intelligent Manufacturing Systems/ collinsj@ece.ucdavis.edu
Mechatronics Lab, 1065 Bainer Hall collinsj@cs.ucdavis.edu
University of California, Davis jwcollins@ucdavis.edu
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Article: 755These tools have been tested using XACT 5.0. The read.me file that states otherwise was an old file.Article: 756
In article <3ifq0h$9ep$1@mhade.production.compuserve.com> Roland Welte <100070.3321@CompuServe.COM> writes: > Can anyone please tell me if there is a newsgroup > available which is dedicated to the topics of > micro controllers in general and Motorola's MC683xx > family in particular? > Try comp.sys.m68k for the Motorola stuff Dave -- djh@sectel.com Tel +44 1285 655 766 Fax +44 1285 655 595Article: 757
In article <3ifq0h$9ep$1@mhade.production.compuserve.com> Roland Welte <100070.3321@CompuServe.COM> writes: > Can anyone please tell me if there is a newsgroup > available which is dedicated to the topics of > micro controllers in general The comp.robotics group has discussions on micro-controllers. I lurk there to get exposed to other topics not in my personal field of expertise like servos, steppers, ultrasound, imaging and ranging... Doug Shade rxjf20@email.sps.mot.comArticle: 758
In article <3ihku7$asj@mark.ucdavis.edu>, jwcollin@chorizo.engr.ucdavis.edu (Jeff Collins) writes: |> I understand that the combinatorial delays (especially the 6ns ones in |> the slower part that I'm using) will lead to some tradeoffs in accuracy. |> However, I really don't think that maximum clock rate should be a problem, |> even with the -6 grade part. My operating freqency is only 5MHz. |> |> If my understanding is correct, is there a specific VCO chip that anyone |> would recommend? If I'm completely off-base, and you're talking about |> some way to implement the entire loop within an FPGA, please let me know. Most designers I know are willing to work pretty hard to avoid analog things like VCOs. Have you checked out Digital PLLs? (Sorry, I don't have a good reference.) After you get the hang of it they are pretty simple. The basic idea is to build a small/fast state machine to wait a while and then look for the next transition. When it finds the transition, it emits the data bit and a valid signal, and restarts the scan. If your state machine is running at nX the bit rate, you expect to see the transition after n clocks. n-1 and n+1 are also reasonable. They just mean that your clock has drifted a tick relative to the transmitting clock. 5 MHz is 200 ns. You want to sample at 10X or 16X. That's 20 or 12.5 ns. You can also process 2 samples in parallel: 40 or 25 ns. If you don't like cramming that into a corner of your FPGA, consider using a PAL. (Think of it as trading the VCO for a PAL.) The details probably depend upon what clocks you have available. You can probably work out the state machines by spending an evening with graph paper and pencil. Note that just parsing the received data stream is only half of the problem. You also have to do something with it, like collect it into bytes and pass it on to some other digital logic. That requires clocking and/or synchronizers. You might, for example, modify the state machine to generate the clock that drives the next stage of the system rather than a valid bit. That means the downstream logic might see shorter than average clock pulses... But it is all digital so once you understand what is going on it is possible to check all the setup/hold times and be pretty sure your design will work.Article: 759
I recenty bought the ispLSI starter kit from Lattice for the ispLSI1016, ispGal22V10 and ispGDS14. Is there anyone out there who played with the kit before and can give me an evaluation. Is the soft bugfree etc... In the kit there is a nice software to program the ispLSI1016, but not the Gal there is only a loader for JEDEC files. Doe anyone know if there exist a simple compiler on the net that can create this JEDEC files ? Does Lattice have an FTP site with updates of the soft, example programs etc.. Any help is welcome. LucArticle: 760
Carl Perkins (carl@gergo.tamu.edu) wrote: : In article <D44sFL.G2t@oasis.icl.co.uk>, trev@ss11.wg.icl.co.uk writes... : }cking@accutron.ie writes :- : }> 1. The FPGA has 5000 internal gates. : }> 2. It can run at 250Mhz internaly : } ^^^^^^ : }250MHz ! Are you sure about this, sounds like a toggle frequency to me, in which case : }would I not expect your design to run at this speed. : } : }Please correct me if I am wrong and let me know who is making such a device. : } : }Cheers, : }T.H. (trev@wg.icl.co.uk) : It wouldn't surprise me at all if such a thing exists. Heck, DEC makes entire : CPUs that run at 300MHz (the DECchip 21164). Xilinx boasts about a PLL circuit that they implemented in one of their faster chips that could run at 320 MHz. I'm not sure wether this was a practially usefull configuration, but it seems as if quite high internal PLL rates can be achieved. Xilinx did take care to say that they didn't imply that a whole circuit could run at 300+ MHz, and that this was only the frequency of the PLL. Roger. -- * The Dutch taxdepartment announces: We will pay people back much more * * quickly. Starting in 1997 we will start transferring the funds back * * to the people around July instead of the current date in November. * EMail: R.E.Wolff@et.tudelft.nl ** Tel +31-15-783643 or +31-15-137459 ** <a href="http://einstein.et.tudelft.nl/~wolff/"> my own homepage </a> **Article: 761
This file contains a summary of information recieved from the posting
'Real-time fractal generation in h/w' up to Wed 22 Feb 1995.
Thanks for all contributions.
Original message:
> I'm currently working on the design of a video RAMDAC
>evaluation/demonstration board, and would like some comments
>and/or help on an idea I have. The board is like this:
> --------------------------------
> | VRAMr |
> PC | _____ |-
>PARALLEL O ------ V |RAM| | -> RGB/sync out
>INTERFACE O |FPGA| R |DAC| |-
> ---> O ------ A ----- |
> | XT M |
> | AL b VRAMg |
> |______________________________|
>
>The FPGA can be programed via the pc printer port.
>The RAMDAC is a fast part (220MHz), so there have to be two
>ways to display an image,
>1. A true color image downloaded to the VRAMS
> (works up to 30MHz dot clock officaly, but will work
> to 50-60MHz (most of the time) if the supply voltage is
> changed slightly),
>2. For the fast pixel rates, via pattern generation on the FPGA.
> (grids, rams cross hatch etc.)
>The FPGA also handles the SYNC generation, and the control interface
>to the RAMDAC.
>
>However, I was wondering if it is possable to use the FPGA to
>generate a fractal image, in *real time*, to display via the
>RAMDAC. I know that such a task is maths intensive, but:
> 1. The FPGA has 5000 internal gates.
> 2. It can run at 250Mhz internaly
> 3. A low resolution image will do (say 160x100).
> 4. A low limit on zooming into the fractal will do.
> 5. A lowish video frame rate will do (<50Hz)
>That gives about 160x100x50=800K pixels/sec to calculate.
> =~300 clock cycles per pixel
>Can a point on the Mandel set (or any other fractal)
>be calculated in such a time (in hardware)?
>
>I would like to be able to pan and zoom the image, via the
>parallel interface, but that should be trivial once the
>calculation routine works.
>
>So if any good Fractal experts/ALU designers/FPGA experts
>find this idea interesting and/or have any ideas,
>please *email* me at the address below, since
>my NEWS access is slow, so I may not be able to read all
>the messages in all the groups that this was posted to.
>If there is interest in the topic, I will sumarise and
>email/post the results to interested parties/newsgroups.
Some Additional information for the curious:
The FPGA is an Atmel AT6005-QC
The RAMDAC is an Analog Devices ADV7162
The FPGA has 108 i/o pins and 3136 cells.
It is SRAM based, and can be configured any number of times.
Partial-reconfiguration is possible while the part is operating.
The 250MHz is the FF toggle rate.
Counters/registers operate around 30-70MHz.
System i/o speed is 70MHz.
Development Software:
ProSym, IDS 2.10b from Atmel, Figaro for auto place and route.
Atmel can be contacted at fpga@atmel.com
The 'VRAMs' are not realy 'random access', but a form of buffer. They have no
external address bus, only a read and write reset, and a read and write clock,
which resets and bumps the internal address busses. This keeps the pin count
down. To save on board routing space/FPGA i/o pins, we also have tied the read
and write data lines together. Therefore, the 'VRAMS' cant be used for any
temp/image storage for the fractal generation.
The work fine as they were intended, ie disable output, reset write, squirt
down the picture, enable output. Then, hit reset read every vertical retrace.
The fractal has to be calculated from only the *current* X&Y coords, so plasma
stuff is probably out.
Also note that the Fractal stuff is only an aside to the project. It is not in
the project specification, just something cool to add on if time constraints
allow.
Accutron Ltd. is an independent product research, design & development company.
We mainly work in the areas of:
* Embedded controler systems, including standalone systems
and networked systems controled/monitored by a PC.
* Data collection systems, stock tracking systems,
including portable intelegent barcode readers.
* Product Prototype/Evaluation/Demonstration systems/Boards.
* Industrial process monitoring and control systems.
* We do a lot of 'one offs' for specialist applications.
Contact: info@accutron.ie
My role is mainly the software/computer engineering for the products that
require a PC as the 'master' in the system, however I do have a electronics
background, and tend to get more than the occasional bit of hardware stuff
thrown at me every now and again. :-|
This is the first time I've had to use FPGAs.
Now the Replys:
========================================================================
From: rich@sunnyvale.dyna.com
Date: Mon, 13 Feb 95 18:14:12 cst
Hi Ciaran.
My name is Rich Hauser and I work for a small high-speed FPGA start-up.
I found your target application intriguing and I would be most
interested in being copied on any response(s) you acquire from your
posting (below). At this time, our test chip has worked, but we are
several months away from full working silicon. However, the first part
is targeted as a 5K/200MHz part which seems to match your application.
I'm thinking that this could be a fun 'app note' to demonstrate the
speed and capability of our part. Of course, if you happen to develop a
market out there, then that might be something for us to support in the
future, too. :)
Anyway, I'm sure you'll have your 'answer' before too long and I would
appreciate it -- if possible -- if you might let me know what you learn.
Thanks.
-Rich
Dyna Logic Corporation
1255 Oakmead Parkway, Sunnyvale, CA 94086-4028
Tel: 408/481-3144 Fax: 408/481-3136 Internet: rich@dyna.com
====================================================================
From: Steve Casselman <sc@vcc.com>
I have a mandelbrot generator that takes about 5000 gates
(50% OF A 4010). You have to be able to fit 3 multipliers
and a handful of adders and a state machine to do the job.
Also, in your calculations, you need to deside the maximum
number of iterations at any one point, I do 256. I use a
24-bit booth multiplier that takes 14 clocks to do a multiply.
So with this multiplier it takes around 25 clocks to do an
iteration. 300/25 = 12 this is not very good but should show
you the outline. You can zoom in pretty good with a 24-bit
system about 10^-6. I think you might be able to do an 8-bit
thing which might allow you to do more than one mandelbrot
generator in the part and cut you clocks/iteration down
to 14-16 (8-bit booth mult takes 6 clocks). There are some
multipliers that will do a better job for this algorithm
they work on the roots of unity and can perform a complex
multiply in one clock cycle. I have not been able to find the
time to implement them though.
Steve Casselman
Virtual Computer
=============================================================
From: David Cary <cary@agora.rdrop.com>
Hi! On the job Last week I was hunting up info about FPGAs because I'd
heard they were cool chips, but I've pretty much given up on them because
I was told a single-seat development system would cost around $30 000
(ouch!).
However, I'm still interested in fractals as a hobbyist.
To do mandelbrot, for each pixel you do the
z <- z^2 + c
iteration over and over until |z|^2 >= 4 or until you're tired.
(you do the same thing for Julia sets, just
the way you set up the initial z and c is different).
where z is a fractional number (floating-point or fixed point).
I don't know how well FPGAs do on multiplies.
Most people keep track of how long it takes for |z| to exceed 2
(the "escape time"), then use that number to pick a color.
(points that "never" escape, i.e., you've given up on iterating it any
more, are traditionally colored black).
Most people give up after a couple hundred iterations ... when you see
the whole set, even with a 1K pixels x 1K pixel screen, I doubt you can
see more than 20 or so iterations.
Mandelbrot and Julia fractals can be calculated pixel-by-pixel,
which is kind of what you're talking about. (If you're going to do
Mandelbrot, you simply *must* do the correspoinding Julia sets as well --
the animation could be interesting).
The only difficulty I see is getting the (probably fixed-point) multiply
to fit into the FPGA. (I've seen some clever schemes that reduce
multiplies to a few look-ups and addition, so that tri(x) or S(x) is a table
lookup, then
A*B = tri(A+B) - tri(A) - tri(B)
or
A*B = (S(A) + S(B) - S(A-B))/2
). Is there room ? I don't know; I know almost nothing about FPGAs.
IFS imaging fractals (the famous fern) are pretty tolerant of mathematical
roundoff error. 10 bits of (fixed-point) precision is probably more than
enough. There are 3D versions of IFS, and it might be interesting to
recalc and rotate them in real time.
There are fractals that don't need fractions and multiplies to calculate:
the serpenski fractal, or
the triangle IFS fractal (only needs addition and divide-by-2)
the L-systems.
However, I don't know any way to generate these fractals (except for the
Mandelbrot and Julia) on a
pixel-by-pixel basis; most algorithms I've seen generate a sequence of x,y
points to be colored, which are never in sequential order. Can you deal
with that ? (have the FPGA calculate new pixel values and randomly put
them in the VRAM, at the same time the VRAM is being sequentially
scanned...)
(I even have a Julia algorithm that claims to be reasonably efficient,
the IIJ algorithm, that just draws the *outline* of the Julia set).
Something different you might want to think about: if you can read as
well as write the DRAM with the FPGA, you might be able to implement
Conway's Life 2D cellular automata. I hear there's a 3-4-3 rule set that
generates more interesting stuff than his original rule set.
(I have a simple 1D cellular automata that generates the triangle fractal
using a completely unrelated algorithm, one line at a time).
--
David Cary
voice: 503.357.0164 email: d.cary@ieee.org
type "finger cary@agora.rdrop.com" for more info.
===========================================================
From: Craig Lindley <cdl@coventry.ac.uk>
A friend of mine made something like this a few years back at Uni. It was
a real-time julia generator. I don`t know any of the specs, but he wrote
a shit-fast generator and programmed it onto some chip (EPROM?). His
idea was that he could sell it to someone like Sony or something, so
that instead of a blank standby screen, they had some fractal zoomer sort
of thing. They weren`t interested, but my friend made a prototype anyway.
Sorry, I know this didn`t help, but I thought it was relevent.
Craig;)
===========================================================
From: Benjohn Barnes <B.Barnes@dcs.warwick.ac.uk>
The fractle triangle thing can be done in a single AND opperation.
you do x AND y. If this is 0, plot a point. If not forget it. I've writen
(with a friend) a prog that does this in real time so dedicated hardware
should do it with no problem.
===========================================================
From: RANDRAKA@ids.net
Ciaran,
Be very careful of the claimed 250 Mhz internal clock rate claims of the FPGA
vendors. For the type of thing you are talking about, you can expect about 40
MHz out of a 3000 series Xilinx...if you are careful in your design. Many of
the designs I rework come to me working at top rates between 15 and 20 Mhz.
Applying reasonable design improvements can get you into the low 40's. Some of
the other families like Quicklogic will get you faster, in the range of about
60 Mhz in some designs. For a Ram based part, I would suggest the Atmel AT6000
or National Semi's CLAy 31. Both have a fine grain architecture that is well
suited for compute intensive algortihms. I've done 30MHz 16 bit array
multipliers in those parts (Can't even come close in Xilinx).
The high 'clock' rates quoted by vendors, particularly Xilinx, pertains to the
maximum flip flop toggle rate. This can be realized for small portions of the
design if it is hand placed and routed, and is really only applicable for
prescale counters and the like. I believe Xilinx's example is a handcrafted
johnson counter.
Note also that the 4000 and new 5000 series xilinx parts are slower than the
3000 series. That means, if you want to use Xilinx, and you need the speed
stick with the 3000 series (they are also cheaper than the 4000).
All that said, your project sounds pretty interesting. Unfortunately, I don't
know a whole lot about generating fractals so I can't give you suggestions in
that area. Once you get a better handle on what computations are required,
however, you would be better off applying more realistic clock rates of
say 30-40MHz to determine how much FPGA real-estate would be required.
Remember, lack of speed may be made up for with parallel and/or pipelined
structures. I would say it is definitely do-able, but it may take more than 1
FPGA to do it. It is easier to design in more hardware and leave yourself some
margin for routing and less than optimum design than to run out of steam and
end up having to use every design trick to just get by. A handcrafted design
done to get the maximum performance can get very time consuming, and requires
an intimate knowledge of the part and the tools.
If you are looking for an FPGA expert familiar with high speed design, I'd be
happy to send you my brochure (by USPS).
Best of luck, and let me know how you do.
-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930 FAX 401/884-7950
email randraka@ids.net
The Andraka Consulting Group is a digital hardware design firm specializing in
obtaining the maximum performance from FPGA's. Services include complete
design, development, simulation and integration of these devices and the
surrounding circuits. We also evaluate, troubleshoot and improve existing FPGA
and board level designs. Please call or write for a brochure.
======================================================================
From: mjodalfr <mjodalfr@nmia.com>
Hopefully, you are planning to do this in real time.
A multiplier in an FPGA is quite expensive ( logic cell/macrocell ) wise, a
5K part won't handle it. Futhermore, 250MHz speeds ??? BAH !!!!! perhaps for a
simple counter, that doesn't ever go anywhere...... Take that figure and div
by 3, to get useable speed. ( of course this really depends on your design....
I have had parts rated at 100MHz run at about 95MHz, but then again, it was
just a simple counter.
For the math to do the fractal stuff, get the books "Fractal and Julia
sets" by Mandelbrot........
Good luck.
Wassail,
MjodalfR
aka Ken Egan
Sr. Elec Engr
American Laser Games
From: MjodalfR <mjodalfr@nmia.com>
Oops forgot something
On a different note, I saw a real cool demo done with 16 T800 transputers
that was about 15 frames/sec.
your rate....160x100x50 = 800K pix sec.
Now consider.... true color ???? would be 2.4Mb/sec... kinda slow.
However, your transformations would be for each component value...r,g,b...
I would suggest a very high density device... Altera's FLEX8000 family does
well with pipelining, or perhaps the newer Actel/Xilinx
==============================================================
From: Trevor Hall <trev@wg.icl.co.uk>
> 1. The FPGA has 5000 internal gates.
> 2. It can run at 250Mhz internaly
^^^^^^
250MHz ! Are you sure about this, sounds like a toggle frequency to me, in
whichcase would I not expect your design to run at this speed.
Please correct me if I am wrong and let me know who is making such a device.
Cheers,
T.H.
==============================================================
From: Davor Slamnig <slama@slama.pub.hr>
Organization: Disorganized
I don't know whether the plasma fractal is a "real" fractal,
but it looks fine and can be generated very quickly.
I found this in Tim Clarke Mars demo description -
the example describes the generation of a height-map using
the plasma fractal. To generate a "normal" 2d image
use the height as the color index, and skip the last
color transformation.
Slama
---------------------------------------------------------------------
This is an excerpt from:
Voxel landscapes and How I did it
---------------------------------
[ Tim Clarke, tjc1005@hermes.cam.ac.uk ]
First, some general points:
---------------------------
The map is a 256x256 grid of points, each having and 8-bit integer height
and a colour. The map wraps round such that, calling w(u,v) the height at
(u,v), then w(0,0)=w(256,0)=w(0,256)=w(256,256). w(1,1)=w(257,257), etc.
Map co-ords: (u,v) co-ordinates that describe a position on the map. The
map can be thought of as a height function w=f(u,v) sampled discretely.
Screen co-ords: (x,y) co-ordinates for a pixel on the screen.
To generate the map:
--------------------
This is a recursive subdivision, or plasma, fractal. You start of with
a random height at (0,0) and therefore also at (256,0), (0,256), (256,256).
Call a routine that takes as input the size and position of a square, in the
first case the entire map.
This routine get the heights from the corners of the square it gets given.
Across each edge (if the map has not been written to at the point halfway
along that edge), it takes the average of the heights of the 2 corners on that
edge, applies some noise proportional to the length of the edge, and writes
the result into the map at a position halfway along the edge. The centre of
the square is the average of the four corners+noise.
The routine then calls itself recursively, splitting each square into four
quadrants, calling itself for each quadrant until the length of the side is
2 pixels.
This is probably old-hat to many people, but the map is made more realistic
by blurring:
w(u,v)=k1*w(u,v)+k2*w(u+3,v-2)+k3*w(u-2,v+4) or something.
Choose k1,k2,k3 such that k1+k2+k3=1. The points at which the map is sampled
for the blurring filter do not really matter - they give different effects,
and you don't need any theoretical reason to choose one lot as long as it
looks good. Of course do everything in fixed point integer arithmetic.
The colours are done so that the sun is on the horizon to the East:
Colour=A*[ w(u+1,v)-w(u,v) ]+B
with A and B chosen so that the full range of the palette is used.
The sky is a similar fractal but without the colour transformation.
========================================================
From: Rogier Wolff <wolff@socrates.et.tudelft.nl>
Hi,
I just did a project with two I960 processors on the board. Calculations
show that we can do 256x256 fractal zooming in real time. The trick is
to do real-time-zooming with one processor while refining the image
in the area where the zoom ends with the other one. I'd suggest a similar
scheme. That would drastically reduce the required number of operations
per time-unit.
========================================================
Thanks again,
Ciaran King.
Ciaran King cking@accutron.ie /\
Accutron Ltd. - Product R&D / \
* Process monitoring/control / <--\-
* Embedded systems design / \
* Data acquisition systems /___/\___\
Article: 762In <3i6ll1$t88@cybernet.cse.fau.edu> tomh@bambi.ccs.fau.edu (Tom Holroyd) writes: > >Here's a way to generate fractals with video hardware in real time. > >First, create a video feedback loop. Do this by aiming the video camera at >the monitor. The monitor and camera settings are important, try the >following general setup: monitor brightness all the way down, or at least >very low (not completely black, obviously). Zoom the camera in so that the >*image* of the monitor on the monitor is about the same size as the monitor >(in other words, aspect ratio close to 1:1). Also, some rotation is >desirable, else you just get a blob that is hard to stabilize. Hint: >turn the monitor upside down, or put it on its side - this is much easier >than trying to mount a camera upside down on a tripod! Oh yeah, tripods are >good. > >At this point you should be able to create lots of swirling, spinning stuff. >Try messing with the color, (B&W is usually easier to start with), phase, >focus, zoom, iris, etc. If the camera and or monitor has automatic features, >turn them all off, you get better control that way. > >The patterns that you see can exhibit spatiotemporal oscillation and chaos, >and can be quite hypnotic. But there is usually a single fixed point on >screen (that is either stable or unstable, depending on the zoom). To >get more complicated patterns like fractals, you need to mix in another >transform. The simplest way to do this is with a mirror. The setup >should look like this: > >monitor > | video camera > | ___ > +-->| >___|---+ > | | ----------------- | > | | mirror | > | | > +------------------------------------+ > >The mirror is positioned so that the camera sees *both* the monitor screen >directly, and a reflected view of it. Now you have two transforms of the >image to play with: the non-linear transform provided by the electronics >of the camera+monitor, and the simple reflection of the mirror. With the >setup above I have been able to create colorful, pulsating, fractal ferns, >and some 'jellyfish' like shapes. Quite different from the usual video >feedback fare, because of the break from circular symmetry. Almost like >life-forms. > >Another way to do this (that I have not tried yet) is with a video mixer. >Point two cameras at the screen, mix their output together and display >it on the screen. With different rotation angles and zoom setting it >should be possible to create lots of cool visual effects. Unfortunately, >I do not have access to a video mixer, so I can't try this myself. I >have tried to do it with the poor man's video mixer, a half-silvered >mirror. I've been able to get some interesting patterns, but there >are some serious constraints on this method. (Anybody know how >I can get (or build) a cheap video mixer? Doesn't have to be fancy.) > >Video feedback is cool in general, and I encourage anybody with a >camcorder to point it at the monitor screen! (Remember to rotate it, >and zoom in to close to 1:1.) It is a great way to demonstrate >nonlinear, self-organizing pattern formation. I have had people >look at the screen and say "where does the pattern come from?" >This is a great excuse to start telling them all about dissipative >structures, reaction-diffusion systems, etc. etc.. Once I even >got a pattern of spiral waves that looks a little like the BZ >reaction. The WWW page with framegrabbed images is, alas, still >"currently under construction" :-( > >Tom Holroyd >Program in Complex Systems and the Brain Sciences The basis of >Florida Atlantic University, Boca Raton, FL 33431 USA stability is >tomh@bambi.ccs.fau.edu instability. >The 9th Amendment of the U.S. Constitution: >"The enumeration in the Constitution, of certain rights, shall not be >construed to deny or disparage others retained by the people." > > I love doing that! I found it out myself fooling around with my camcorder one day. Never tried it with a mirror, though. Scott Cutler SCutler@ix.netcom.comArticle: 763
For you folks that've asked (and asked, and asked) for a cheaper way to do the Xilinx parts, I've just heard there's an entry-level version for $100US that's supposed to do the 2K, 3K and some of the 4K (??) parts. We're about to get it at work (already have the high-priced version), and I'll post a description + comments + comparison when we've run it through it's paces. Since you can get the 3K and 4K parts from Digi-Key now, I'd expect them to be selling the development system Real Soon Now. Beyond what I've overheard at work, I don't have any hard facts on the new package (wait a few weeks). If it's true and it works, it'll be a real boon to those of us wanting to use FPGAs at home. I'm just surprised it took Xilinx soooo long to figure out what MMI found out years ago - sell the chips, give away the software and you'll sell a LOT of chips. Sell the chips, charge LOTS for the software, and you won't sell many of either. Yes, Virginia, there IS a Santa Claus!Article: 764
Vaporware at it's finest :(Article: 765
Ronald Goodstein 205 West Street Needham, MA. 02194 Home (617)-444-2226 Experience: Board and Chip level simulation, ASIC DESIGNER 1993 Jan Chipcom - Southborough,Mass - Contract Engineer 1994 Oct * Created and simulated ethernet, Token-ring bridge board models * Used Mentor 8.2 Quicksim, ACTEL FPGA, TI ASIC, LMC, 68302 and 80960 processors, AMD 7990 LAN chip and LM 1000 hardware modeler * Programed in AMPLE and LMC PCL code for 80960 processor 1992 IBM - Hawthorne, NY - Contract Engineer Gigabit fiberoptic Wan/Lan Project * Created and simulated Gigabit fiberoptic Lan board model. * Used Valid(cadence),Synopsys, VHDL on AIX IBM RS6000 system. * Participated in LAN board lab debug 1991 NCR/AT&T Corporation, Liberty, SC - Contract Hardware Engineer * Simulated 15000 gate array, 1.0 micron CMOS, 208 pin flat pack. * Gate array interfaces C710 SCSI I/O processor to Microchannel bus. * Gate array was successfully debugged and working first time in lab * Completed video tape course on Verilog. 1984 - 1990 Digital Equipment Corporation, Marlboro, MA - Senior Hardare Eng. * Designed, schematic captured, simulated and debugged Toshiba 3200 gate array, 1.5 micron 68 pin grid for Vaxcluster CI Switch. * Recieved patent #4,897,833 for array that arbitrated 8 nodes. * Used CAE2000 schematic Capture system. Simulated using DECSIM. * Timing verified using AUTODLY. Achieved fault coverage of 97%. * Designed NTSC/PAL decoder board for interactive video info system. * Investigated other video technologies for multimedia IVIS. 1982 - 1984 Analytical Systems Engineering Corp, Burlington,MA - Hardware Eng. * Analyzed Air Force Communications System including error correction 80186 microprocessor and data encryption techniques. 1980 - 1982 GTE Sylvania, Needham, MA - Junior Engineer * Performed computer field level analyses around buried ELF (extremely low frequency antenna). 1979 - 1980 McDonnell Douglas, Huntington Beach, CA - Associate Engineer * Redesigned guidance electronics for nuclear environment. Education: Completed 4 Graduate courses in Computer Science at Boston Univ. Completed 6 Graduate courses at Northeastern Univ. in Electrical Syracuse University, BSEE 1979 - G.P.A. 3.0/4.0 Affiliations: Toastmasters International - Competent Toastmaster Award. Member of Boston Computer Society. References: Furnished upon request.Article: 766
In <3i02ch$d85@msunews.cl.msu.edu> jimenez2@oscar.egr.msu.edu (Manuel Alejandro Jimenez-Cede) writes: > >I've been looking for technical info about >fpgas (electrical characteristics, timing, pwr diss., packaging, etc.).Does anybody can suggest me where to find the right databooks? >Or at least a way to get info from manufacturers? > >I'd appreciate any reply. > >Manuel Jimenez > > A good start would be to look at Altera's web server. The URL is http:\\www.altera.com. Jack OgawaArticle: 767
In <3iklm0$dsc@rc1.vub.ac.be>, Luc Deriemaeker <llderiem@vnet3.vub.ac.be> writes: >Does Lattice have an FTP site with updates of the soft, example >programs etc.. > deletes... I haven't played with the download software, but will do so in about 3 weeks. For help, I've been using the 1-800-LATTICE help line. They have a BBS there with downloadable programs. You have to speak to the helpdesk people to get access to the BBS. Kevin Curcuru.Article: 768
In article <gshinD35pL2.3xx@netcom.com> gshin@netcom.com (George Shin) writes:
Hello, i'm looking for following synthesis tools for the Linux platform. I
believe most of them if not all are University tools. Thanks much.
bdsyn
espresso
sis/misII
-gshin
PS BTW, i'm in search of tool like bdsyn but can directly work on FSM rather
than just on the combinatoric logic portion.
SIS from UCB contains both espresso and sis/misII.
ftp ic.eecs.berkeley.edu:/pub/Sis/
sis-1.2.patch1
sis-1.2.tar.Z
Here is the README:
----------------------------------------------------------------------
SIS_paper.ps is the original paper on SIS. Updates to SIS are recorded
in the release notes for each release.
sis-1.2.tar.Z is the latest release of SIS. It can be ftp'd in < 300kb
chunks with the files in sis-1.2-chunks.
ex-temp.tar.Z is a large set of examples. It can be ftp'd in < 300kb
chunks with the files in ex-chunks.
For Linux compilation, just get sis-1.2.tar.Z and the patch file,
sis-1.2.patch1. The patch contains all the Linux patches.
sis-1.2.patch1 contains patches for sis-1.2. It is up-to-date as of
10/30/94. To apply the patches, go to the top-level directory of
sis-1.2, that is, the directory that contains sis-1.2, which contains
sis, nova, etc. Copy sis-1.2.patch1 to this directory, and execute
'patch < sis-1.2.patch1' and the patches will be applied to the files
in the directory sis-1.2.
--
Desmond A. Kirkpatrick (desmond@eecs.berkeley.EDU)
UC Berkeley CAD group
Article: 769Hi, I am looking for university tool which perform placement on xilinx-type FPGA? Please send me e-mail if you have any information about it? Thanks! C.C. Lin UC, Santa Barbara e-mail: linchih@guitar.ece.ucsb.eduArticle: 770
Luc Deriemaeker <llderiem@vnet3.vub.ac.be>: > I recenty bought the ispLSI starter kit from Lattice for > the ispLSI1016, ispGal22V10 and ispGDS14. > Is there anyone out there who played with the kit before and can > give me an evaluation. Is the soft bugfree etc... > In the kit there is a nice software to program the ispLSI1016, but > not the Gal there is only a loader for JEDEC files. Doe anyone know > if there exist a simple compiler on the net that can create this > JEDEC files ? I played a little bit with their package and my feeling is that it is a DEMO. In other words, one could easily do a simple design like a state machine or a counter, i.e. when the chip (1016) contains _one_ structure. Trying to put more will lead you to the necessity of tracking all the connections in a text form (Abel-like language). Besides, the absence of the simulator makes it almost impossible to debug any complex design, unless you output some internal signals and use a scope. All in all, this is a nice package for well tracked combinatorial designs and a hook for people who will appreciate the comfort of "in system programming" and can afford spending real money for their ViewLogic stuff. > Any help is welcome. > > > Luc S.B.Article: 771
#******************************************************************#
CALL FOR PAPERS, TUTORIALS, & WORKSHOPS
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Eighth Annual
APPLICATION SPECIFIC INTEGRATED CIRCUIT
Conference and Exhibit 1995
"Implementing the Information Superhighway
with Emerging Technologies"
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September 18-22
CALL FOR PAPERS, TUTORIALS, & WORKSHOPS
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Workshops: Four or eight hour technical workshops covering ASIC design
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Article: 772
Dear Sir
I am currently a student on University of Hamburg
with emphasys Investment Banking.For my Diploma
"Financial Conditions in Highg Growth ,High technology
Industries" i need more Company name as Xilinx.
I knew alsow Triuqent -GaAS,Altera -?,Actel -?
Can you send me another FPGA company name with
suggest about theys market segment /GaAS,Mos &/
I would very pleased for you
Yours Faithfully GErus
P.S.Under this name R.Alster
/My database teacher/ exist
a different number
from ws4c601 until ws4c620
my number
ws4c619@server1.rrz.uni-hamburg.de
Article: 773In article <3inm67$65u@newsbf02.news.aol.com>, buttoid@aol.com (Buttoid) writes: >Vaporware at it's finest :( Actually does exist with 9404 release (I've had the release for over a month!). Only supports Xilinx at this time. I'm waiting for the Actel and Altera support before I can load it. -- Bob Lindesmith rjl@dow.com This view is mine, not necessarily that of my employerArticle: 774
In article <D4Ex1t.A57@serval.net.wsu.edu> hart@PROBLEM_WITH_INEWS_DOMAIN_FILE (John C. Hart) writes: >Tom Holroyd (tomh@bambi.ccs.fau.edu) wrote: >: Here's a way to generate fractals with video hardware in real time. > >: First, create a video feedback loop. Do this by aiming the video camera at >: the monitor. The monitor and camera settings are important, try the >: following general setup: monitor brightness all the way down, or at least >: very low (not completely black, obviously). Zoom the camera in so that the >: *image* of the monitor on the monitor is about the same size as the monitor >: (in other words, aspect ratio close to 1:1). Also, some rotation is >: desirable, else you just get a blob that is hard to stabilize. Hint: >: turn the monitor upside down, or put it on its side - this is much easier >: than trying to mount a camera upside down on a tripod! Oh yeah, tripods are >: good. > >This is also described at the beginning of Peitgen, Jurgens and Saupe's >``Chaos and Fractals: New Frontiers of Science'' (Springer-Verlag, 1992). > >: Another way to do this (that I have not tried yet) is with a video mixer. >: Point two cameras at the screen, mix their output together and display >: it on the screen. With different rotation angles and zoom setting it >: should be possible to create lots of cool visual effects. > >With a single monitor, several cameras and a mixer you should be able to >produce the attractor of an iterated function system of similtudes. With >several monitors, several cameras and a mixer you get the attractor of a >recurrent iterated function system of similtudes. > >-John Hart >--- >John C. Hart, Asst. Prof. >School of EECS, Wash. St. Univ. >Pullman, WA 99164-2752 >(509)335-2343 fax:(509)335-3818 Hey I'm fascinated to hear that other people see the same connections between fractal making and video feedback. A video camera and monitor is a fast, if crude, iterated function system. I'd like to know if anyone has succeeded in using multiple cameras and/or monitors, and what kind of equipment (esp mixer) they have used. The problem with feedback is that it's TOO chaotic, too messy, though it can be phenomenally beautiful. For better control, I'd like to build a system using a video processing DSP board, rotate and scale and maybe filter an image, then feed the output back in to the front end. Video feedback without a camera. Perfect control, too. Any thoughts on this? Jonathan
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