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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Since there have been a few Intel questions on this newsgroup, let
me update with the latest status.
The contract has been officially signed and closed, so as of
October 1, Altera now totally owns the Intel PLD & FPGA products.
The iFX8160 (I don't know the Altera name yet) has sampled
and shipped to a few customers already. The first silicon
was completely functional! (we are very proud of that!)
PLDshell 4.0 Beta software is available on the Intel FTP
site through October. This is until Altera makes the
official release available.
3 different OS versions of PLDshell are available.
ftp.intel.com:/pub/pld_fpga/software/dos/p40beta.zip (2.6Mb)
/hp700/p40beta.tar.Z (4.5Mb)
/sun4.sunos/p40beta.tar.Z (4.2Mb)
If you have any questions regarding the new Altera
product line, you may call them for more information.
--Richard Vireday
Intel Corporation
Article: 251>Cool. Any idea of time frame for the improved 780's and 740's? This >would eliminate my biggest beef about the FlexLogic chips, the #$@ OTP >EPROM. Yes, the OTP EPROM is a pain unless you find that one perfect embedded application you really want to dedicate the chip towards. The only near-term way to get flash with the FLEXlogic architecture is the 8160. I suspect there will be a longer wait for the 780 and 740 with flash unless Intel had them almost ready to go before they sold the product line to Altera. -- || Dave Van den Bout || || Xess Corporation ||Article: 252
In article <36ggda$muq@raffles.technet.sg> attmes@solomon.technet.sg writes: "Folks, " "Look! AT&T has announced the biggest FPGA device, ORCA 2C26, and it seems "very powerful. Any comments? " "Simon. " ...AT&T advertising stuff deleted ... Simon, Like any new device, the experience of real users (as often discussed here) is the real determination its worth. If I want to read AT&T's promotional stuff, I just phone or mail them. Well, you did ask! David Pashley Direct Insight Ltd +44 280 700262Article: 253
Eric Edwards (Eric@wolf359.exile.org) wrote: > In article <36h0ur$lpr@char.vnet.net>, David Van den Bout writes: > Cool. Any idea of time frame for the improved 780's and 740's? This > would eliminate my biggest beef about the FlexLogic chips, the #$@ OTP > EPROM. Isn't OTP EPROM a contradiction in terms? :-) -- ------- Bryan Butler bbutler@netcom.comArticle: 254
As some of you have noticed, our WWW server went off line over the weekend. Two things happened: 1) the file system holding the WWW pages moved to a different physical machine, and I had foolishly published the physical (rather than logical) machine name; and 2) we finally are running HTTP. So... the correct URL is now (and I'm told should remain): http://www.super.org:8000/FPGA/caf.html For those of you who still want ftp access, you can find it at: ftp://ftp.super.org/pub/www/FPGA/caf.html I'll try to track down some of the major sites which point to the comp.arch.fpga page. As always, send problems or comments to jma@super.org -jeff ------ Jeffrey Arnold IDA Supercomputing Research Center 17100 Science Dr. Bowie, MD 20715 email: jma@super.orgArticle: 255
Hi, I'm a customer of Xilinx products in Korea. I need some assistance on technical questions about Xilinx products I purchased. Is there any kind personnel who can tell me about the email address of Xilinx office that can handle this matter? Thanks a lot in advance. Saeyang.Article: 256
Hi! I'm interested in any experiences people made with the Virtual Computer Corporation's Engineers' Virtual Computer (EVC1) and the SRAM Module available for it. (e.g. problems, successfull applications etc.) Markus -------- Markus Weinhardt, Lehrstuhl IPD Prof. Goos, Universitaet Karlsruhe Postf. 6980, Vincenz-Priessnitz-Str. 3, D-76128 Karlsruhe, Germany ==> NEW ADDRESS !!! -----------------^---------------------------- Tel.(49)721/6086086 Fax:(49)721/691462 Email:weinhard@ira.uka.deArticle: 257
In article <Cww790.ALo@bbc.co.uk>, phill@dd.eng.bbc.co.uk (Phil Layton) writes: |> David Pashley (david@fpga.demon.co.uk) wrote: |> ... [deleted to save space] |> |> : Some older programmers have trouble with this particular device as |> : the susceptibility to clock pin noise is somewhat higher than the |> : norm. |> |> : David Pashley ... |> |> Unfortuanately there are programmers around - Stag 3000 in particular |> - that for some unknown reason treat the Xilinx serial proms as PLDs |> and therefore insist on Jedec format. Stag in the past have been prepared |> to give out conversion utilities to customers who complain or it is fairly |> straight forward to write your own. |> |> -- |> .... |> * Phil Layton, Senior R & D Engineer * Thank you for your advice - David, unfortunately we have access to a Stag 3000 only, which as you say, Phil, treats the Xilinx serial PROMS as PLD's! Anyway, the problem is solved now. My apologies for not responding to your postings sooner - I do not get an opportunity to read this (very useful) newsgroup very often. -- Tomas.Article: 258
Has anyone had any experience with the new Motorola MPA devices? Since the devices are new, I don't expect that there are many experts on them yet (excepting Motorola). The architecture is quite interesting. The devices use a fine-grained architecture and use hierarchical routing. Any input would be appreciated. The only info I have is a literature pack from Motorola. --Jeff ====================================================================== Jeff Hutchings Director Of Engineering Metalithic Systems, Inc. ====================================================================== e-mail: hutch@metalith.com ======================================================================Article: 259
Does anyone out there know what happened to CLI and their FPGA product line? -- Jeffrey David Cohen cohen@cs.cornell.edu http://www.cs.cornell.edu/Info/People/cohen/home.html finger or www for pgp keyArticle: 260
Does anyone know if there are ORCA design tools for Mentor and if yes how good they are? -Jeff.Article: 261
In article <1994Oct5.193827.3005@cs.cornell.edu>, cohen@cs.cornell.edu (Jeffrey David Cohen) writes: |> |> Does anyone out there know what happened to CLI and |> their FPGA product line? Atmel took over the whole FPGA business from Concurrent Logic last year. It seems that they are continuing with all the products. They have a new "Configurable Logic Handbook" 94/95 which covers AT(CLI)6000 Series. Phone : 408 4410311 (headquarter San Jose) ***************************************************************************** Swiss Federal Institute of Technology * Email: edi@ife.ee.ethz.ch Electronics Laboratory * High Performance Computing * Edi Hiltebrand * Tel: +41 1 632 27 61 8092 Zurich, Switzerland * Fax: +41 1 632 12 10 *****************************************************************************Article: 262
Совместное Российско - Германское предприятие "Тезис - Интехна",
явлющееся oфициальным представителем компании Actel Corp. (США),
предлагает программируемые пользователем вентильные матрицы (FPGA) и
средства автоматизированного проектирования для работы с ними.
СП также может провести разработку микросхем как по полному маршруту,
так и по любому этапу, и поставить Вам рабочие образцы.
25 -26 октября СП "Тезис - Интехна" проводит в Воронеже семинар-
презентацию FPGA - микросхем и САПР компании Actel Corp., на
которой будут присутствовать представители компании Actel Сorp. и
немецкой микроэлектронной фирмы Thesys GmbH. Если Вы желаете
принять участие в этом мероприятии, то сообщите об этом,
пожалуйста, не позднее 15-го октября для заказа гостиницы.
E_mail : jv@itn.voronezh.su
Тел. (0732) 56-59-19
Тел\факс (0732) 55-36-97.
Кадомский В.С.
Article: 263The AT&T ORCA FPGA are supported via NeoCAD which run under Mentor Graphics throught the Open Door arrangement. Contact NeoCAD or you Mentor Sales Person for info and pricing. BTW NeoCAD is a very nice tool and it supports multiple FPGA architectures from one database, so you can compare the different FPGA architectures. Tom Tessier Ball RTI.Article: 264
I require a few pics of the Xilinx LCA, CLB etc for an overview of their architecture in my final year thesis. If anyone has any, or could tell me where to get some I would be grateful. Otherwise I'll just have to draw them myself :(. Regards John -- John Fulton, STUD IEAust | Computer Science Email: fulton@lucifer.latrobe.edu.au | and Electronic Eng TEL: 853 9068 | La Trobe UniversityArticle: 265
I am interested in learning more about FPGAs. Frankly I spend most of my design time fiddling with high speed analog and other black magic and my knowledge of programmable digital logic is a bit thin. I'm looking for a FAQ or a list of reference books. I've been bothering my parts reps for data books and reading up in them but frankly they are a bit one sided. Thanks. If you could, reply by email. -- Robert Young bz099@cleveland.Freenet.edu It needs more string! It will never work without more string!Article: 266
Hello,
I discovered today that my university doesn't have any
documentation on the XNF file format. This is a serious
problem for me, as I have a design with app. 400 CLBs
which I would like to translate directly into an XNF file...
I have seen that some translators exist on the net, so there
must *be* documentation. Can anybody help me with this
problem, maybe point me at the right spot?
Thanks in advance
Bernd
--
"And the band played 'Waltzing Matilda' / as we stopped to bury our slain;
And we buried ours / and the Turks buried theirs | ..... living in Oz ....
And it started all over again" |
(The Pogues, "Waltzing Matilda", orig by Eric Bogle, "And the band played WM")
Article: 267Bernd Meyer (umisef@yoyo.cc.monash.edu.au) wrote: : Hello, : I discovered today that my university doesn't have any : documentation on the XNF file format. This is a serious : problem for me, as I have a design with app. 400 CLBs : which I would like to translate directly into an XNF file... : I have seen that some translators exist on the net, so there : must *be* documentation. Can anybody help me with this : problem, maybe point me at the right spot? XNF documentation is only available from Xilinx under NDA, what format is your 400 CLB design in at the moment, we might be able to help convert it? -- ================================================================= Aedan Coffey, Toucan Technology, Technology Centre, Mervue, Galway, Ireland. Phone +353-91-757223/770007 Email: coffey@iol.ieArticle: 268
List of FPGA-based Computing Machines
Maintained by: Steve Guccione
guccione@ccwf.cc.utexas.edu
Last Updated: 9/28/94
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
System name: ACME (Adaptive Connectionist Model Emulator)
FPGA Devices: 14 Xilinx XC4010s and 6 Xilinx XC3195s
On-board RAM: 7 4K Dual-ported global memories
each 4010 has a 4k Dual-ported memory
External bus: SBUS
Interconnect: Clos Network between 4010s and 3195s
3195s are used as programmable interconnect
among 4010s and with global memory
Contact: Pak K. Chan
Computer Engineering Board
225 Applied Sciences
University of California
Santa Cruz, CA 95064
Email: pak@cse.ucsc.edu
Notes: See FPGA'94 Berkeley ACM Workshop
System name: Anyboard
FPGA Devices: 5 Xilinx 3042
On-board RAM: 384K
External bus: ISA
Interconnect: Fixed buses
Contact: David E. Van den Bout
ECE Department
North Carolina State University
Raleigh, NC 27695-7911
Notes:
System name: ArMen
FPGA Devices: 1 3090 per node. The MIMD/FPGA parallel machine is
modular and extensible.
On-board RAM: 1, 2 or 4Mb/node
each board has a T805 processor with 4 20Mb/s links.
External bus: SBUS Archipel board with a T805.
I/Os can be handled directly within ArMen using additional
transputer/peripheral boards.
Interconnect: Processor interconnection is host system dependent.
We have two 8 nodes computers configures as cubes.
3090 south and west ports are assembled into a linear
ring with 36bits data path. North ports are mapped in the
processor address space, so that they receive address/data
from their local processor. The FPGA 32 bit south port is
free for extensions or input/output on each node.
Contact: Bernard Pottier
Laboratoire d'Informatique de Brest
Universite de Bretagne Occidentale
UFR Sciences, BP 802,
Brest, 29285, FRANCE.
Email: pottier@univ-brest.fr
Notes: See Napa FCCM 93 and 94 or Hawai HICSS-94 proceedings.
ArMen can easily be connected to any host having
an interface board for transputers. There are projects
for commercial distribution
System name: BORG
FPGA Devices: 2 Xilinx 3030s and 2 Xilinx 3042s
On-board RAM: 2K
External bus: PC-bus interface in 5th FPGA
Interconnect: 4 FPGAs in a Clos network
2 FPGAs can be used as interconnect or logic
Contact: Pak K. Chan
Computer Engineering Board
225 Applied Sciences
University of California
Santa Cruz, CA 95064
Email: pak@cse.ucsc.edu
Notes: 25 boards made by Xilinx and distributed
for educational purposes.
See FPGA'92 Berkeley ACM Workshop
System name: BORG II
FPGA Devices: 2 Xilinx 4003As and 2 Xilinx 4002As
On-board RAM: 8K
External bus: PC-bus interface in 5th FPGA
Interconnect: 4 FPGAs in a Clos network
2 FPGAs can be used as interconnect or logic
Contact: Pak K. Chan
Computer Engineering Board
225 Applied Sciences
University of California
Santa Cruz, CA 95064
Email: pak@cse.ucsc.edu
Notes: 100 boards made by Xilinx and distributed
for educational purposes.
FPGAs are socketed and can be replaced by
any 4000 series pc84 part.
System Name: Chameleon
FPGA Devices: 7 Algotronix CAL
External Bus:
Interconnect: Fixed mesh
Contact: Cuno Pfister
pfister@cs.inf.ethz.ch
Notes: Experimental workstation from ETH Zurich with FPGA's
closely coupled to MIPS R3000 processor and innovative
object based design software written in the Oberon
language.
System name: CHAMP (Configurable Hardware Algorithm
Mappable Processor)
FPGA Devices: 16 Xilinx 4013
On-board RAM: 512K Dual-ported
External bus: VME
Interconnect: Crossbar (using FPGAs)
Contact: Brian Box
Lockheed Sanders
NCA01-2244
P.O Box 868
Nashua, NH 03060
Phone: (603) 885-7487
FAX: (603) 885-9056
Email: box@nhquax.sanders.lockheed.com
Notes:
System name: CHS 2x4
FPGA Devices: 9 Algotronix CALs (1 controller + 8 compute)
On-board RAM: 2 MB SRAM
External bus: ISA
Interconnect: Fixed mesh
Contact: Tom Kean
Xilinx Development Corp.
53 Mortonhall Gate
Edinburgh EH16 6TJ
Phone: 44 31 666 2600ext204
Fax: 44 31 666 0222
Email: tomk@xilinx.com
Notes: Based on work at the University of Edinburgh by
Tom Kean and John Gray. Commercialized by Algotronix.
Algotronix purchased by Xilinx in 1993. System
cascadable to 2 boards. No longer commercially
available.
System name: CM-2X
FPGA Devices: 16 Xilinx 4005
On-board RAM: None
External bus: Fixed
Interconnect: None
Contact: Craig Reese
IDA Supercomputing Research Center
17100 Science Drive
Bowie, MD 20715
Phone: (301) 805-7479
FAX: (301) 805-7602
Phone: cfreese@super.org
Notes: A Connection Machine 2 SIMD machine from
Thinking Machines Corporation with the Weitek
WTL3164 floating point processors replaced
by Xilinx 4005s. De-commissioned 1994.
System name: DSP-56X
FPGA Devices: 1 Xilinx 3042
On-board RAM: 32KW-128KW (shared with DSP56000)
External bus: SBus & Flexible
Interconnect: See notes below.
Contact: Michael C. Peck
President
Berkeley Camera Engineering
3616 Skyline Drive
Hayward, CA 94542-2521
Phone: 510-889-6960
Fax: 510-889-7606
email: mikep@bce.com
Notes: The DSP-56X is an SBus card that contains a
40MHz Motorola 5600x family DSP, a Xilinx 3042, and
memory (32K words or 128K words I believe). The
3042 sits directly on the 56000 bus and can
be accessed from either the 56000 or the SBus.
Some of the Xilinx pins are connected to the
SBus back panel connector.
System name: DTM-1
FPGA Devices: 16 DTM chips
On Board RAM: 32 8K x16 SRAM banks on separate DTM ports,
dual ported to host
External Bus: VME
Interconnect: Packed Exponential Connections (a multi-grid mesh network)
Contact: Worth Kirkman
MITRE Corporation
7525 Colshire Dr.
McLean, VA 22102
Phone: (703)883-7082
FAX: (703)883-6708
Email: kirkman@mitre.org
Notes: Built from custom DTM chips. These devices are custom
RAM-configurable 64x64 arrays of expandable-gate cells,
each pipelined for 2 boolean input evaluations in a
100MHz cycle. 256 I/O pins, each arbitrary direction
with echo-cancellation and programmable parallel<=>
serial sub-sampling - normally run at 1/4 the internal
rate.
System name: EVC (The Engineers Virtual Computer)
FPGA Devices: 1 Xilinx 4010
On-board RAM: Daughter board (see notes)
External bus: SBus
Interconnect: None
Contact: Steve Casselman
Virtual Computer Corporation
Reseda, CA 91335
Phone: (818) 342-8294
FAX: (818) 342-0240
Email: sc@vcc.com
Notes: The EVC is a single FPGA based transformable
computing system. It has a daughter board area
that has 96 user I/O from the 4010. A 2 Meg fast
SRAM daughter board is available now.
System Name: G-800 System
FPGA Devices: Grouped in modules (maximum 16 -- see Notes below)
On-board RAM: See Notes below
External Bus: VESA (VL) Local bus
VESA Media Channel - 100 MB/sec video bus
80 pin connector supports 32 bit devices
Interconnect: Bus Oriented Communication - Virtual Bus
All Interconnect via Xilinx 4010's on G-800
2x32 bit buses and 2x16 bit buses on G-800
Configuration is programmable - Virtual Bus
Contact: bovarga@gigaops.com
2374 Eunice St.
Berkeley, CA. 94708
Notes: Modules have standard form factor and pinout.
All bus lines to G-800 connect via FPGAs.
Up to 16 modules of all types on 1 G-800 board.
Visual Computing Module (VMC)= 2xXC4005; 4MB DRAM
and 80 MIPS DSPS
PGA10MOD = 1 x XC4010, 2MB DRAM, 128K SRAM
PROTOMOD = same as PGA10MOD with pinouts extended
to pads for wirewrap, logic analyzer, etc.
16xVCMs = 32 XC4005's, 2 XC4010's on G-800, 64 MB DRAM
16xPGA10MODs = 16 XC4010's, 2 XC4010's on G-800, and
32 MB DRAM and 2 MB SRAM
XPGAMOD = 4xXC4010, 8 MB DRAM, 512K SRAM (available Oct)
16xXPGAMODs = 32 XC4010's, 2 XC4010's on G-800, and
128 MB DRAM and 8 MB SRAM
System name: GANGLION
FPGA Devices: 24 Xilinx 3090
On-board RAM: 24K PROM
External bus: VME / Datacube MAXbus
Interconnect: Fixed
Contact: Charles Cox
IBM Research Division
Almaden Research Center
San Jose, CA 95120-6099
Notes: Used exclusively for neural networks.
System name: HARP1
FPGA Devices: 1 Xilinx 3195
On-board RAM: 64K SRAM / 4MB DRAM
External bus: 4 x 20Mbit/sec transputer links +
expansion port (spare FPGA pins)
Interconnect: None
Contact: Ian Page
Oxford University Computing Laboratory,
Wolfson Building, Parks Road, Oxford OX1 3QD, U.K.
+44 1865 273853
FAX: +44 1865 273839
EMail : Ian.Page@comlab.ox.ac.uk
Notes: The HARP1 is an industry standard TRAM board (size 6 =
165 x 84mm) containing a 32-bit RISC-style
microprocessor (a T805 transputer) with 4 Mbytes of
dynamic RAM. Two independent banks of 32K x 16-bit
fast static RAM are attached to the Xilinx 3195 Field
Programmable Gate Array. The FPGA has full access to
the microprocessor bus. A 100MHz frequency synthesiser
is used for arbitrary clock generation. An expansion
port is connected to the spare FPGA pins. TRAM
motherboards allow for easy integration into a variety
of host systems, or for connecting multiple HARP boards
together.
For more information see:
http://www.comlab.ox.ac.uk/oucl/people/ian.page.html
System name: Marc-1
FPGA Devices: 25 Xilinx 4005 (18 processing + 5 interconnect +
2 control)
On-board RAM: 6 MB
External bus: SBus
Interconnect: 5 Xilinx 4005
Contact: David M. Lewis
University of Toronto
Department of Electrical Engineering
Toronto, Canada
Email: lewis@eecg.toronto.edu
Notes: Marc-1 consists of two modules. Each module
contains an instructions unit of 3 Xilinx 4005s,
a datapath of 6 Xilinx 4005s, a 256K x 64
instruction memory, a 256K x 32 data memory
and a Weitek 3364. These are connected by an
interconnect module of 5 Xilinx 4005s. Two more
Xilinx 4005s are used to interface to the Sun
Sparc host.
System name: Mushroom
FPGA Devices: 7 Xilinx 3090
On-board RAM: 5Mb 35ns static RAM
External bus: VME (Sun 3/110 as host)
Interconnect: Fixed busses
Contact: Mario Wolczko
now at : Sun Microsystems Labs, Mario.Wolczko@sun.com
or
Ifor Williams
now at: ADC, 100140.2651@CompuServe.COM
Project was based at the University of Manchester,
England, 1987-92.
Notes: See: `Using FPGAs to Prototype New Computer Architectures,'
Ifor Williams, in `FPGAs', Abingdon EE&CS Books,
edited by Will R Moore and Wayne Luk, 1991, pp 373-382.
Mushroom was a prototypical implementation of a
RISC architecture designed to support dynamic
object-oriented languages.
System name: nfXboard
FPGA Devices: 1 Intel NFX780 in 84-pin PLCC
On-board RAM: None
External bus: IBM-PC printer port
Interconnect: None
Contact: XESS Corp.
1-800-549-XESS
devb@vnet.net
Description: The nfXboard is a small 4''x 2'' board containing an
Intel NFX780 FPGA in 84-pin PLCC package.
The nfXboard is programmed using the PLDasm HDL and
Intel's free PLDshell Plus programming environment.
Configuration files are downloaded to the nfXboard
through the PC printer port using the JTAG protocol.
Additional signals from the printer port can be used to
exercise the downloaded design and the results can be
observed using the 7-segment LED on the nfXboard. The
nfXboard can be used stand-alone or it can be mounted in
a protoboard (all 84 pins are made available on two rows
of 42 pins each). Since configuration is done using a
JTAG stream, it is easy to cascade multiple nfXboards to
experiment with larger designs. Inter-FPGA wiring has
to be added manually, however.
A book accompanies the nfXboard:
"FPGA Workout: Beginning Exercises with the Intel
FLEXlogic FPGA". Softcover, 240 pp., 120
illustrations, and index. ISBN 0-9642187-0-4.
This book shows how to use FPGAs to build digital systems
ranging from simple combinational logic up to a 4-bit
microcontroller. All PLDasm examples in the book
can be downloaded into the nfXboard and tested.
System name: nP (The Nano Processor)
FPGA Devices: 2 Xilinx 3090
On-board RAM: 64K SRAM / 1M DRAM
External bus: ISA
Interconnect: Fixed
Contact: National Technology, Inc.
9500 South 500 West Suite #104
Sandy, UT 84070
Phone: (801) 561-0114
FAX: (801) 561-4702
Email: wirthlin@gecko.ee.byu.edu
Notes:
System name: PAM (Programmable Active Memories) (perle-0)
FPGA Devices: 25 Xilinx 3020
On-board RAM: 0.5 MB
External bus: VME
Interconnect: Fixed mesh
Contact: Patrice Bertin
Paris Research Laboratory
Digital Equipment Corporation
85, avenue Victor Hugo
92500 Rueil-Malmaison, France
bertin@prl.dec.com
Notes: Replaced by the DEC PAM perle-1.
System name: PAM (Programmable Active Memories) (PeRLe-1)
FPGA Devices: 24 Xilinx 3090
On-board RAM: 4MB SRAM
External bus: DEC TURBOchannel
Interconnect: Fixed mesh
Contact: Patrice Bertin
Paris Research Laboratory
Digital Equipment Corporation
85, avenue Victor Hugo
92500 Rueil-Malmaison, France
bertin@prl.dec.com
Notes: Set the record for RSA encryption in 1990.
System name: PRISM (Processor Reconfiguration through
Instruction Set Metamorphosis)
FPGA Devices: 4 Xilinx 3090
On-board RAM: None
External bus: 16 bit
Interconnect: None
Contact: Mike Wazlowski or Harvey Silverman
Laboratory for Engineering Man/Machine Systems
Brown University
Providence, RI 02912
{mew,hfs}@lems.brown.edu
Notes: Notable for its use of C as the description language
for the programmable logic.
System name: PRISM-II (Processor Reconfiguration through
Instruction Set Metamorphosis)
FPGA Devices: 3 Xilinx 4010 per processing node
On-board RAM: 128K x 32 per 4010
External bus: 64 bit writes, 32 bit reads, on processor bus
(it's not external)
Interconnect: Inverted tree, or none, application selectable
Contact: Mike Wazlowski or Harvey Silverman
Laboratory for Engineering Man/Machine Systems
Brown University
Providence, RI 02912
{mew,hfs}@lems.brown.edu
Notes: Each PRISM-II board is a node in the Armstrong III
loosely-coupled parallel processor. The host CPU is a
33Mhz AMD Am29050 RISC processor. There are 20 nodes
that are connected by a reconfigurable (of course)
interconnection topology.
System name: R16 and RISC4005
FPGA Devices: 1 Xilinx XC4005
On-board RAM: 64K Words (16 bit words)
External bus: R16 bus, 16 bit addr, 16 bit data,
Synchronous at 20 MHz
Interconnect: Any
Contact: Philip Freidin
Fliptronics
468 S. Frances St,
Sunnyvale, CA 94086
Phone: (408) 737-8060 or at Xilinx (408) 879-5180
email: philip@xilinx.com
Notes: A 16 bit RISC processor that requires 75% of an
XC4005, 16 general registers, 4 stage pipeline,
Target speed is 20 MHz. Can be integrated with
peripherals on 1 FPGA, and ISET can be extended.
System name: Rasa Board
FPGA Devices: 3 Xilinx 4010
On-board RAM: 320K SRAM
External bus: ISA
Interconnect: 2 Aptix FPICs
Contact: Herman Schmit
ECE Department
Carnegie Mellon University
Pittsburgh, PA 15213
Phone: (412) 268-2476
Notes: Integrated with a behavioral synthesis tool which
allows specification of the desired algorithm in
behavioral Verilog or C.
System name: RIPP (Reconfigurable Interconnect Peripheral
Processor)
FPGA Devices: 8 Altera FLEX 81188
On-board RAM: 2 MB SRAM
External bus: ISA
Interconnect: Fixed buses / programmable interconnect
(see Description)
Contact: Nick Tredennick
Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
Phone: (408) 894-7000
Email: nickt@altera.com
Notes: Up to 8 Altera FLEX 81188 parts, each of which
may be replaced by an ICUBE IQ160 Field Programmable
Interconnect Device (FPID). Devices are grouped
into 4 pairs of 2 devices, each sharing an SRAM
device. Designed by David E. Van den Bout of the
Anyboard project.
System name: SPARXIL
FPGA Devices: 3 Xilinx XC4010s
On-board RAM: 2 256Kx32bit SRAMs for user data
1 128Kx8bit SRAM for on-board configuration cache
External bus: SBus
Interconnect: fixed
Contact: Andreas Koch
Institut f"ur theoretische Informatik
Abteilung Entwurf Integrierter Schaltungen
Gaussstr. 11
D-38106 Braunschweig, Germany
Email: a.koch@tu-bs.de
Notes: See FPL'93 Oxford workshop
System name: SPACE (Scalable Parallel Architecture for
Concurrency Experiments)
FPGA Devices: 16 Algotronix CAL
On-board RAM:
External bus: Custom
Interconnect: Fixed grid
Contact: George Milne
HardLab
Department of Computer Science
University of Strathclyde
Glasgow G1 1XH
Scotland, UK
Notes: Used for physics research.
System name: Spyder
FPGA Devices: 5 Xilinx 4003, 2 Actel A1280
On-board RAM: 128K SRAM plus 2K fast registers
External bus: VME and Sun SBus
Interconnect: Fixed
Contact: Christian Iseli
Logic Systems Laboratory
Swiss Federal Institute of Technology
CH-1015 Lausanne
Switzerland
Email: chris@lslsun.epfl.ch
Notes: A reconfigurable VLIW machine.
System name: Spyder (version 2)
FPGA Devices: 3 Xilinx 4008 (upgradable to 4010),
2 Xilinx 4005, 1 Actel A1280 and
1 Actel A1225
On-board RAM: 128K SRAM plus 4K fast registers
External bus: VME
Interconnect: Fixed
Contact: Christian Iseli
Logic Systems Laboratory
Swiss Federal Institute of Technology
CH-1015 Lausanne
Switzerland
Email: chris@lslsun.epfl.ch
Notes: A reconfigurable VLIW machine. A newer version
of Spyder.
System name: SPLASH
FPGA Devices: 32 Xilinx 3090
On-board RAM: 4 MB SRAM
External bus: VME
Interconnect: Linear array
Contact: Jeffrey M. Arnold
IDA Supercomputing Research Center
17100 Science Drive
Bowie, MD 20715
Phone: (301) 805-7479
FAX: (301) 805-7602
Phone: jma@super.org
Notes: Replaced by SPLASH 2.
System name: SPLASH 2
FPGA Devices: 16 Xilinx 4010
On-board RAM: 8 MB
External bus: Sun SBus
Interconnect: Linear array plus crossbar
Contact: Jeffrey M. Arnold
IDA Supercomputing Research Center
17100 Science Drive
Bowie, MD 20715
Phone: (301) 805-7479
FAX: (301) 805-7602
Phone: jma@super.org
Notes:
System name: The Stack
FPGA Devices: 8 iFX 780
On-board RAM: 4-8x 8kx24 Fast Sram
External bus: Proprietary 16 bit NRZ bus designed for
extensive cabling
Interconnect: 420Mb/s 13/24 bit input bus,
30Mb/s OC bus between all nodes, 600Mb/s memory
Contact: Peter Averkamp
Tech. Univ. of Munich
Physics Dept. E20
James-Franck-Str. 1
D-85748 Garching, Germany
Email: petav@e20.physik.tu-muenchen.de
Notes: Used in conjunction with GHz ECL logic
for on-line data reduction algorithms
in subnanosecond Synchrotron Experiments
System name: TbC-Pamette (PAM - Programmable Active Memories)
FPGA Devices: 1 to 4 Xilinx 40XX in PQ-208 package
Currently supported configurations: 4010 + 4003H
4 x 4010
On-board RAM: Daughter board (see notes)
External bus: DEC TURBOchannel
Interconnect: Fixed mesh 2 x 2 matrix
Contact: Mark Shand
Paris Research Laboratory
Digital Equipment Corporation
85, avenue Victor Hugo
92500 Rueil-Malmaison, France
shand@prl.dec.com
Notes: 128 user I/O to daughter board. Synchronous RAM daughter
board is under development.
Pamette is targeted as a generic I/O adapter with local
compute capability.
System name: TM-1 (Transmogrifier 1)
FPGA Devices: 4 Xilinx 4010
On-board RAM: 4 32Kx9 SRAMs
External bus: custom to SUN workstation
Interconnect: entirely programmable using Aptix AX1024 FPIC
Contact: Jonathan Rose
Dept. of Electrical and Computer Engineering
University of Toronto
6 King's College Road
Toronto, Ontario
Canada M5S 1A1
Email: jayar@eecg.toronto.edu
Notes: Intended more for rapid prototyping of circuits, but
can be used for computing.
System name: VZ80 (Pin compatible replacement for the Zilog Z80 8 bit uP)
FPGA Devices: 2 Xilinx 4013s
On-board RAM: Not applicable
External bus: 40 Pin DIP socket to any Z80 motherboard (ex:TRS-80)
Interconnect: Fixed wire wrapped interconnect
Contact: Gregory Recupero
VAutomation Inc.
71 Spit Brook Rd.
Suite 306
Nashua NH 03060
Email: greg@VAutomation.com
Notes: From synthesizable VHDL model available from VAutomation.
System name: V6502 (Pin compatible replacement for the Rockwell 6502 8 bit uPFPGA Devices: 1 Xilinx 4013
On-board RAM: Not applicable
External bus: 40 Pin DIP socket to any 6502 motherboard (ex:AppleII-C)
Interconnect: Fixed wire wrapped interconnect
Contact: Eric Ryherd
VAutomation Inc.
71 Spit Brook Rd.
Suite 306
Nashua NH 03060
Email: eric@VAutomation.com
Notes: From synthesizable VHDL model available from VAutomation.
System name: The Virtual Computer (P-Series)
FPGA Devices: Up to 52 Xilinx 4013
On-board RAM: Up to 8 MB SRAM, 256K dual-ported SRAM
External bus: Bus Independent - Current SBus interface
Interconnect: Up to 24 ICUBE FPID
Contact: Steve Casselman
Virtual Computer Corporation
Reseda, CA 91335
Phone: (818) 342-8294
FAX: (818) 342-0240
Email: sc@vcc.com
Notes: The Virtual Computer P-Series consists of P1,
P2, P3 and P4. The P1 has 14 4013s the P2 26
4013s the P3 40 4013s and the P4 has 52 4013s.
System name: Windchime
FPGA Devices: Actel 1020A (1-3 per processor)
On-board RAM:
External bus:
Interconnect: Mesh connected wormhole routing
Contact: Erik Brunvand
CS Dept.
University of Utah
Salt Lake City, UT, 84112
Email: elb@cs.utah.edu
Phone: (801)581-4345
FAX: (801)581-5843
Notes: MIMD multiprocessor. Used for
self-timed circuit experimentation.
System name: X-12
FPGA Devices: 12 Xilinx 3195
On-board RAM: 384K SRAM (32K per FPGA)
External bus: ISA
Interconnect: Fixed common bus
Contact: National Technology, Inc.
9500 South 500 West Suite #104
Sandy, UT 84070
Phone: (801) 561-0114
FAX: (801) 561-4702
Email: wirthlin@gecko.ee.byu.edu
Notes:
Article: 269
List of FPGA-based Computing Machines
Maintained by: Steve Guccione
guccione@ccwf.cc.utexas.edu
Last Updated: 9/28/94
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
System name: ACME (Adaptive Connectionist Model Emulator)
FPGA Devices: 14 Xilinx XC4010s and 6 Xilinx XC3195s
On-board RAM: 7 4K Dual-ported global memories
each 4010 has a 4k Dual-ported memory
External bus: SBUS
Interconnect: Clos Network between 4010s and 3195s
3195s are used as programmable interconnect
among 4010s and with global memory
Contact: Pak K. Chan
Computer Engineering Board
225 Applied Sciences
University of California
Santa Cruz, CA 95064
Email: pak@cse.ucsc.edu
Notes: See FPGA'94 Berkeley ACM Workshop
System name: Anyboard
FPGA Devices: 5 Xilinx 3042
On-board RAM: 384K
External bus: ISA
Interconnect: Fixed buses
Contact: David E. Van den Bout
ECE Department
North Carolina State University
Raleigh, NC 27695-7911
Notes:
System name: ArMen
FPGA Devices: 1 3090 per node. The MIMD/FPGA parallel machine is
modular and extensible.
On-board RAM: 1, 2 or 4Mb/node
each board has a T805 processor with 4 20Mb/s links.
External bus: SBUS Archipel board with a T805.
I/Os can be handled directly within ArMen using additional
transputer/peripheral boards.
Interconnect: Processor interconnection is host system dependent.
We have two 8 nodes computers configures as cubes.
3090 south and west ports are assembled into a linear
ring with 36bits data path. North ports are mapped in the
processor address space, so that they receive address/data
from their local processor. The FPGA 32 bit south port is
free for extensions or input/output on each node.
Contact: Bernard Pottier
Laboratoire d'Informatique de Brest
Universite de Bretagne Occidentale
UFR Sciences, BP 802,
Brest, 29285, FRANCE.
Email: pottier@univ-brest.fr
Notes: See Napa FCCM 93 and 94 or Hawai HICSS-94 proceedings.
ArMen can easily be connected to any host having
an interface board for transputers. There are projects
for commercial distribution
System name: BORG
FPGA Devices: 2 Xilinx 3030s and 2 Xilinx 3042s
On-board RAM: 2K
External bus: PC-bus interface in 5th FPGA
Interconnect: 4 FPGAs in a Clos network
2 FPGAs can be used as interconnect or logic
Contact: Pak K. Chan
Computer Engineering Board
225 Applied Sciences
University of California
Santa Cruz, CA 95064
Email: pak@cse.ucsc.edu
Notes: 25 boards made by Xilinx and distributed
for educational purposes.
See FPGA'92 Berkeley ACM Workshop
System name: BORG II
FPGA Devices: 2 Xilinx 4003As and 2 Xilinx 4002As
On-board RAM: 8K
External bus: PC-bus interface in 5th FPGA
Interconnect: 4 FPGAs in a Clos network
2 FPGAs can be used as interconnect or logic
Contact: Pak K. Chan
Computer Engineering Board
225 Applied Sciences
University of California
Santa Cruz, CA 95064
Email: pak@cse.ucsc.edu
Notes: 100 boards made by Xilinx and distributed
for educational purposes.
FPGAs are socketed and can be replaced by
any 4000 series pc84 part.
System Name: Chameleon
FPGA Devices: 7 Algotronix CAL
External Bus:
Interconnect: Fixed mesh
Contact: Cuno Pfister
pfister@cs.inf.ethz.ch
Notes: Experimental workstation from ETH Zurich with FPGA's
closely coupled to MIPS R3000 processor and innovative
object based design software written in the Oberon
language.
System name: CHAMP (Configurable Hardware Algorithm
Mappable Processor)
FPGA Devices: 16 Xilinx 4013
On-board RAM: 512K Dual-ported
External bus: VME
Interconnect: Crossbar (using FPGAs)
Contact: Brian Box
Lockheed Sanders
NCA01-2244
P.O Box 868
Nashua, NH 03060
Phone: (603) 885-7487
FAX: (603) 885-9056
Email: box@nhquax.sanders.lockheed.com
Notes:
System name: CHS 2x4
FPGA Devices: 9 Algotronix CALs (1 controller + 8 compute)
On-board RAM: 2 MB SRAM
External bus: ISA
Interconnect: Fixed mesh
Contact: Tom Kean
Xilinx Development Corp.
53 Mortonhall Gate
Edinburgh EH16 6TJ
Phone: 44 31 666 2600ext204
Fax: 44 31 666 0222
Email: tomk@xilinx.com
Notes: Based on work at the University of Edinburgh by
Tom Kean and John Gray. Commercialized by Algotronix.
Algotronix purchased by Xilinx in 1993. System
cascadable to 2 boards. No longer commercially
available.
System name: CM-2X
FPGA Devices: 16 Xilinx 4005
On-board RAM: None
External bus: Fixed
Interconnect: None
Contact: Craig Reese
IDA Supercomputing Research Center
17100 Science Drive
Bowie, MD 20715
Phone: (301) 805-7479
FAX: (301) 805-7602
Phone: cfreese@super.org
Notes: A Connection Machine 2 SIMD machine from
Thinking Machines Corporation with the Weitek
WTL3164 floating point processors replaced
by Xilinx 4005s. De-commissioned 1994.
System name: DSP-56X
FPGA Devices: 1 Xilinx 3042
On-board RAM: 32KW-128KW (shared with DSP56000)
External bus: SBus & Flexible
Interconnect: See notes below.
Contact: Michael C. Peck
President
Berkeley Camera Engineering
3616 Skyline Drive
Hayward, CA 94542-2521
Phone: 510-889-6960
Fax: 510-889-7606
email: mikep@bce.com
Notes: The DSP-56X is an SBus card that contains a
40MHz Motorola 5600x family DSP, a Xilinx 3042, and
memory (32K words or 128K words I believe). The
3042 sits directly on the 56000 bus and can
be accessed from either the 56000 or the SBus.
Some of the Xilinx pins are connected to the
SBus back panel connector.
System name: DTM-1
FPGA Devices: 16 DTM chips
On Board RAM: 32 8K x16 SRAM banks on separate DTM ports,
dual ported to host
External Bus: VME
Interconnect: Packed Exponential Connections (a multi-grid mesh network)
Contact: Worth Kirkman
MITRE Corporation
7525 Colshire Dr.
McLean, VA 22102
Phone: (703)883-7082
FAX: (703)883-6708
Email: kirkman@mitre.org
Notes: Built from custom DTM chips. These devices are custom
RAM-configurable 64x64 arrays of expandable-gate cells,
each pipelined for 2 boolean input evaluations in a
100MHz cycle. 256 I/O pins, each arbitrary direction
with echo-cancellation and programmable parallel<=>
serial sub-sampling - normally run at 1/4 the internal
rate.
System name: EVC (The Engineers Virtual Computer)
FPGA Devices: 1 Xilinx 4010
On-board RAM: Daughter board (see notes)
External bus: SBus
Interconnect: None
Contact: Steve Casselman
Virtual Computer Corporation
Reseda, CA 91335
Phone: (818) 342-8294
FAX: (818) 342-0240
Email: sc@vcc.com
Notes: The EVC is a single FPGA based transformable
computing system. It has a daughter board area
that has 96 user I/O from the 4010. A 2 Meg fast
SRAM daughter board is available now.
System Name: G-800 System
FPGA Devices: Grouped in modules (maximum 16 -- see Notes below)
On-board RAM: See Notes below
External Bus: VESA (VL) Local bus
VESA Media Channel - 100 MB/sec video bus
80 pin connector supports 32 bit devices
Interconnect: Bus Oriented Communication - Virtual Bus
All Interconnect via Xilinx 4010's on G-800
2x32 bit buses and 2x16 bit buses on G-800
Configuration is programmable - Virtual Bus
Contact: bovarga@gigaops.com
2374 Eunice St.
Berkeley, CA. 94708
Notes: Modules have standard form factor and pinout.
All bus lines to G-800 connect via FPGAs.
Up to 16 modules of all types on 1 G-800 board.
Visual Computing Module (VMC)= 2xXC4005; 4MB DRAM
and 80 MIPS DSPS
PGA10MOD = 1 x XC4010, 2MB DRAM, 128K SRAM
PROTOMOD = same as PGA10MOD with pinouts extended
to pads for wirewrap, logic analyzer, etc.
16xVCMs = 32 XC4005's, 2 XC4010's on G-800, 64 MB DRAM
16xPGA10MODs = 16 XC4010's, 2 XC4010's on G-800, and
32 MB DRAM and 2 MB SRAM
XPGAMOD = 4xXC4010, 8 MB DRAM, 512K SRAM (available Oct)
16xXPGAMODs = 32 XC4010's, 2 XC4010's on G-800, and
128 MB DRAM and 8 MB SRAM
System name: GANGLION
FPGA Devices: 24 Xilinx 3090
On-board RAM: 24K PROM
External bus: VME / Datacube MAXbus
Interconnect: Fixed
Contact: Charles Cox
IBM Research Division
Almaden Research Center
San Jose, CA 95120-6099
Notes: Used exclusively for neural networks.
System name: HARP1
FPGA Devices: 1 Xilinx 3195
On-board RAM: 64K SRAM / 4MB DRAM
External bus: 4 x 20Mbit/sec transputer links +
expansion port (spare FPGA pins)
Interconnect: None
Contact: Ian Page
Oxford University Computing Laboratory,
Wolfson Building, Parks Road, Oxford OX1 3QD, U.K.
+44 1865 273853
FAX: +44 1865 273839
EMail : Ian.Page@comlab.ox.ac.uk
Notes: The HARP1 is an industry standard TRAM board (size 6 =
165 x 84mm) containing a 32-bit RISC-style
microprocessor (a T805 transputer) with 4 Mbytes of
dynamic RAM. Two independent banks of 32K x 16-bit
fast static RAM are attached to the Xilinx 3195 Field
Programmable Gate Array. The FPGA has full access to
the microprocessor bus. A 100MHz frequency synthesiser
is used for arbitrary clock generation. An expansion
port is connected to the spare FPGA pins. TRAM
motherboards allow for easy integration into a variety
of host systems, or for connecting multiple HARP boards
together.
For more information see:
http://www.comlab.ox.ac.uk/oucl/people/ian.page.html
System name: Marc-1
FPGA Devices: 25 Xilinx 4005 (18 processing + 5 interconnect +
2 control)
On-board RAM: 6 MB
External bus: SBus
Interconnect: 5 Xilinx 4005
Contact: David M. Lewis
University of Toronto
Department of Electrical Engineering
Toronto, Canada
Email: lewis@eecg.toronto.edu
Notes: Marc-1 consists of two modules. Each module
contains an instructions unit of 3 Xilinx 4005s,
a datapath of 6 Xilinx 4005s, a 256K x 64
instruction memory, a 256K x 32 data memory
and a Weitek 3364. These are connected by an
interconnect module of 5 Xilinx 4005s. Two more
Xilinx 4005s are used to interface to the Sun
Sparc host.
System name: Mushroom
FPGA Devices: 7 Xilinx 3090
On-board RAM: 5Mb 35ns static RAM
External bus: VME (Sun 3/110 as host)
Interconnect: Fixed busses
Contact: Mario Wolczko
now at : Sun Microsystems Labs, Mario.Wolczko@sun.com
or
Ifor Williams
now at: ADC, 100140.2651@CompuServe.COM
Project was based at the University of Manchester,
England, 1987-92.
Notes: See: `Using FPGAs to Prototype New Computer Architectures,'
Ifor Williams, in `FPGAs', Abingdon EE&CS Books,
edited by Will R Moore and Wayne Luk, 1991, pp 373-382.
Mushroom was a prototypical implementation of a
RISC architecture designed to support dynamic
object-oriented languages.
System name: nfXboard
FPGA Devices: 1 Intel NFX780 in 84-pin PLCC
On-board RAM: None
External bus: IBM-PC printer port
Interconnect: None
Contact: XESS Corp.
1-800-549-XESS
devb@vnet.net
Description: The nfXboard is a small 4''x 2'' board containing an
Intel NFX780 FPGA in 84-pin PLCC package.
The nfXboard is programmed using the PLDasm HDL and
Intel's free PLDshell Plus programming environment.
Configuration files are downloaded to the nfXboard
through the PC printer port using the JTAG protocol.
Additional signals from the printer port can be used to
exercise the downloaded design and the results can be
observed using the 7-segment LED on the nfXboard. The
nfXboard can be used stand-alone or it can be mounted in
a protoboard (all 84 pins are made available on two rows
of 42 pins each). Since configuration is done using a
JTAG stream, it is easy to cascade multiple nfXboards to
experiment with larger designs. Inter-FPGA wiring has
to be added manually, however.
A book accompanies the nfXboard:
"FPGA Workout: Beginning Exercises with the Intel
FLEXlogic FPGA". Softcover, 240 pp., 120
illustrations, and index. ISBN 0-9642187-0-4.
This book shows how to use FPGAs to build digital systems
ranging from simple combinational logic up to a 4-bit
microcontroller. All PLDasm examples in the book
can be downloaded into the nfXboard and tested.
System name: nP (The Nano Processor)
FPGA Devices: 2 Xilinx 3090
On-board RAM: 64K SRAM / 1M DRAM
External bus: ISA
Interconnect: Fixed
Contact: National Technology, Inc.
9500 South 500 West Suite #104
Sandy, UT 84070
Phone: (801) 561-0114
FAX: (801) 561-4702
Email: wirthlin@gecko.ee.byu.edu
Notes:
System name: PAM (Programmable Active Memories) (perle-0)
FPGA Devices: 25 Xilinx 3020
On-board RAM: 0.5 MB
External bus: VME
Interconnect: Fixed mesh
Contact: Patrice Bertin
Paris Research Laboratory
Digital Equipment Corporation
85, avenue Victor Hugo
92500 Rueil-Malmaison, France
bertin@prl.dec.com
Notes: Replaced by the DEC PAM perle-1.
System name: PAM (Programmable Active Memories) (PeRLe-1)
FPGA Devices: 24 Xilinx 3090
On-board RAM: 4MB SRAM
External bus: DEC TURBOchannel
Interconnect: Fixed mesh
Contact: Patrice Bertin
Paris Research Laboratory
Digital Equipment Corporation
85, avenue Victor Hugo
92500 Rueil-Malmaison, France
bertin@prl.dec.com
Notes: Set the record for RSA encryption in 1990.
System name: PRISM (Processor Reconfiguration through
Instruction Set Metamorphosis)
FPGA Devices: 4 Xilinx 3090
On-board RAM: None
External bus: 16 bit
Interconnect: None
Contact: Mike Wazlowski or Harvey Silverman
Laboratory for Engineering Man/Machine Systems
Brown University
Providence, RI 02912
{mew,hfs}@lems.brown.edu
Notes: Notable for its use of C as the description language
for the programmable logic.
System name: PRISM-II (Processor Reconfiguration through
Instruction Set Metamorphosis)
FPGA Devices: 3 Xilinx 4010 per processing node
On-board RAM: 128K x 32 per 4010
External bus: 64 bit writes, 32 bit reads, on processor bus
(it's not external)
Interconnect: Inverted tree, or none, application selectable
Contact: Mike Wazlowski or Harvey Silverman
Laboratory for Engineering Man/Machine Systems
Brown University
Providence, RI 02912
{mew,hfs}@lems.brown.edu
Notes: Each PRISM-II board is a node in the Armstrong III
loosely-coupled parallel processor. The host CPU is a
33Mhz AMD Am29050 RISC processor. There are 20 nodes
that are connected by a reconfigurable (of course)
interconnection topology.
System name: R16 and RISC4005
FPGA Devices: 1 Xilinx XC4005
On-board RAM: 64K Words (16 bit words)
External bus: R16 bus, 16 bit addr, 16 bit data,
Synchronous at 20 MHz
Interconnect: Any
Contact: Philip Freidin
Fliptronics
468 S. Frances St,
Sunnyvale, CA 94086
Phone: (408) 737-8060 or at Xilinx (408) 879-5180
email: philip@xilinx.com
Notes: A 16 bit RISC processor that requires 75% of an
XC4005, 16 general registers, 4 stage pipeline,
Target speed is 20 MHz. Can be integrated with
peripherals on 1 FPGA, and ISET can be extended.
System name: Rasa Board
FPGA Devices: 3 Xilinx 4010
On-board RAM: 320K SRAM
External bus: ISA
Interconnect: 2 Aptix FPICs
Contact: Herman Schmit
ECE Department
Carnegie Mellon University
Pittsburgh, PA 15213
Phone: (412) 268-2476
Notes: Integrated with a behavioral synthesis tool which
allows specification of the desired algorithm in
behavioral Verilog or C.
System name: RIPP (Reconfigurable Interconnect Peripheral
Processor)
FPGA Devices: 8 Altera FLEX 81188
On-board RAM: 2 MB SRAM
External bus: ISA
Interconnect: Fixed buses / programmable interconnect
(see Description)
Contact: Nick Tredennick
Altera Corporation
2610 Orchard Parkway
San Jose, CA 95134-2020
Phone: (408) 894-7000
Email: nickt@altera.com
Notes: Up to 8 Altera FLEX 81188 parts, each of which
may be replaced by an ICUBE IQ160 Field Programmable
Interconnect Device (FPID). Devices are grouped
into 4 pairs of 2 devices, each sharing an SRAM
device. Designed by David E. Van den Bout of the
Anyboard project.
System name: SPARXIL
FPGA Devices: 3 Xilinx XC4010s
On-board RAM: 2 256Kx32bit SRAMs for user data
1 128Kx8bit SRAM for on-board configuration cache
External bus: SBus
Interconnect: fixed
Contact: Andreas Koch
Institut f"ur theoretische Informatik
Abteilung Entwurf Integrierter Schaltungen
Gaussstr. 11
D-38106 Braunschweig, Germany
Email: a.koch@tu-bs.de
Notes: See FPL'93 Oxford workshop
System name: SPACE (Scalable Parallel Architecture for
Concurrency Experiments)
FPGA Devices: 16 Algotronix CAL
On-board RAM:
External bus: Custom
Interconnect: Fixed grid
Contact: George Milne
HardLab
Department of Computer Science
University of Strathclyde
Glasgow G1 1XH
Scotland, UK
Notes: Used for physics research.
System name: Spyder
FPGA Devices: 5 Xilinx 4003, 2 Actel A1280
On-board RAM: 128K SRAM plus 2K fast registers
External bus: VME and Sun SBus
Interconnect: Fixed
Contact: Christian Iseli
Logic Systems Laboratory
Swiss Federal Institute of Technology
CH-1015 Lausanne
Switzerland
Email: chris@lslsun.epfl.ch
Notes: A reconfigurable VLIW machine.
System name: Spyder (version 2)
FPGA Devices: 3 Xilinx 4008 (upgradable to 4010),
2 Xilinx 4005, 1 Actel A1280 and
1 Actel A1225
On-board RAM: 128K SRAM plus 4K fast registers
External bus: VME
Interconnect: Fixed
Contact: Christian Iseli
Logic Systems Laboratory
Swiss Federal Institute of Technology
CH-1015 Lausanne
Switzerland
Email: chris@lslsun.epfl.ch
Notes: A reconfigurable VLIW machine. A newer version
of Spyder.
System name: SPLASH
FPGA Devices: 32 Xilinx 3090
On-board RAM: 4 MB SRAM
External bus: VME
Interconnect: Linear array
Contact: Jeffrey M. Arnold
IDA Supercomputing Research Center
17100 Science Drive
Bowie, MD 20715
Phone: (301) 805-7479
FAX: (301) 805-7602
Phone: jma@super.org
Notes: Replaced by SPLASH 2.
System name: SPLASH 2
FPGA Devices: 16 Xilinx 4010
On-board RAM: 8 MB
External bus: Sun SBus
Interconnect: Linear array plus crossbar
Contact: Jeffrey M. Arnold
IDA Supercomputing Research Center
17100 Science Drive
Bowie, MD 20715
Phone: (301) 805-7479
FAX: (301) 805-7602
Phone: jma@super.org
Notes:
System name: The Stack
FPGA Devices: 8 iFX 780
On-board RAM: 4-8x 8kx24 Fast Sram
External bus: Proprietary 16 bit NRZ bus designed for
extensive cabling
Interconnect: 420Mb/s 13/24 bit input bus,
30Mb/s OC bus between all nodes, 600Mb/s memory
Contact: Peter Averkamp
Tech. Univ. of Munich
Physics Dept. E20
James-Franck-Str. 1
D-85748 Garching, Germany
Email: petav@e20.physik.tu-muenchen.de
Notes: Used in conjunction with GHz ECL logic
for on-line data reduction algorithms
in subnanosecond Synchrotron Experiments
System name: TbC-Pamette (PAM - Programmable Active Memories)
FPGA Devices: 1 to 4 Xilinx 40XX in PQ-208 package
Currently supported configurations: 4010 + 4003H
4 x 4010
On-board RAM: Daughter board (see notes)
External bus: DEC TURBOchannel
Interconnect: Fixed mesh 2 x 2 matrix
Contact: Mark Shand
Paris Research Laboratory
Digital Equipment Corporation
85, avenue Victor Hugo
92500 Rueil-Malmaison, France
shand@prl.dec.com
Notes: 128 user I/O to daughter board. Synchronous RAM daughter
board is under development.
Pamette is targeted as a generic I/O adapter with local
compute capability.
System name: TM-1 (Transmogrifier 1)
FPGA Devices: 4 Xilinx 4010
On-board RAM: 4 32Kx9 SRAMs
External bus: custom to SUN workstation
Interconnect: entirely programmable using Aptix AX1024 FPIC
Contact: Jonathan Rose
Dept. of Electrical and Computer Engineering
University of Toronto
6 King's College Road
Toronto, Ontario
Canada M5S 1A1
Email: jayar@eecg.toronto.edu
Notes: Intended more for rapid prototyping of circuits, but
can be used for computing.
System name: VZ80 (Pin compatible replacement for the Zilog Z80 8 bit uP)
FPGA Devices: 2 Xilinx 4013s
On-board RAM: Not applicable
External bus: 40 Pin DIP socket to any Z80 motherboard (ex:TRS-80)
Interconnect: Fixed wire wrapped interconnect
Contact: Gregory Recupero
VAutomation Inc.
71 Spit Brook Rd.
Suite 306
Nashua NH 03060
Email: greg@VAutomation.com
Notes: From synthesizable VHDL model available from VAutomation.
System name: V6502 (Pin compatible replacement for the Rockwell 6502 8 bit uPFPGA Devices: 1 Xilinx 4013
On-board RAM: Not applicable
External bus: 40 Pin DIP socket to any 6502 motherboard (ex:AppleII-C)
Interconnect: Fixed wire wrapped interconnect
Contact: Eric Ryherd
VAutomation Inc.
71 Spit Brook Rd.
Suite 306
Nashua NH 03060
Email: eric@VAutomation.com
Notes: From synthesizable VHDL model available from VAutomation.
System name: The Virtual Computer (P-Series)
FPGA Devices: Up to 52 Xilinx 4013
On-board RAM: Up to 8 MB SRAM, 256K dual-ported SRAM
External bus: Bus Independent - Current SBus interface
Interconnect: Up to 24 ICUBE FPID
Contact: Steve Casselman
Virtual Computer Corporation
Reseda, CA 91335
Phone: (818) 342-8294
FAX: (818) 342-0240
Email: sc@vcc.com
Notes: The Virtual Computer P-Series consists of P1,
P2, P3 and P4. The P1 has 14 4013s the P2 26
4013s the P3 40 4013s and the P4 has 52 4013s.
System name: Windchime
FPGA Devices: Actel 1020A (1-3 per processor)
On-board RAM:
External bus:
Interconnect: Mesh connected wormhole routing
Contact: Erik Brunvand
CS Dept.
University of Utah
Salt Lake City, UT, 84112
Email: elb@cs.utah.edu
Phone: (801)581-4345
FAX: (801)581-5843
Notes: MIMD multiprocessor. Used for
self-timed circuit experimentation.
System name: X-12
FPGA Devices: 12 Xilinx 3195
On-board RAM: 384K SRAM (32K per FPGA)
External bus: ISA
Interconnect: Fixed common bus
Contact: National Technology, Inc.
9500 South 500 West Suite #104
Sandy, UT 84070
Phone: (801) 561-0114
FAX: (801) 561-4702
Email: wirthlin@gecko.ee.byu.edu
Notes:
Article: 270In article umisef@yoyo.cc.monash.edu.au (Bernd Meyer) writes: >Hello, > >I discovered today that my university doesn't have any >documentation on the XNF file format. This is a serious >problem for me, as I have a design with app. 400 CLBs >which I would like to translate directly into an XNF file... > >I have seen that some translators exist on the net, so there >must *be* documentation. Can anybody help me with this >problem, maybe point me at the right spot? > >Thanks in advance > > Bernd Have you checked with Xilinx? I don't know if Xilinx considers their .XNF file format (which is entirely ASCII text) proprietary or not. If not, then they should be happy to provide you with a format definition doc. If they consider it proprietary so as to protect it from *others'* enhancements (e.g. the PC-ISA bus), then they should be happy to give you a copy after you sign a non-disclosure agreement. If they consider it proprietary in the sense of *trade secret*, then you have to sign a non-disclosure agreement or be a big-bucks customer or both; or you can just decipher the "language" yourself and learn from the error messages you get from the "other tools". This isn't the first time this request has surfaced in a newsgroup posting. I don't speak for Xilinx, these are just my uninformed opinions. Anyone from Xilinx listening to this newsgroup and care to comment? Bob Elkind, Tektronix TV ProductsArticle: 271
In article <36vrdm$57@dartvax.dartmouth.edu>, jeff_cunningham@fostex.com (Jeff Cunningham) writes: |> Does anyone know if there are ORCA design tools for Mentor and if yes |> how good they are? |> |> -Jeff. NeoCAD has a design kit for Mentor Graphics. Using them you can target ORCA as well as other devices. best regards, Todd Selden Technical Advisory Group Mentor GraphicsArticle: 272
In article 704@foghorn.cc.utexas.edu, guccione@foghorn.cc.utexas.edu (Steve Guccione) writes: > > List of FPGA-based Computing Machines > > System name: Anyboard > FPGA Devices: 5 Xilinx 3042 > On-board RAM: 384K > External bus: ISA > Interconnect: Fixed buses > Contact: David E. Van den Bout > ECE Department > North Carolina State University > Raleigh, NC 27695-7911 > Dave - are you out there? Who is the contact at NCSU now? --- ~ Bill Wolf, Raleigh NC ~ I can see ~ ~ wolf@aur.alcatel.com ~ the fog ~ ~ My opinions, NOT my employer's ~ at the end of the tunnel ~Article: 273
Xilinx is reasonable about the XNF format, I obtained a set of docs about 2 years ago while investigating a possible conversion product. They did require a NDA but it was reasonable and the whole processthing was done in a few weeks. The format is taright fowared, a few sample design into .xnf should reval most of what you might want to know. Not sure why you need the format ot get to .xnf, the tools they furnish go back and forth between .lca .mao and ,xnf failry well. Depending on your design you migh end up with "gates" or clb blocks or both in the xnf created form the .lca. What is NOT at all posible is to go from a "bitsream" or prom format to xnf, the actuall bitstream format that programs each switch is considered very proprietary to Xlinx and is not released. At best even if you could do this conversion you would get a very confusing .lca since ALL of the inputs on ALL of the block are connected to somthing during the "tie" process. The other reason Xilinx does not release the bitstream format is to help protect their custumers, if you could go bitstream to .lca na dback it would be easier to disguise blatent coying of a design. Pardon the typos, decided to type this online where I do not know the editor (In oprior line make that .MAP not .MAO. ) Martin Moeller mmoeller@delphi.com We do Video and Xilinx.Article: 274
In article <37ak0u$h10@harbinger.cc.monash.edu.au> umisef@yoyo.cc.monash.edu.au (Bernd Meyer) writes: >Hello, > >I discovered today that my university doesn't have any >documentation on the XNF file format. This is a serious >problem for me, as I have a design with app. 400 CLBs >which I would like to translate directly into an XNF file... The xnf format reference document is available from Xilinx, after signing an NDA. The format is ASCII, and unless you are trying to do something really weird, reading some existing xnf would make it fairly obvious what the format is for most things. Usually the only people that really need the spec are people who are writing net-list translators from schematic capture or synthesis to xnf, or are taking the placed-and- routed design and backannotating the timing information back into their simulation environment. Could you please elaborate on why you need the spec. I may be able to help you without you needing to get the spec. > >I have seen that some translators exist on the net, so there >must *be* documentation. Can anybody help me with this >problem, maybe point me at the right spot? See above for offer of help > >Thanks in advance > > Bernd The people in the EE dept at Melb.Uni have Xilinx development system, and I would be real surprised if there werent some somewhere at Monash. To track them down, you might want to call Stan Sacks at ACD and he should know who at Monash have copies (of the software, not the xnf spec). All the best Philip
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