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In a previous article bwanga@cats.uc*sc.edu (Timothy A. Seufert) writes: : ;In article <3346C531.335B@emf.net>, blt@emf.net wrote: : ;>The Xilinx FPGAs use 13 serial-programming pins: m0, m1, m2, cclk, :>pgm,done,din,dout,init,tdi,tck,tms,tdo. It is worse if you want to ;>load parallel. : ;tdi, tck, tms, and tdo sound like JTAG test port pins, not serial :programming pins. ; :Dunno about Xilinx, but with Altera's FPGAs the pin count for programming ;pins isn't too bad, because you can re-use most of the parallel pins as :I/O after initialization. ; :But I do agree that it would be nice to have an FPGA with a PCI interface ;right on the die. It'd make my life a lot simpler. FYI, Lucent plans to put a hariwired PCI core on one of their future FPGA. We are very excited about it because we do a lot of PCI interfaces in FPGA, and for our need it is not a very easy job.Article: 6026
Jian Shen wrote: > > Hi, VHDL friends: > > I have successfully simulated a 8085 VHDL model in Synopsys. > But when the design_analyzer complained about clock rising > edge specification when synthesizing it. The error msg is: > The use of clock edge specification not supported. > > The design lines are as follows: > ------------------------------------- > elsif (X1 = '1') and (not X1'stable) then -- Begin processing on > --positive edge of clock > CLKOUT <= '0' after 1 ns; > --if bit2int(TSTATES) = 1 then ALE <= '1'; end if; > if TSTATES = "0001" then ALE <= '1'; end if; > ------------------------------------- > > How to model rising edges? Thanks a lot! -- Jian Hi, Instead of using (not X1'stable) use X1'event, so: elsif (X1 = '1') and (X1'event) then .... Best regards, Jaap Mol (jh_mol@signaal.nl)Article: 6027
Austin Franklin (#darkroom@ix.netcom.com#) wrote: : If you are running NT4, I strongly suggest a Dual PPro 200... I moved from : a Pentium 133 on an Asus T2P4, to a Dual PPro 200/256k on a Tyan 1662, and : found my performance almost doubled! CPUs are ~$600, and MB was $350. : : The big advantage of the dual is you can route, and still do other things : without any noticeable degradation. It's real nice...and very stable. However, Max+Plus II doesn't take advantage of the second CPU, so depending on other uses, it may be a waste of money.Article: 6028
Keith Blei (keithb@netventure.com) wrote: : I'm wondering what will reduce compilation time more. Available : memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium. : Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized. : Compilation currently takes around an hour. : : Considering, Pentium Pro 200 and 64 MB. : Anybody have any practical experience in this area? PPro should give you about 2.5x speedup, but according to my experience, RAM is the single most important thing -- you should have enough to eliminate swapping. We're using 10K100 and according to the report file sometimes it uses almost 100 meg of memory. According to my monitor (OS!), the memory usage is about 50 - 100% larger. Since I got 512 meg, that's not an issue. --- Reply-To: and From: fields have been altered to avoid spam.Article: 6029
Tom Burgess <Tom_Burgess@bc.sympatico.ca> wrote: >Keith Blei wrote: >> >> I'm wondering what will reduce compilation time more. Available >> memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium. >> Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized. >> Compilation currently takes around an hour. >> >> Considering, Pentium Pro 200 and 64 MB. >> Anybody have any practical experience in this area? >> TIA, >> Keith > >Doubling the CPU clock rate, along with improved CPU, cache, and bus >architecture will have a much more noticeable effect than marginally >increasing RAM. I found that my Xilinx compilation speeds approximately >tripled between each change from 386-25 to 486DX2-50 to P133. >Adding RAM had little effect, other than increasing maximum design size. >Since the PPro is less of a jump, I doubt that you can hope for double >speed, but plan for at least 1.5x and probably better. >Or best just get a PP200 machine for short-term evaluation - this is not >at all difficult, if you are willing to spend the time to set it up and >deal with the paperwork. Computer sellers do this all the time, and are >used to dealing with rejection: "Well, the beige case clashes with my >Jimi Hendrix poster". "The windows pop up too quick" - O.K. > > regards, tom Tom, Thanks for the feedback. I suspect memory will *REALLY* matter if the design demands more than you have as the swapping will kill you. Anybody else out there got experience with any of this? Thanks again, KeithArticle: 6030
Keith Blei wrote: > > I'm wondering what will reduce compilation time more. Available > memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium. > Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized. > Compilation currently takes around an hour. > > Considering, Pentium Pro 200 and 64 MB. > Anybody have any practical experience in this area? > TIA, > Keith FWIW, 10K20 filled to 90% from VHDL source to placed, routed and timing-back-annotated VHDL takes about 10 minutes on a PPRO200, 128MB, NT4. Given the price of RAM and processors at the moment, neitehr is likely to break the bank. (and twin PPRO boards look _very_ tempting, my old twin P90 board was pleasant, as a compile was genuinely background, with the foreground being almost unaffected) I could try running 4 instantiations of my VHDL to try filling a 10K70, but I'm not sure how representative that'd be of your problem. I note that the 10K 'auto-implement-in-EAB' option in the fitter makes some bad choices, very, very slowly. Have you turned it on by mistake? (it sounds like not, but be warned) hope that helps a bit, SteveArticle: 6031
Brad Taylor wrote: > > - ability to be reprogrammed from the PCI bus along with the normal > > programming methods > > This is extremely painful to deal with, when the interface is all in > FPGA logic. Think about it. If you want to to reprogram the FPGA on > the PCI, what are you going to do? I mean the bus interface disappears > as soon as you begin to program it. By the way, you can hang only > 1 load on each PCI bus pin. The PCI part could catch one or two of the I/O addresses, allowing to reprogram the FPGA part. All the other I/O addresses will go to the FPGA. PCI I/O isn't trivial (relocatible I/O and all that stuff), but standardized. Most of the work is done in the PCI part, anyway, so why not add a reprogramming feature? The PCI special cycles could be used to enable this feature (e.g. shutdown), if you don't want to waste a I/O address for reprogramming in normal operation. I think it's a good idea and speeds up developement (no reset, no reboot to reload the FPGA part). A driver update could load new logic, and enhance speed or functionality, too. -- Bernd Paysan "Late answers are wrong answers!" http://www.informatik.tu-muenchen.de/~paysan/Article: 6032
> : If you are running NT4, I strongly suggest a Dual PPro 200... I moved from > : a Pentium 133 on an Asus T2P4, to a Dual PPro 200/256k on a Tyan 1662, and > : found my performance almost doubled! CPUs are ~$600, and MB was $350. > : > : The big advantage of the dual is you can route, and still do other things > : without any noticeable degradation. It's real nice...and very stable. > > However, Max+Plus II doesn't take advantage of the second CPU, so > depending on other uses, it may be a waste of money. May be I didn't state my point clearly enough... Since the router currently will run only on one CPU, and takes up %100 of that CPUs resources for quite a long time, if you want to do anything else, like Excel, Word, Web Browsing, E-Mail, or any other application, this 'second' application will benefit greatly by the second CPU. AustinArticle: 6033
Timothy A. Seufert (bwanga@cats.uc*sc.edu) wrote: : Dunno about Xilinx, but with Altera's FPGAs the pin count for programming : pins isn't too bad, because you can re-use most of the parallel pins as : I/O after initialization. : But I do agree that it would be nice to have an FPGA with a PCI interface : right on the die. It'd make my life a lot simpler. We're using the AMCC : chip on the board I'm working on, because we'd like to be able to program : the Altera 10K FPGAs from the PCI host computer. That means we need both : the AMCC chip and an EPROM-based PLD to write data from the AMCC into the : 10K configuration port. We've got too many chips going into the board as : is, and it would be very useful to eliminate the PLD and the AMCC chip at : one stroke. Not to argue that an FPGA with PCI built in would be nice, - it is possible to load up an Altera 8K (and presumably 10K) from a PLX9060 without using an EPROM-based PLD. You can share the PLX serial EEPROM clock & data pins with the Altera passive serial load mode, and use the PLX user out pin to init the FPGA. No extra chips needed. Graeme Gill.Article: 6034
I am trying to use fpga as FFT processor... Where can I find the relative documents about this?Article: 6035
keithb@netventure.com (Keith Blei) wrote: >I'm wondering what will reduce compilation time more. Available >memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium. >Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized. >Compilation currently takes around an hour. > >Considering, Pentium Pro 200 and 64 MB. >Anybody have any practical experience in this area? >TIA, >Keith > Whatever processor you settle on go for a Dual motherboard. If your budget is huge go for dual PP200. If you are a bit more limited go for a single PP200 on a dual motherboard and add the second processor later. If you are limited and your boss will only open his wallet once (i.e. no chance to add a second processor later) go for dual P166MMX. This will give you a lot more usable system than a single PP200 for about the same money. I guess you get the idea by now :-) Even though your router will only use one processor it will run much faster on a dual system. I currently have 118 threads running on my system with just 4 apps open. If I start a compile (and had my second processor fitted) most of those would get moved onto one CPU. The compiler thread would have a whole CPU to itself, it doesn't even have to share with the operating system. As for RAM, get as much as you need to eliminate paging. Build the system, bung in 64 megs, run a build and see what it uses. If your budget runs to 128 from day one, it'll do no harm and I'd guess it'll be used on your 10K50 never mind the '70. Good luck JulianArticle: 6036
I have also evaluated the Motorola FPGA devices. I found that the fine grain architecture worked will using Synopsys for synthesizing. My testing of the devices was about 1 year ago. I got several designs working with the devices MPA1064. The biggest problem I had with the devices was routing resources. With the fine grain architecture you will have to trade off some routing resources. I also found that since Motorola had yet developed a serial program cable, we developed a simple parallel port programmer. It is easy to develop one using the data book as a guide to get the programming algorithm. Andreas Kugel <akugel@t-online.de> wrote in article <33448C9F.3B91@t-online.de>... > Sorry to come to this topic again, but - > > Motorola offers a FREE place&route tools for the > 2 smallest members of their FPGA family: MPA1016, MPA1036 > which claim a complexity of 3k and 8k gates respectively. > > After a very long "journey" I managed to get hold of some > chips and a small testboard (ISA-bus + external prototyping card) > will be ready within a few weeks. > > Motorola doesn't supply frontend tools but it is very simple to > create the netlist manually, by a generator program, or from > a schemtaic with EDIF output capabilities. > I choose the schematic way with Ulticap as a front end. > > In order to get these devices a litte better known in the FPGA > communitiy I'd like to share the experiences I now have > and maybe find some people willing to join a sort of > "FPGAs for all" workgroup. > > Feel free to cantact me or visit http://home.t-online.de/home/akugel > > > MPA infos can be found at : > http://design-net.com/fpga/fpga.html > > > Andreas > > -- > Andreas Kugel, Karolinenstr. 4 > 76135 Karlsruhe, Germany > Phone: (49) 721 377865, Fax (49) 721 937 49 12 > E-mail: akugel@t-online.de >Article: 6037
> Altera passive serial load mode, and use > the PLX user out pin to init the FPGA. No extra chips needed. Isn't that two chips? If you did the PCI interface in the FPGA, then that would be one chip? Austin Franklin ..darkroom@ix.netcom.com.Article: 6038
Deadline: May 1st
Call For Papers: FPGA
IEEE Design and Test of Computers
Special Issue
Spring 1998, Volume 15, Number 1
Web Page: http://www.cs.tamu.edu/faculty/lombardi/datsi.htm
IEEE Design and Test of Computers seeks original manuscripts for a
theme issue on Field Programmable Gate Arrays (FPGAs) scheduled to
appear in the first issue of 1998. Articles concerning applied
research and practical experience reports are solicited. The topics
of interest include, but are not limited to:
FPGA Fabrication and Technology. Manufacturing, process control,
yield enhancement, and novel architectures for and device
technology to support field programmable chips.
Exploitation of Field Programmability. Configurable computer
architectures, rapid prototyping, programmable interconnect
architectures, field configurable memories, programmable I/O
systems, and novel implementations.
Reliable Online Implementations. Online testing, built-in
self-test, concurrent testing, design for rapid testability,
latency reduction, fault containment, verification of
reprogramming, online reconfiguration approaches, and design for
reconfigurability.
Synthesis Approaches and Tools. Partitioning, logic minimization
and technology mapping, placement and routing, test generation,
verification of synthesis, and design for synthesizability.
Submitted articles must not have been previously published or
currently submitted for publication elsewhere. Authors should submit
their original work to the guest editor by May 1, 1997, formatted
according to the instructions below. Notification of acceptance will
be sent September 1, 1997. Camera-ready copy for accepted papers will
be due November 1, 1997.
Submit articles by May 1, 1997 to:
Prof. Fabrizio Lombardi, Guest Editor
Department of Computer Science Phone: (409) 845--5464
Texas A & M University Fax: (409) 847--8578
College Station TX 77843-3112 E-Mail: lombardi@cs.tamu.edu
Important dates:
May 1, 1997: Submission deadline
September 1, 1997: Authors notified of acceptance
with requested revisions
November 1, 1997: Final copy due to Design & Test Managing Editor
Spring 1998: Publication in IEEE Design and Test of Computers
Submission requirements:
Send six (6) copies of the manuscript, in English, to the guest
editor. Manuscripts are not to exceed 35 double-spaced pages,
inclusive of figures and tables, in A4 or 8.5 by 11 inches. Type size
must be at least 12 point. Each copy of the manuscript must contain a
cover page with author contact information (name, postal address,
telephone number, and e-mail address) and a 100-word abstract.
Manuscripts must be cleared for publication. Accepted manuscripts
will be edited for technical content, structure, style, clarity, and
grammar. Detailed information for authors can be found at the Computer
Society D&T website at http://www.computer.org/pubs/d&t/d&t.htm or in
the Spring 1996 issue of Design & Test.
Article: 6039Graeme Gill wrote: > > ... > > Not to argue that an FPGA with PCI built in would be nice, - it is > possible to load up an Altera 8K (and presumably 10K) from a PLX9060 > without using an EPROM-based PLD. You can share the PLX serial EEPROM > clock & data pins with the Altera passive serial load mode, and use > the PLX user out pin to init the FPGA. No extra chips needed. > > Graeme Gill. TNX a lot, I was just looking for this possibility. There SEEMS to be another way: Connect the JTAG pins of a FLEX 10k device to the PCI-connector and figure out how to pump configuration data into these lines on the motherboard side. Anyone got an idea? Alfred Fuchs Siemens PSE EZE TNT -- My little grey cells speak for themselves, not for my company. But have a look at http://www.siemens.at, .de or .comArticle: 6040
Here are a couple of recommendations: For Xilinx, check out the DSP section on their Web site at 'http://www.xilinx.com/apps/dsplit.htm'. There is a paper there called "The Fastest FFT in the West" which is a downloadable Acrobat file 'http://www.xilinx.com/appnotes/fft.pdf'. An abstract from their Web site is listed below: "This paper discusses that the incorporation of a large FFT in a single FPGA, while noteworthy, may evoke a "so what" response. Its speed will be compared to the more standard single-chip DSP design. We propose to compare Xilinx FPGA performance with an exhaustive list of DSP devices. The test benchmark, established in 1995, is the execution time of a 256-point FFT. The speed in the FPGA design is set by the computation time of the radix 2 butterfly. For 16-bit data and a 50 MHz system clock the computation time indicated is 320 ns. The number of butterfly computations ((N/2)log2N) for a 256-point FFT is: (256/2)log2 256 = 128 x 8 = 1024 " For Altera, I've come across a couple of papers including: Fast Fourier Transform Data Sheet: 'http://www.altera.com/document/ds/dsfft_01.pdf' Fast Fourier Transform Megafunction: 'http://www.altera.com/document/sb/sb12_01.pdf' -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Chyr-Pyng Su <cpsu@slider> wrote in article <5ia9ru$l76@news.cis.nctu.edu.tw>... | I am trying to use fpga as FFT processor... | Where can I find the relative documents about this? | | |Article: 6041
keithb@netventure.com (Keith Blei) wrote:
>I'm wondering what will reduce compilation time more. Available
>memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium.
>Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized.
>Compilation currently takes around an hour.
>
>Considering, Pentium Pro 200 and 64 MB.
>Anybody have any practical experience in this area?
>TIA,
>Keith
>
>
>
If you lookat the end of the report file generated by the compile it
will tell you how much memory it used. There is also a goide in the
book that gives recommended RAM for different size parts. I'm doing a
10K20 and they recomment 64meg.
Also, look in the readme.hlp file. There is a section there that
explains it quite well.
Regards,
Aaron Quantz \^ ^/
)@ @(
+---------------------------oOO--(_)------------------------------------+
+ Mgr Software Development, Turret Control Systems +
+ HR Textron | Phone: (805) 253-5471 +
+ 25200 W. Rye Canyon Rd. | Fax: (805) 253-5962 +
+ Valencia, CA USA 91355-1265 | Email: aquantz@ibm.net +
+ Visit the Textron web site: http://www.textron.com +
+-----------------------------------Oooo--oOO---------------------------+
oooO ( )
( ) ) /
\ ( (_/
\_)
Article: 6042Peter Alfke wrote: > Saliva is mostly water and therefore boils ans sizzles at 100 degrees C. ( Saliva contains some minerals too (NaCl), which lower the temperature at which the water boils by a few degrees (that's also how you can get boiling water below 100 C - just add salt). My $0.02 CAN Martin. -- | Martin d'Anjou | tel: (613) 765-3058 | | Nortel | fax: (613) 763-9535 | | P.O. Box 3511, Station C | email: mdanjou@nortel.ca | | Ottawa, Ontario, CANADA K1Y 4H7| My opinions, not Nortel's | | http://www.nortel.com/ | Mes opinions, pas celles de Nortel|Article: 6043
I am with Human Resources for the Small Internetworks Business Unit (formerly Grand Junction) at Cisco Systems. We develop switches, routers, and hubs that focus on small and medium-sized companies. Revenue-wise we are the fastest growing Business Unit at Cisco Systems with 30+% growth over the last five quarters. We are currently looking for senior and intermediate ASIC Engineers (digital) as well as senior and intermediate Systems Engineers (embedded CPU, FPGA) to join our team. We are located in San Jose, California. If you, or anyone you know is interested, please contact me or send me your resume. I will be happy to talk with you further about the positions. To send your resume: fax: 408-527-8048 or email: lshevock@cisco.com No agencies please -- To send your resume: fax: 527-0180 or email: lshevock@cisco.com No agencies pleaseArticle: 6044
There is an interesting behavioral compiler for FSM synthesis called WaveScript (TM) Compiler. It compiles WaveScript text file and generates synthesizable RTL code (Verilog now). WaveScript is a waveform based visual scripting language that enables designers to describe the synchronous i/o behavior of any sequential control functions. WaveScript Compiler can perform automatic state-assignment in various styles (full-encode to one-hot). WaveScript Compiler is available on Sun-Solaris (Sparcstations or PC), Windows-NT, and Windows95. For more information, please contact: ETI PO BOX 2878 Cupertino, CA 95015-2878 or Email: clementw@msn.comArticle: 6045
testArticle: 6046
wen-king@myri.com (Wen-King Su) wrote:
:In a previous article bwanga@cats.uc*sc.edu (Timothy A. Seufert) writes:
::
:;In article <3346C531.335B@emf.net>, blt@emf.net wrote:
::
:;>The Xilinx FPGAs use 13 serial-programming pins: m0, m1, m2, cclk,
::>pgm,done,din,dout,init,tdi,tck,tms,tdo. It is worse if you want to
:;>load parallel.
::
That's a tad unfair to Xilinx :-) The listed pins indeed _may_ have a
programming function, but that's not mandatory. Let's assume we don't
have an 8-bit parallel data bus in this case (if we had, just use that
for programming). Listing the pins, and their functions:
Programming In use
M0 Select mode Input
M1 " Output
M2 " Input
CCLK Clock Readback clock
PGM Clear memory Probably system reset
DONE Program complete Signal to system
DIN Program data in I/O
DOUT Daisy chain out I/O
INIT May be left high I/O
TDI JTAG I/O
TMS " I/O
TCK " I/O
TDO " O
Only CCLK is absolutely useless in the running system. Of the others,
DONE can be used to enable the external circuits once the FPGA is
programmed, and PGM may thought of as power-on reset. DIN will be the
serial program data, but can be mux-ed (use DONE to switch it) to be
an input in the running system.
The M0 & M2 inputs need to be held at the right levels (use DONE
again) during programming, but are freely useable thereafter.
If you are not using the JTAG feature, its pins are all available for
use.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or servers
"From" line rigged to foil spambots: daveb <at> iinet.net.au
Article: 6047Peter Alfke wrote: > > I will soon publish here a way to use one of the input protection diodes > to measure chip temperature more exactly. > Cool! Would LOVE to see this. Curious if ground bounce creates measurement problems (by shifting average ground) and if so would it help to do a differential measurement using a nearby zero-level output as a reference. The chips needing temperature measurement will be typically (always) embedded in noisy digital environments. But the accuracy requirements are not high. regards, tomArticle: 6048
keithb@netventure.com (Keith Blei) wrote: >I'm wondering what will reduce compilation time more. Available >memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium. >Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized. >Compilation currently takes around an hour. > >Considering, Pentium Pro 200 and 64 MB. >Anybody have any practical experience in this area? >TIA, >Keith It turns out Altera uses lots of 200 MHz Pentium Pro's and 128 MB is not uncommon there. Quite a "reference" platform eh<g>? With the rate at which this stuff becomes junk, I'm going with PP200, Intel Venus and 96MB. Looks like Intel wants us all to go to NT/PPro and the consumer market to MMX pentiums. Thanks for all the good advice. KeithArticle: 6049
I'm doing some comparison shopping/measuring for various FPGA products vs. synthesis tools. I'm looking for information along the lines of: Xilinx XC9885 28 instances of Prep#1 with Synario v9.99 Altera Flex 2940 39 instances of Prep#1 with Synario v9.99 Lucent Orca 4c99 32 instances of Prep#1 with Synario v9.99 Xilinx XC9885 52 instances of Prep#1 with VHDL4u v0.01 Altera Flex 2940 31 instances of Prep#1 with VHDL4u v0.01 Lucent Orca 4c99 40 instances of Prep#1 with VHDL4u v0.01 For the moment, I'm interested in SRAM FPGAs rather than OTP or EE devices. All the product names and "figures" above are bogus, of course; but this should illustrate that for which I am searching (I'm typing and watching my prepositions at the same time). Any pointers? Thanks, kindly. All help and guidance and advice is cheerfully and gratefully accepted! Bob Elkind **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****
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