Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Ray Andraka wrote:
> You can get the structure you need to get the desired performance and
> density using an HDL, but you will likely have to resort to low level
> instantiation and a host of extra attributes to control placement.
> Effectively, this is writing a textual description of the schematic.
> The current HDL synthesis tools really don't provide enough control over
> the design implementation to quickly, reliably and successfully turn out
> high performance designs. Hopefully the CAE vendors will fix this soon,
> but I am not holding my breath.
>
This is all too true. The situation is a lot better than 5 years ago, but
thereis a lot of improvement needed. Synthesis tools are only slightly smarter
than a fresh graduate who's never done a real design. On the other hand,
a good VHDL-93 compiler in the hands of somebody who knows the
limitations of the tool and how to get around them can be real dynamite
in FPGA design.
<several paragraphs clipped>gwash. Here are a few of the moreent all seem to
imply tha
> As you can see, (and many of you already know this) I am not a big fan
> of HDLs at the current time, mostly because the control over the
> implementation in the current tools is not as complete or as intuitive
> as those controls applied in schematic entry. Give me that control, and
> I think the two real advantages stated above would tip the balance in
> favor of HDLs. For now, however, I can get to the desired performance
> and logic density faster using schematic entry, and since I get paid to
> get a working design, that means I either earn more money by doing more
> designs or have a little extra time to devote to my wife and kids or to
> flying (which is where the extra money part comes in).
>
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
Well Ray, I agree that control is the name of the game. I've pretty much
given up on writing behavioral VHDL because it sacrifices too much control.
It's ok in a very limited context where the resulting logic occupies 1 or 2
LUT's,
but register synthesis is often a disaster when you have complex register
libraries.
My solution is what I call "SuperStructural" VHDL, which is heavily parameterized
LPM style components that use lots of technology specific gate instantiation.
This
is essentially textural schematics, with the added bonus that I can use the
elaboration phase of the compile to perform lots of really neat design
computation
that eliminates the need for external C programs to calculate constants & such.
It's portable VHDL in theory, but not likely to work well on any FPGA
architecture
other than the target it was designed for. Unlike behavioral VHDL, I *can* do
floorplanning with my VHDL libraries. The test code shown below creates a 3600
element shift register and floorplans every flop into a serpentine array on a
2C40A ORCA
device. It works, I've done it. I stopped drawing schematics 2 years ago
because it
was a lot slower than writing VHDL. Doing this design with a schematic would
be
a perfect nightmare of component plopping and attribute attachment.
John McCluskey
Lucent Technologies
J.McCluskey@ieee.org
Libraries shown below are available at http://www.cam.org/~jqm
---------------Finally, we have a test entity for "orca_ff.vhd"--------------
-- This simple test case builds a 3600 bit shift register as an 30x30 block of
-- PFU sites with the upper left corner located at Row 1, Column 1
LIBRARY ieee;
use ieee.std_logic_1164.all;
use work.orca_loc.all;
use work.orca_ff.all;
entity test is
generic (width: integer := 3600 );
port ( clk: IN std_logic;
data_in: in std_logic;
data_out: OUT std_logic
);
end test;
architecture orca of test is
constant loc_vec: cell_loc_vec(0 to width-1)
:= mk_blk(1,1,30,width,right,down,do_pack)(0 to width-1);
signal tbus: std_logic_vector(width-1 downto 0);
begin
d1: dff_std generic map(location => loc_vec )
port map(D => (data_in & tbus(width-1 downto 1)), clk => clk, Q => tbus );
data_out <= tbus(0);
end orca;
Article: 8851Magnus Homann wrote: > Hi, > > I'm just curious of how big a step there is from FPGA to ASIC? I design using VHDL and find that there is practicaly no difference. > I > cnostatntly hear that ASIC is so much harder, but is that just to > protect the ASIC-designers postions? Perhaps. I guess it depends on the design flow you use. I prefer designingfor ASICs because I don't have to buy the vendor's place & route tools and many fabs take the gate level netlist as sign-off as well as nice portable VHDL testbenches for pre and post layout simulation and verification. ASIC design get's difficult for under .5um and when you are trying to achieve zillion bps performance because of the innacuracy of pre-layout timing estimates. > I can accept that there is some added difficulty, but how hard can it > really be? After doing a few FPGA designs (1-3) and taking a week > course in ASIC design, would I be ready? Probably. I guess that depends on you :)rgds, Sam Falaki (remove nospam from email address to email) > Homann > -- > Magnus Homann Email: d0asta@dtek.chalmers.se > URL : http://www.dtek.chalmers.se/DCIG/d0asta.html > The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.htmlArticle: 8852
ASICs require test vectors (e.g. you have to test a new ASIC out of the oven on the vendor's tester, whereas your FPGA is already tested). Creating the test vectors is tricky, plus you gotta make up schemes to do the tests (e.g. JTAG for example, Memory BIST). Plus, you usually have to do lots more analysis so you get it right, e.g. Static Timing Analysis (e.g. MOTIVE). Just a much higher 'level of care'. So, I don't think its the VHDL/Verilog digital design that's so different, just the extra handling demanded by ASICs. A mistake costs $100,000 and months of delay, versus just trying out another place & route on the lab! Thomas A. Coonan Thomas.Coonan@Sciatl.com >Magnus Homann wrote: > >> Hi, >> >> I'm just curious of how big a step there is from FPGA to ASIC? > >I design using VHDL and find that there is practicaly no difference. > >> I >> cnostatntly hear that ASIC is so much harder, but is that just to >> protect the ASIC-designers postions? > >Perhaps. I guess it depends on the design flow you use. I prefer >designingfor ASICs because I don't have to buy the vendor's place & route >tools and >many fabs take the gate level netlist as sign-off as well as nice portable >VHDL >testbenches for pre and post layout simulation and verification. ASIC >design get's >difficult for under .5um and when you are trying to achieve zillion bps >performance >because of the innacuracy of pre-layout timing estimates. > >> I can accept that there is some added difficulty, but how hard can it >> really be? After doing a few FPGA designs (1-3) and taking a week >> course in ASIC design, would I be ready? > >Probably. I guess that depends on you :)rgds, > >Sam Falaki >(remove nospam from email address to email) > >> Homann >> -- >> Magnus Homann Email: d0asta@dtek.chalmers.se >> URL : http://www.dtek.chalmers.se/DCIG/d0asta.html >> The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html > > >Article: 8853
hi, does anyone have vectors which define ISA bus timings which they can share ? Is there any tool out there which would generate memory and IO access vectors from an ISA bus slot ? I am trying to write a test bench for verilog to test a small FPGA design for an ISA slot. thanks muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 8854
Ray Andraka wrote: > > Johannes Sølhusvik wrote: > > > > Can anyone guide me with the design of a 3-staged pipelined multiplier > > in VHDL that is optimised for Xilinx 4000XL series ? > > > > -- > > Johannes Sølhusvik, PhD, Electronic Systems > > ABB Corporate Research Centre, Norway > > Tel: +47 66 84 34 28, Email: jso@nocrc.abb.no > > How many bits and what's the clock rate? Makes a big difference in the > best implementation, and the level of instantiation required. 7x10 bits signed, clock rate = 18 MHz -- Johannes Sølhusvik, PhD, Electronic Systems ABB Corporate Research Centre, Norway Tel: +47 66 84 34 28, Email: jso@nocrc.abb.noArticle: 8855
>system and maintain it when the engineer marked it up. and now we have >secretaries that won't answer the phone, won't order supplies, won't type >papers, won't do the mail, won't photocopy, won't fax ... What *do* they do? :) Sounds like I should get a job in your firm. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8856
There are advantages and disadvantages for both ASICs and FPGAs. The main advantages of ASICs are two: cheap sillicon and high speed. An ASIC of the same micron technology will be around 5 times as fast as its equivalent FPGA in terms of gate count. Also it takes about 50 times as many transistors to roughly have the same numbers of resources in an FPGA when compared to an ASIC. However, ASICs are considered extremely unflexible. There is literally no room for human error. That is why typically designers will prototype in FPGAs before they move towards ASICs FPGAs, on the other hand, are fully flexible, specially the ones with SRAM technology such as LUCENT's, Xilinx, Altera's etc. You can reprogram these parts as many million times as you need. But guess what? If you are targetting implementations below 40K gates at speeds of 90Mhz or lower, it is better to stay in FPGAs even when going to high volume. This is occurring because nowadays the sillicon is becoming so small that the price of the packaging has become the price of the component. Check out the Xilinx Spartan parts and you will see. From 40 to 100K gates both Xilinx and Altera offer you a great solution that consists in prototyping in their bigger FPGAs and then moving to ASICs with relative peace of mind. For the time being, when your design goes higher than 150K gates you will have to start with ASICs with other solutions to do prototyping that still involve FPGAs. Expect in one year from now to have 1/2 million gates FPGAs available for high volume production. In article <34d4fd93.591701886@news.mindspring.com>, Thomas A. Coonan <tcoonan@mindspring.com> wrote: >ASICs require test vectors (e.g. you have to test a new ASIC out of >the oven on the vendor's tester, whereas your FPGA is already tested). >Creating the test vectors is tricky, plus you gotta make up schemes to >do the tests (e.g. JTAG for example, Memory BIST). >Plus, you usually have to do lots more analysis so you get it right, >e.g. Static Timing Analysis (e.g. MOTIVE). Just a much higher >'level of care'. So, I don't think its the VHDL/Verilog digital >design that's so different, just the extra handling demanded by ASICs. >A mistake costs $100,000 and months of delay, versus just trying >out another place & route on the lab! > >Thomas A. Coonan >Thomas.Coonan@Sciatl.com > >> >Article: 8857
In order to perform a good estimate on the number of combinatorial
gates that can be implemented in an FPGA, I would like to get a good
idea on the average number of gates that can be put in a look-up table.
Both Altera (in Flex10K) and Xilinx in XC40xx series use look-up tables
with 4 inputs, 1 output.
Could anybody give me a good idea what on the average, the number of
equivalent gates (nand2-equivalents) that can be put in such a table.
Thanks
--
Koenraad SCHELFHOUT
Switching Systems Division http://www.alcatel.com/
Microelectronics Department - VH14 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 47 \ / /
mailto:ksch@sh.bel.alcatel.be \ / /
_____________________________________________\ / /______
\ / /
Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium
Article: 8858
Altera recently migrated the 5000 family to a more advanced technology
(0.65 micron). We are having problems programming these new devices
(EPM5032DC-20) with a code that worked fine before. The entire design is
synchronous and has been working perfectly for the last 5 years. We tried
programming the new devices with Data IO and with BP, but the devices
seem to be work as if they were programmed wrong (verify checks out!).
Does anyone have any ideas and/or experiences with this kind of
phenomena? Altera, themselves, claim that we should try to use their
programming hardware. We're still waiting for it...
Please assist ASAP.
Thanks
Igor.
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 8859A suggestion: check out my article 'Moving beyond programmable logic; if, when, how?' in the November 20, 1997 issue of EDN (www.ednmag.com). Feedback always appreciated.... > >Hi, > >I'm just curious of how big a step there is from FPGA to ASIC? I >cnostatntly hear that ASIC is so much harder, but is that just to >protect the ASIC-designers postions? > >I can accept that there is some added difficulty, but how hard can it >really be? After doing a few FPGA designs (1-3) and taking a week >course in ASIC design, would I be ready? > >Homann Brian Dipert Technical Editor EDN Magazine: The Design Magazine Of The Electronics Industry 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** Visit me at <http://members.aol.com/bdipert>Article: 8860
Magnus Homann wrote: > I'm just curious of how big a step there is from FPGA to ASIC? I > cnostatntly hear that ASIC is so much harder, but is that just to > protect the ASIC-designers postions? > > I can accept that there is some added difficulty, but how hard can it > really be? Here is my ( admittedly biased ) input: Beyond the design effort, there are other big differences: For the ASIC, you or somebody else must develop a custom test program specifically for your design. ASICs are custom circuits and cannot be tested before they are customized. You don't have that problem with an FPGA. You know that the manufacturer has tested that chip thoroughly, throwing a million ( or more ) test vectors at it. And there is economics. You ( or your employer ) must pay for the non-recurring engineering charges that pay for creating the custom mask ( set) and the specialized testing. FPGAs have none of that cost. Then there are more subtle points: Who pays for your mistakes ? Who pays for a mid-life design change? Who pays when you ordered too many of too few parts? And there is a new wrinkle: IC processing is advancing very fast, and FPGAs are at the cutting edge of this progress. Does your ASIC supplier offer 0.25 micron technology? I am just now designing a frequency counter, and the resolution is well above 300 MHz ( worst case ), using an XC4000XL FPGA.Just some thoughts...Peter Alfke, Xilinx ApplicationsArticle: 8861
CALL FOR PARTICIPATION
Configurable Computing: Technology and Applications
Part of SPIE's Internationsl Symposium on
Voice, Video and Data Communications
November 1-6, 1998
Boston, Massachusetts USA
Sponsored by:
SPIE The International Society for Optical Engineering
Held in Cooperation with:
NASA's Technology 2008
This is the third international meeting on high performance computing
using Reconfigurable Logic Devices held at SPIE's International
Symposium.
It will serve as a forum to present current work by researchers from
around the
world as well as highlight activities in the commerical configurable
computing area.
Conference Chair: John Schewel, Virtual Computer Corp.
Cochairs: Peter M. Athanas, Virginia Polytechnic Institute and State
Univ.;
Steven A. Guccione, Xilinx Inc.; Stephan Ludwig, Digital Equipment
Corp.;
John T. McHenry, National Security Agency
Many systems engineers are using reconfigurable device technologies,
such
as Field Programmable Gate Arrays (FPGAs) and Complex programmable Logic
Devices (CPLDs), to overcome computation and product development
bottlenecks. In recent years, these devices have been incorporated into
computing systems for the purpose of providing a reconfigurable
environment
for high-performance applications. This conference focuses on two areas
of
configurable technology:
1) systems, tools and techniques
2) high-performance applications
Today's reconfigurable devices can be used for datapath and data
processing
applications, as well as for general logic replacement. Processors built
from reconfigurable logic devices are being applied to a wide range of
computationally-intensive tasks. For this reason, it is necessary to
spread information about reconfigurable technology beyond the
traditional
users of these devices.
This conference is the first of it's kind outside the FPGA community,
and
it serves as an opportunity to introduce newcomers to this arena. The
conference will present papers that illustrate applications and
techniques
for using reconfigurable technology in both the design cycle and in
production systems. Papers relating to the following areas are
solicited:
* digital and analog reconfigurable components
* programming tools and methodologies for configurable computing systems
* applications and platforms utilizing configurable technology for:
- hardware/software codesign
- rapid product development
- high-performance computing
- image, signal, and communication processing
- intelligent systems, robotics, and evolvable algorithms
Abstracts Due Date: 31 March 1998.
Manuscripts Due Date: 10 August 1998.
Proceedings of this conference will be published and available at the
meeting. The Abstract and Manuscript due dates must be strictly
observed.
Your abstract must include the following:
1. Submit to: VV04, Schewel
2. Abstract Title
3. Author listing (pronciple author first)
First, Last name, Affiliation
Mailing Adress, telephone, fax and email
4. Abstract text (aprox. 250 words)
5. Keywords (list a maxium of five keywords)
6. Brief Biography ( Principle author - 50 words )
Submission Instructions
Please choose only ONE of the following options:
1. SPIE WEB - Complete the form found on SPIE Web site
www.spie.org/forms/pe98_submission_form.html
2. or EMAIL abstarct to: abstracts@spie.org
in ASCII text (not encoded) format. Subject line MUST
include ONLY the following:
SUBJECT: VV04, Schewel
3. or MAIL three copies of your abstarct to:
Voice, Video and Data Communications
SPIE PO Box 10, Bellingham WA 98227-0010 USA
Shipping Address: 1000 20th St. Bellingham WA 98225 USA
Tel. 360/676-3290
4. or FAX one copy to SPIE at 360/647-1445 be sure to
include Attention VV04-Schewel
--
Best Regards,
John Schewel, VP Marketing & Sales
Virtual Computer Corp.
http://www.vcc.com
Article: 8862rk describing *day* job: : >system and maintain it when the engineer marked it up. and now we have : >secretaries that won't answer the phone, won't order supplies, won't type : >papers, won't do the mail, won't photocopy, won't fax ... peter inquisitively asks? : What *do* they do? :) Sounds like I should get a job in your firm. rk responds as appropriate from day job: : no comment. -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 8863
This whole thread of HDL vs schematics reminds me of a question I have been meaning to ask this newsgroup for a while: Do you folks have examples of what you consider excellent examples of VHDL (Verilog) programming style? I am interested in collecting such examples for state machines, random logic, etc. etc. This question is in complete analogy to various programming styles advocated in C, C++ etc. I am also interested in any books that have significant and non-trivial VHDL code that can serve as an example of good VHDL programming. Any suggestions? Thanks HemantArticle: 8864
>-- This simple test case builds a 3600 bit shift register as an 30x30 block of >-- PFU sites with the upper left corner located at Row 1, Column 1 Now, if you really wanted to make a case for HDL, you would have attached the *schematic* also, as a jpeg :) Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8865
Hi, Is there a CardBus core available to any FPGA out there? EhudArticle: 8866
Marco Rivero wrote: > The following is a collection of problems that I have had with not > only > version M1.4.12 (that I'm running now under NT in conjunction with > WVOffice > 7.4) but with several previous versions of XACT. > > 1. When the Viewlogic project data is stored on a Novell Network > drive, the > flow engine fails when trying to run hitop. All Xilinx binaries and > license > file are stored on a local drive. I was told by customer support > (again) to > copy the project onto a local drive and run it, and that Novell "is > not a good > network." This is unacceptable. We're a group of engineers and we > share > information over a network. Are we the only ones running data over a > Novell net? > > I welcome any comments or guidance on how to solve the first or third > "comments" > > Thanks for taking the time to read this, > Marco Rivero Re: Problem 1 We have observed the same problem. A solution which seems to work is described on the xilinx homepage, document <http://www.xilinx.com/techdocs/2950.htm>. The problem is that the software, of any obscure reason, needs access to a drive mapping of the root of the disc. Regards, Jon Vedum, Seem Audio a/sArticle: 8867
jqm@cam.org wrote:
> My solution is what I call "SuperStructural" VHDL, which is heavily
> parameterized LPM style components that use lots of technology
> specific gate instantiation. This is essentially textural schematics,
> ...
Interesting. I guess my schematics could be called "schematicural text".
I implemented your benchmark design as a schematic in under 3 minutes
(including floorplanning). It has the following 4 parts:
Pad-in: Din
Clkpad: Clk
Pad_out: Q0
XFunc: Q[3599:0] := <Din,Q[3599:1]>
And a line in the floorplanning script:
PFU Q%d ($1/4)/30+1 , ($1/4)%30+1
One can see the appeal of HDL, since I couldn't post the schematic
here, but could post a textual description of it in (probably) less
time than it took to draw the schematic. Unfortunately, as shown by
your VHDL example, current languages don't allow such a simplistic
textual description.
Also, I don't think we see the advantages and disadvantages until
we start doing large complicated designs.
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 8868AUM Systems, Inc., based in Central New Jersey, provides systems integration services to companies ranging from midsize to Fortune 500 corporations. We are an innovative company seeking creative individuals to fill many available positions. ============================================================== System Testing & Optimization Immediate Position ... NJ Electrical Design Engineers (RF, Analog, Digital, Frame Electrical) are needed for the development of next generation wireless project involving all aspects of product realization, including design concepts, hardware design/integration, engineering for manufacture, assembly and testing. REQUIREMENTS: --Extensive experience in design, manufacture and test of cost effective, high quality, wireless systems --Detailed knowledge of digital (FPGA, DSP) analog/RF design simulation and test techniques and high speed backplanes --Minimum of BSEE =====================CONTACT INFO:======================= ATTN: Sandra Koziar AUM SYSTEMS, INC. Tel: (732) 225-4050 180 Raritan Center Pkwy., 2 FL Fax: (732) 225-5060 P.O Box 6853 E-mail: staff@aumtech.com Edison, NJ 08818-6853 (ASCII Only) ============================================================== Please include daytime telephone number and earliest start date.Article: 8869
AUM Systems, Inc., based in Central New Jersey, provides systems integration services to companies ranging from midsize to Fortune 500 corporations. We are an innovative company seeking creative individuals to fill many available positions. ============================================================== System Testing & Optimization Immediate Position ... NJ Electrical Design Engineers (RF, Analog, Digital, Frame Electrical) are needed for the development of next generation wireless project involving all aspects of product realization, including design concepts, hardware design/integration, engineering for manufacture, assembly and testing. REQUIREMENTS: --Extensive experience in design, manufacture and test of cost effective, high quality, wireless systems --Detailed knowledge of digital (FPGA, DSP) analog/RF design simulation and test techniques and high speed backplanes --Minimum of BSEE =====================CONTACT INFO:======================= ATTN: Sandra Koziar AUM SYSTEMS, INC. Tel: (732) 225-4050 180 Raritan Center Pkwy., 2 FL Fax: (732) 225-5060 P.O Box 6853 E-mail: staff@aumtech.com Edison, NJ 08818-6853 (ASCII Only) ============================================================== Please include daytime telephone number and earliest start date.Article: 8870
Everyone is saying all the right things. One more point. ASICs demand that you use a certain 'discipline' to verify the design - Static Timing Analysis, test vectors, elaborate simulations. And, of course, FPGAs *can* be developed in a somewhat ad-hoc, "let's pop one and see what happens" approach. Sometimes, there ain't nothin' wrong with taking advantage of FPGAs to experiment and rapid prototype. Hoever, not using all the more disciplined approaches can bite you. Like; it works in the lab, and maybe even works with a hair dryer on it, but is fails in the field under certain temperature conditions, or, your company decides they want to go to an ASIC and you don't have 'real' simulations and test vectors that the ASIC methodology demands. My point is that, some of the more finicky design practices demanded in ASIC design *should* be applied to FPGAs. I know my first digital projects were FPGAs and we winged it in the lab. After a few ASIC projects and FPGA->ASIC conversions, I'm a little more inclined to apply ASIC design practices to FPGAs. blah blah blah. tom coonan Scientific Atlanta Thomas.Coonan@Sciatl.com >Magnus Homann wrote: > >> I'm just curious of how big a step there is from FPGA to ASIC? I >> cnostatntly hear that ASIC is so much harder, but is that just to >> protect the ASIC-designers postions? >> >> I can accept that there is some added difficulty, but how hard can it >> really be? > >Here is my ( admittedly biased ) input: > >Beyond the design effort, there are other big differences: > >For the ASIC, you or somebody else must develop a custom test program >specifically for your design. ASICs are custom circuits and cannot be >tested before they are customized. >You don't have that problem with an FPGA. You know that the manufacturer >has tested that chip thoroughly, throwing a million ( or more ) test >vectors at it. > >And there is economics. You ( or your employer ) must pay for the >non-recurring engineering charges that pay for creating the custom mask >( set) and the specialized testing. >FPGAs have none of that cost. > >Then there are more subtle points: Who pays for your mistakes ? Who pays >for a mid-life design change? Who pays when you ordered too many of too >few parts? > >And there is a new wrinkle: >IC processing is advancing very fast, and FPGAs are at the cutting edge >of this progress. Does your ASIC supplier offer 0.25 micron technology? >I am just now designing a frequency counter, and the resolution is well >above 300 MHz ( worst case ), using an XC4000XL FPGA.Just some >thoughts...Peter Alfke, Xilinx Applications >Article: 8871
Hello everyone, I am a University student looking for information on the web dealing with the hardware aspect of FPGA logic. The main interest of mine is new and technologies to come in this area. If possible please send me addresses of any information in this area. Any help in this matter is greatly appreciated, and I thank you in advance for any help that you can send me. Peter M.Article: 8872
Hi, I am after any experience you have in ways that any of the above packages are better than each other. I'm currently using WVO (schem only, not VHDL - yet!), but due to Xilinx' apparent reduction in support for this package, I am considering the other two packages as I need to (for my own reasons) move to (purchase) any one of them now. Both OE & Fd seem to be more user friendly in several ways (compared to WVO 7.2), eg. the simulation tools. They also seem to have much tighter integration of features than WVO, particularly in interfacing to M1 core tools. Apart from Foundations lack of VHDL simulation support (standard version), they seem on a par, both with their pros & cons. Obviously these packages are at the lower end of the EDA tools market - I just want an idea of your opinion of where these products stand - past, present, & future. Any past reviews of the low end EDA tools would also be of interest. Regards, Stu. --------------------------------------------- Stuart Summerville Project Engineer Practel Surveillance Systems 650 Burwood Road, Hawthorn, Victoria 3122. Tel: (61.3) 9813 3636 Fax: (61.3) 9813 3733 Email: stuart.summerville@surv.practel.com.au ---------------------------------------------Article: 8873
Hi: Does anyone know of a way to combine Altera .sof files, pipe them into maxplus2 and generate an .rbf file. Something like: > cat file1.sof file2.sof ... | maxplus2 (some options) > file.rbf I can do this through the GUI, but would prefer to use a script if possible. Thanks -- ========================================== Jim McGrath : mcgrath@axiscorp.com 408-588-2000 x 120 : 408-588-1662 (FAX) ==========================================Article: 8874
Sorry for making trouble, my e-mail address for submition was incorrect.
Please submit papers to
hironaka@ce.hiroshima-cu.ac.jp
^^
=============================================================
CALL FOR PAPERS
The Sixth FPGA/PLD Design Conference & Exhibit
Pacifico Yokohama,Yokohama,Japan, June 24-26,1998
The "FPGA/PLD Design Conference & Exhibit" is the only conference and
exhibit on FPGA and PLD in Japan, which provides a forum to exchange
ideas and promote research on the fields of device technology, design
technology, EDA support tools, and applications for FPGA/PLD.
At the sixth conference and exhibit, we are planning to introduce more
practically technical information and leading edge technology trends
on "Devices, Designs, EDA tools, and Application for FPGA/PLD";
specially on the FPGA/PLD in the 21st century. To make more intensive
discussion possible on the current studies and the sprouting ideas,
the next conference will expand the number of user presentations and
tutorial sessions. For example subjects handled on these session is
such as FPGA/PLD device which enables entirely new functions,
developing "System on Chip" using IP, new design methodologies for
FPGA/PLD toward the 21st century, and killer applications for
FPGA/PLD.
We invite papers on the following topics and also welcome papers on
related fields, such as system LSI design, development, and
application. Papers on case studies of design or application
from industries are most welcome. We are looking forward to your
papers.
MAJOR TOPICS
* Device architectures
* Circuit design technology
* CAD/DA technology
* Development support technology with FPGA/PLD-compatible IP
* Developing System on chip with IP
* Compiler technology for embedded systems
* Emulation technology and rapid prototyping
* Hardware/Software codesign
* Reconfigurable computing
* Evolving hardwares
* All kinds of application using FPGA/PLD
* Other topics related to FPGA/PLD
PAPER SUBMISSION
Please send six (6) copies of extended abstract and the completed
application form to the address below. Your papers will be reviewed by
the program committee for selection. Besides technical contents, your
extended abstract is expected to contain a presentation outline
describing the background, goal, approaches, importance, and
originality. The extended abstract may not exceed four pages of A4
size papers, including the title, figures, and tables. Abstracts
exceeding four pages will not be accepted.
APPLICATION FORM
Fill in the application form with the title of the paper, name of
author(s), author(s) affiliation, abstract(about 100 words), and three
or less keywords, with the contact address of the
corresponding author; name, affiliation, postal code and address,
telephone number, FAX number, and E-mail address. We welcome
applications by E-mail or postal mail. Ask for application
forms(template) to the address below.
AWARD
Excellent papers will be awarded based on the decision made by the
program committee. The authors of excellent papers will be awarded at
the conference, and will be asked to give presentations at the special
session. Supplementary prizes will be also provided to the awarded
authors respectively. In addition, all applicants will receive a
three-day conference tickets for free.
SCHEDULE
* February 6, 1998(Friday): Deadline for submission of abstracts
and application forms
* March 17, 1998(Tuesday): Notification of acceptance
* May 8, 1998(Friday): Deadline for camera-ready papers
* June 24(Wed.)-26(Fri.), 1998: Conference
Send abstract/application forms or inquires to
Tetsuo HIRONAKA
Hiroshima City University
Ozukahigashi 3-4-1, Asaminami-ku, Hiroshima-shi, Hiroshima,
731-31, Japan
TEL:(082)830-1566 FAX:(082)830-1792
E-mail:hironaka@ce.hiroshima-cu.ac.jp
ORGANIZERS/SPONSORS
Organizers: Execution committee of
The Sixth FPGA/PLD Design Conference & Exhibit
Sponsors: The Institute of Electronics, Information and
Communication Engineers (of Japan)
(plan) Information Processing Society of Japan
(plan) Embassy of the United States of America
(plan) Semiconductor Industry Association
(plan) Distributers Association of Foreign Semiconductors
(plan) International Semiconductor Cooperation Center
----------------------------------------------------------------------
Tetsuo HIRONAKA
Faculty of Computer Sciences Tel : +81-82-830-1566
Hiroshima City University Fax : +81-82-830-1792
Hiroshima, 731-31, JAPAN E-mail: hironaka@ce.hiroshima-cu.ac.jp
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z