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Joseph H Allen <jhallen@world.std.com> wrote in article <ELELD5.3yv@world.std.com>... > > Can the slew rate be controlled on the boundary scan pins when they're being > used as general I/O? To use these I insert special symbols in place of the > normal ipad or opad in the schematic (orcad). But it gives an error if I > set the slew rate option (FAST) on these symbols. > > What is the default slew rate for these pins? I would guess slow, but I'd > like to know for sure. Bring up XDE and look at the IO Blocks for the pins in question.....Article: 8476
Just wondered if anyone would like to comment on their experience with the new ATMEL 40k. In abstract terms it looks very nice, as it is superbly regular/orthogonal/self-consistent. The only quibble I've noticed is that both ports of the RAM are clocked by the same clock: fine for DSP, but not so nice for FIFOs. (Put me right on that if I've misunderstood.) If anyone has now used the devices and would comment on how they and the tools work in practice, I'd be very interested to hear. Paul -- Paul Walker 4Links phone/fax paul@walker.demon.co.uk P O Box 816, Two Mile Ash +44 1908 http://www.walker.demon.co.uk Milton Keynes MK8 8NS, UK 566253Article: 8477
I don't know anything about the algorithm in question, but I know a little about FPGAs: You get the highest performance if you utilize massive parallelism, make every CLB work simultaneously, not waiting for interconnect- or logic- delayed inputs. That means, use pipelining and explore restructure the algorithm. In a totally different application, we have seen several-orders-of-magnitude improvements in DSP applications by changing from the conventional MACs to "distributed arithmetic" that really lets the CLBs work in parallel. Just some thoughts... Peter Alfke, Xilinx ApplicationsArticle: 8478
[This followup was posted to comp.arch.fpga and a copy was sent to the cited author.] In article <34992b23.86739239@news.lazerlink.com>, dmk1@valleytech.com says... > > Immediate openings for hardware and software deisgn engineers > at a growing DSP product company. Valley Technologies is seeking both > experienced and entry level engineers. If you desire to be part of > leading edge development company, please check out the following web > page: > > http://www.valleytech.com/employment.htm > > > > > This article was posted from <A HREF="http://www.slurp.net/">Slurp Net</A>. >Article: 8479
In article <ltbtye5stc.fsf@palver.dtek.chalmers.se>, Magnus Homann <d0asta@palver.dtek.chalmers.se> writes: > When using the largest Xilinx, we found that it got half the speed of > a pentium Pro at 200MHz and running NT4.0. CPUs are pretty good at doing addition. Is the problem memory/IO limited or CPU limited? > For this run, we used Synplifier and just modified the C-code into > VHDL. Do you think there will be any gains when optimizing the code > for Xilinx manually? You might get more info if you post a chunk of code - the inner loop. I've never used Synplifier. You might be able to get significant speedups by modest amounts of hand tweaking. What limits the current design? One signal? A whole data bus transfer? What's next? The really big gains in things like this usually come from changing the algorithim. Can you add pipeline stages? Do you need to prefetch the data? ...Article: 8480
About MD5 in FPGA:
I found a good piece of information in RFC 1810, where the algorithm
was analyzed. It seems that it is not very suitable for implementing
in an FPGA, due to very limited paralellism.
The algorithm is based on 32-bit additions and some logical op. There
are 4 adds in a loop, and only the two first can be performed
simultaneously.
When using a RISC CPU with multiple issue, it is estimated that the bit
rate of MD5 in Mbps is 1.25 x MIPS of the CPU.
They also estimated that with the current technology (July '95) a CMOS
VLSI would be capable of 256 Mbps. I have not fully understood their
calculations for that.
Is it reasonable to assume that todays FPGA can do half of that
(128Mbps)? I don't know how close the technologies are.
I also got a tip that the ORCA from Lucent might be better suited,
because it had better support for wider datapaths. I wonder if that is
true?
Thankful for any input.
Refs:
ftp://ftp.isi.edu/pub/hpcc-papers/touch/sigcomm95.ps.Z
http://www.internic.net/rfc/rfc1810.txt
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 8481Has anyone managed to simulate a bidi pin, using a script file, in Aldec/Foundation? I've spent hours at this and I can't do anything to get the output enabled - it's always hi-Z. One of the Xilinx answers mentions setting stimulator strengths, but these seem to be overridden when the script file is run. The pin is a registered input with a tristate buffer output; the command file explicitly sets GSR active (high) at the beginning of simulation, and holds GTS low throughout. I'm also having trouble with a simple tristate buffer output, which should be easy. I think this may be because I've previously applied Z to the output, and it then simply locks up as Z, and doesn't enable. Any ideas? EvanArticle: 8482
VHDL International Users' Forum
October, 1998
Preliminary Call for
Workshops, Tutorials and Papers
"Idea Factory: VHDL for Power Users"
http://www.vhdl.org/viuf
Over the past ten years, the EDA Industry has seen VHDL and some of
its satellite standards evolve from infancy to maturity. The time for
"introducting" VHDL to the user community is long past; VIUF must
address the needs of a more experienced user base. In light of this,
the Steering Committee for VIUF Fall 1998 has chosen to diverge from
the usual conference format.
Traditionally, Fall VIUFs have focused on the practical, real-world
application of VHDL. This will not change. The Steering Committee is
committed, however, to promoting a more active exchange of ideas and
experiences among the presenters, moderators and attendees through a
workshop and tutorial format. Workshops will be informal, but highly
focused. Attendance to individual workshops will be limited in order
to facilitiate open discussion.
Workshop topics:
- Modeling Enhancements I: "Tweaks and Enhancements"
The focus of this workshop will be the small "deficiencies" in
VHDL that drive you nuts and make your job harder (e.g. textio
does not support all standard data types). What language
adjustments could (or should) be included in VHDL-200X to
improve productivity?
- Modeling Enhancements II: "Challenges"
The focus of this workshop will be the larger issues. Given
VHDL's existing capabilities, can we enhance or change these
capabilities in VHDL-200X to meet future needs? Or, do we need
more significant structural changes to make the designs of the
future possible?
- VHDL at its limits: Switch-level and System-level Modeling
Current usage trends of VHDL appear to favor RTL/synthesis
coding. VHDL is applicable to a broader spectrum of design
challenges. What VHDL techniques and capabilities facilitate
modeling above and below the RTL level?
- Large Project Management & Control
Design projects encompass more than writing and simulating HDLs.
Systems on a chip and the increasing use of IP suggest the need
for more stringent control; design database verification is also
required. How can these tasks be accomplished? Are there VHDL
language changes that would better support these needs?
- Design and Synthesis for FPGAs
Working with FPGAs begins to mimic the skills and techniques
once used primarily in ASIC design. This implies that HDLs will
become more prevalent in this process. FPGA design also has
some unique challenges. Does VHDL usage enhance or inhibit
these efforts?
- Design for Reuse: IP Modeling
Some industry sources claim that verification requires up to 80%
of a design effort. With design sizes increasing and cycle times
decreasing, existing designs must be more efficiently
re-utilized. How? What features of VHDL can be used to enhance
design re-use?
- Testbenches and Testing
As designs become more complex and verification time decreases,
having more efficient and effective test methods is a must.
VHDL is a powerful tool for this, especially through the use of
testbenches. Which VHDL techniques, methodologies, and tricks
facilitate testing?
- VHDL vs. Verilog: Truths and Myths
They share much in concept, but are significantly different. Are
their uses different? Is common evolution desirable, or should
they each specialize? Most efficient utilization, both together
and separately? Can they handle the design tasks of tomorrow?
This workshop strives to highlight their uses, not accentuate
the battles of the past.
In addition to the focused workshops, the Fall forum will offer a range
of tutorials (novice to expert level), and a few technical papers
pertaining to the practical applications of VHDL. Tutorials in support
of any of the above workshop topics are of interest. Other potential
tutorial topics include (but are not limited to):
- Recent updates and new standards
- Behavioral Synthesis
- Hardware/Software Co-design and Co-verification
- Reconfigurable logic and dynamically reprogrammable FPGAs
- Advanced use of VHDL
- Getting up to speed with VHDL
Potential topics for papers include (but are not limited to):
- System-on-a-Chip Design: Case Studies
- Design methodologies and flows
- Advanced use of VHDL
- Analog and Mixed-Signal Integration
Submission Guidelines
The VIUF Fall 1998 Steering Committee invites you to contribute your
considerable VHDL expertise for the benefit of other "power users" by
submitting an extended abstract for a workshop presentation (panels
welcome), tutorial and/or paper. A workshop submission should identify
the above workshop topic under which it falls.
Submissions should include a 50-word abstract and a 500-1000 word
summary describing key ideas, results, major technical contributions,
advantages, limitations, application environment and/or directions for
future work, as appropriate. Each abstract will undergo a thorough
review by an international panel of distinguished experts. Those
submitting abstracts for workshops and tutorials will not be required to
prepare a full-length paper. However, they will be required to provide
a copy of their slides in machine readable form by the Final Material
Submission Deadline.
Please send your abstract and summary information to the Program Chair,
Peter Ashenden, via regular mail (see sidebar) or via electronic mail
(preferred) at:
petera@cs.adelaide.edu.au
Submit your extended abstract by April 15, 1998.
Important Dates:
Abstract Submission Deadline: April 15, 1998
Notification of Acceptance Sent: May 25, 1998
Final Material Submission Deadline: July 31, 1998
Conference Chair Program Chair
Yvonne T. Ryan Peter J. Ashenden
Leader's Edge Dept. Computer Science
953 Mt Carmel Drive The University of Adelaide
San Jose, CA 95120 Adelaide, SA 5005
USA Australia
Phone: 408-997-6028 Phone: +61 8 8303 4477
Fax: 408-997-7481 Fax: +61 8 8303 4366
Email: yryan@vhdl.org Email: petera@cs.adelaide.edu.au
Workshops Chair Tutorials Chair
James Goeke Jose Torres
Eastman Kodak Co. Viewlogic Systems, Inc.
901 Elmgrove Road 47211 Lakeview Blvd
Rochester, NY 14653 Fremont, CA 94538
USA USA
Phone: 716-726-6571 Phone: 510-659-0901
Fax: 716-726-7881 Fax: 510-659-0129
Email: goeke@kodak.com Email: jtorres@viewlogic.com
Design Contest Chair Distributed Materials Chair
Mike McCollough Matt Hsu
Hughes Aircraft Co. Shomiti Systems, Inc.
PO Box 902, RS/R1/A508 1800 Bering Drive
El Segundo, CA 90245 San Jose, CA 95112
USA USA
Phone: 310-334-7085 Phone:
Fax: 310-334-1243 Fax:
Email: mikem@tcville.es.hac.com Email: matt@shomiti.com
Publicity Co-chairs
Publicity Co-chairs
April Mitchell Nanette Collins
SEVA Technologies, Inc.
9340 Carmel Mtn. Rd, Ste D 37 Symphony Road, Unit A
San Diego, CA 92129 Boston, MA 02115
USA USA
Phone: 619-538-6283 Phone: 617-437-1822
Fax: 619-538-4271 Fax: 617-425-0340
Email: april@seva.com Email: nanette@nvc.com
Forum Management
Conference Management Services (CMS)
528 Abrego Street, Suite 205
Monterey CA 93940
USA
Phone: 408-394-6384
Fax: 408-394-6382
Email: kjm@event-mgmt.com
Program Committee
Peter Ashenden - The University of Adelaide (Chair)
Matt Hsu - Shomiti Systems, Inc. (Distrib. Mat. Chair)
J. Bhasker - Lucent Technologies
Dennis Brophy - Mentor Graphics Corp.
Todd A. DeLong - The University of Virginia
Steve Drager - Air Force Research Laboratory
Wolfgang Ecker - Siemens Corporate Technology
Darrell Gibson - Bournemouth University
Bill Hanna - The Boeing Company
John Hillawi - DA Solutions
Michael McKinney - Texas Instruments, Inc.
Paul Menchini - Menchini & Associates
Gabe Moretti - Veribest, Inc.
Wolfgang Nebel - Universität Oldenburg
Serafin Olcoz - SIDSA
Greg Peterson - Air Force Research Laboratory
Mark Ronan - Northern Telecom Ltd.
Lance Thompson - IBM Corp.
John Willis - FTL Systems, Inc.
Philip Wilsey - The University of Cincinnati
Article: 8483A basic question... I am looking for various ways of cleaning up a noisy clock without resorting to an additional external gate or using an additional internal clock. An old philips data book suggests a way using 2-3 pins on a PLD with 2 resistors to form a schmitt trigger, functional but expensive on pins. I am using Abel in Synario with a Lattice ISP. Any clues or pointers to resources? Cheers Don don@led.com.auArticle: 8484
In article <01bd0db8$b3f71560$158925cb@i586-133>, Don Ingram <dingram@m130.aone.net.au> writes >A basic question... > >I am looking for various ways of cleaning up a noisy clock without >resorting to an additional external gate or using an additional internal >clock. An old philips data book suggests a way using 2-3 pins on a PLD with >2 resistors to form a schmitt trigger, functional but expensive on pins. I >am using Abel in Synario with a Lattice ISP. > >Any clues or pointers to resources? > >Cheers >Don >don@led.com.au I needed a Schmidt trigger for a push-button reset circuit in a Lattice CPLD, and did it with two cross-coupled 2-input NANDs and an inverter feeding one of the NANDs, with the input to the other NAND connected to the input of the inverter. I saw this circuit *many* years ago in Don Lancaster's TTL Cookbook, but this is the first time I've used it! Leon -- Leon Heller: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk Amateur Radio Callsign G1HSM Tel: +44 (0) 118 947 1424 See http://www.lfheller.demon.co.uk/dds.htm for details of my AD9850 DDS system - schematic and software.Article: 8485
subject: source code for auto routers Is anyone familiar with the public domain source code that has served as the back ground for the currently common rip-up & retry type of autorouters seen on the market place? Berkeley's Mighty is said to be the start of them all, but it was (is) only capable of routing 2 layers. Since most now have the capability to handle more than 2 layers and also cost-based optimazation, and are remarkably similiar to each other, I'm assuming there is other pd source from which they have evolved. Source code for routers other than the ripup & retry types are also of intrest. Source code for "shape based", neura based, "annealing" based, etc. are also of intrest. If you know of some, let me know. Many thanks, -Hul htytus@iglou.comArticle: 8486
The vendors are slow to realise Schmitt triggers matter... I had a design last week, on a lowly 16V8, that HAD to be clocked from an open drain pin, and even with quite low pullups, the 16V8 was unhappy.. I was pleased to see the nerw AT40K FPGA's have programmable Schmitts on ALL IOs :-) Your best choice is : Look at TI, Philips PicoGATE, Fairchild TinyLOGIC series ( best range ) These are SOT23, 5 leaded SMD, Single Gates. Ideal for cleanup of single signala. The problam with 'feedback' schmitt construction is that at the threshold, these can oscillate, often > 100MHz. This short burst of RF, does wonders for GND noise, and often makes unrelated sections of the CPLD unstable in operation. Even a SLOW edge ( optocoupler IP ) can have the same effect. - jim granville. Don Ingram wrote: > > A basic question... > > I am looking for various ways of cleaning up a noisy clock without > resorting to an additional external gate or using an additional internal > clock. An old philips data book suggests a way using 2-3 pins on a PLD with > 2 resistors to form a schmitt trigger, functional but expensive on pins. I > am using Abel in Synario with a Lattice ISP. > > Any clues or pointers to resources? > > Cheers > Don > don@led.com.au -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Many reusable object modules - i2c, SPI, SPL, RC5, etc = Safe, Readable & Fast code - Step up from Assembler and C = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55. OptoISP for 89S, AVR, AT17K. = for more info, mailto:DesignTools@xtra.co.nz Subject : c51ToolsArticle: 8487
Hello, I want to know the detail of FPGA Hardware Architectrue. If anyone can show me some stuff? BR Liu YinArticle: 8488
Hi all, Does anyone know a source for hardware systems computing square root using self-timed asinchronous approach? Thanks,Article: 8489
Don Ingram wrote: > A basic question... > > I am looking for various ways of cleaning up a noisy clock without > resorting to an additional external gate or using an additional > internal > clock. An old philips data book suggests a way using 2-3 pins on a PLD > with > 2 resistors to form a schmitt trigger, functional but expensive on > pins. Here is a proven and simple solution that costs one extra pin: Use the extra pin to be an uninverted output driven by the input that you want to clean up. Then connect a 10 kilohm resistor from this output to the input you want to clean up. ( Effectively, you have created a latch with a weak feedback ) Now drive the input through a 1 kilohm series resistor. This gives you a hysteresis of 10% of the supply voltage. You can change the absolute and relative resistor values to suit your application, Peter Alfke, Xilinx Applications.Article: 8490
Hello, I'm looking for a digital logic library for Visio4. The one that they have in the Electrical--Electronic is just not robust enough. Any one have something better. JimboArticle: 8491
Does anyone know where I can find some reference on how to implement PCI-AT bridge with CPLD or FPGA?Article: 8492
Duane Clark wrote: > Howdy, > > Does anyone know of any 5 volt serial PROMs larger than the XC17256D, > that can be used with XC4000EX FPGAs? I notice that Xilinx has 512K and > 1M bit PROMs in a 3.3V package, but apparently nothing so far in 5V. > > -- > > -Duane Xilinx is now shipping X1701 (5V). (1Meg serial PROM) -Prashanth Banuru.Article: 8493
Bill Lenihan wrote: > Does anyone know of any cases, benchmarks, studies, etc., demonstrating > where the envelope is for FPGA designs done on state-of-the-art PCs vs. > state-of-the-art workstations? Has anyone had a case where a design > couldn't compile on a PC, but could when ported to a workstation? (or > vice-versa?) Xilinx M1.0 tools work well on both PC's & WS's. Make sure that when designing on PC's you have enough RAM and Virtual memory settings. These are device dependent larger the design more memory requirements.Article: 8494
E.M. Shattock wrote: > Has anyone managed to simulate a bidi pin, using a script file, in > Aldec/Foundation? I've spent hours at this and I can't do anything to > get the output enabled - it's always hi-Z. One of the Xilinx answers > mentions setting stimulator strengths, but these seem to be overridden > when the script file is run. The pin is a registered input with a > tristate buffer output; the command file explicitly sets GSR active > (high) at the beginning of simulation, and holds GTS low throughout. > > I'm also having trouble with a simple tristate buffer output, which > should be easy. I think this may be because I've previously applied Z > to the output, and it then simply locks up as Z, and doesn't enable. > > Any ideas? > > Evan I am able to simulate BIDI-IOB's in foundation via command macro file. Say in your case: BIDIIOBPAD -> IBUF -> FD -> BUFT -> OBUF ->BIDI-IOBPAD |Command macro file | a comment in foundation simulator... | timing simulation set_mode timing watch gsr gts clk tri_enable in_fd out_fd_tristated | Save output on every clock edge break in clk ? do (print > simulout.txt) | Define clock clock clk 0 1 step 25ns | initial conditions -- if that matters | note high tri_enable means output is in high impedance high tri_enable in_fd high gsr gts | simulate for 4 clock cycles say.. c 4 low gsr gts | now tri_enable kicks in c 4 low in_fd c 2 | enable the output of FD now.. low tri_enable c 2 | change input.. high in_fd c 2 | end of file. I tested this in F1.3 version and works fine.Article: 8495
> Xilinx M1.0 tools work well on both PC's & WS's. > Make sure that when designing on PC's you have > enough RAM and Virtual memory settings. These > are device dependent larger the design more memory > requirements. I have an experience. Consider a simple asynchronous reset D-type flip flop, I have successfully got the bitstream file by using Synopsys and Xilinx M1.3.7 in WS. But, I failed in PC by using Foundation. It minimized my design such that it contained nothing. I don't know why. Any idea? Regards, KenArticle: 8496
"Prashanth K. Banuru" <prashanth.banuru@xilinx.com> writes: > Bill Lenihan wrote: > > > Does anyone know of any cases, benchmarks, studies, etc., demonstrating > > where the envelope is for FPGA designs done on state-of-the-art PCs vs. > > state-of-the-art workstations? Has anyone had a case where a design > > couldn't compile on a PC, but could when ported to a workstation? (or > > vice-versa?) There was a comparison on Exemplar's Leonardo running on Sun(s), (not the all-mighty top-notch model though), on a PC running Linux and the same PC running Win95. Linux showed similar preformance to that of the Sun, Win95 was considerably slower and it also crashed on one design. The results were posted here about a year ago and I seem to remember that I've seen them on a web page somewhere. Leonardo running on a modest 133MHz Pentium w/ 64M RAM with Linux is actually quicker than on an Axil-320 (a sparc-20 clone) w/ 256M RAM. The only problem is, that you can have simulators and synthesis tools for Linux but you can't get place&route as yet. None of the vendor toolchains that I know of are available for Linux (quite a few vendors' support engineers have never heard of it by my experience). Zoltan -- +------------------------------------------------------------------+ | Reply address antispammed. Use ZOLTAN-at-BENDOR-dot-COM-dot-AU | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 8497
Rick Collins (rickman@erols.com) wrote: : We just bought the Xilinx development software. However we found that : the copy protection works differently from the past. We were expecting : to be able to install the software on several workstations and share a : dongle. But now they protect the licence by keying the software to the : serial number on your diskdrive. : : I have been told that this serial number can be changed so that we can : once again let each engineer work at his own desk. Does anyone know how : to do this? Can you point me to a source of this information? : : : Rick Collins : : rickman@erols.com Use Disk Edit utility for disk drives. Cheers, Paresh K. Joshi. ------------------------------------------------------------------------ Problems cannot be solved in the framework in which they are created. ------------------------------------------------------------------------Article: 8498
The relevant article is below. You could have found it with Altavista
or Dejanews, too.
>>I got the new M1 product update to XACT step for PCs, and I would love to
>>try it but the licensing system is seriously braindead. It uses flexlm and
>>a parallel port dongle for copy protection. This would be fine (PADS PCB
>>uses this method also, and it works fine), but it also requires a matching
>>hard drive partition serial number. Now I don't understand how this
>>improves security either, but there it is. They require it. In fact their
>>flexlm license file is generated to match it, and their web-based license
>>file generator gives you only one shot to create this file, and gives you no
>>opportunity to change your mind about what hard drive you're going to
>>install the program on.
>>
>>So they expect:
>> - you to run their software on one machine only: no switching dongles to
>> my lap-top anymore
>>
>> - your hard drive to never break
>>
>> - you to never upgrade the hard drive in your machine
>>
>> - hmm... maybe they don't require the dongle any more and the security
>> is based entirely on the partition serial number. This is great news!
>> I'll install it on all my machines and edit the volume name entry of
>> each of them to match!
>
>It's true! The key is no longer needed and the security is entirely based
>on the partition serial number. This is vastly more conventient than that
>silly hardware key thing. I won't have to lug that key around when I use
>my laptop anymore.
>
>Now suppose you have linux installed on your hard (as I do) and the
>Windows-95 vfat partition is /dev/hda2 and you want the serial number to be
>(hex) AABB-CCDD:
>
>log into root,
>
>type: joe /dev/hda2,39,4 # edits bytes 39-42 of drive C boot sector
>type: ^T T # put joe into overtype mode
>type: ` x D D ` x C C ` x B B ` x A A # Enters new serial number
>type: ^K X # saves data back to disk
>
>You could also do this from Windows-95 but you would have to write a C
>program. Remember it's bytes 39-42 of the first sector of the C: partition.
>Be sure to make backups before messing with your boot sector.
Actually I forgotten about the MS-DOS debug command, which
surprisingly, is
still provided with windows-95. This is the easiest way to change the
serial number without linux, but be very careful (back up your
files!), as
debug is not very forgiving:
C:\>debug
l 0 2 0 1 - load one sector beginning with sector 0 of
drive 2 (C:) into address 0 (of some
segment)
e 27 - hex entry mode
DD <SPACE> CC <SPACE> BB <SPACE> AA <RETURN>
d 0 - display to verify results
w 0 2 0 1 - write boot sector back to hard drive
q - quit
C:\>
Article: 8499
Dear all: i'm using Altera's Maxplus2 to complete my project and use
VHDL as design entry, because the logic is complex,Maxplus2 fails to fit
it,i think i have to insert some LCELLs into my VHDL source files,but i
have no idea about how to do this,can anybody help me? any help will be
appreciated!!
-------------------==== Posted via Deja News ====-----------------------
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