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I just build a uart with a 10k chip. The thing is that the design work fine under DOS but when i place it under Win NT it's does not work. Well it interfeer with other blocks like my parallel port. Only input are the same (aen, iord, iowr d[7..0] and a[9..0]). It only works when i specify the option "what you see is what you get". Is someone have an answer? or an idea?Article: 8126
Hi. Does anybody explain the meaning of " metastability time of a
flip_flop", and what would happen if data changed in metastability time
of a flip_flop? any help will be appreciated! thanks advanced!
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 8127Victor Levandovsky wrote: > >I`m looking for a State Machine >basics material in Internet. > See: "Writing Verilog State Machines " http://www.quicklogic.com/support/anqn/qn038.pdf for a good HDL tutorial that can be demonstrated with tools at: http://www.quicklogic.com/products/webtools/ johnArticle: 8128
In article <879988211.25480@dejanews.com>, <lzh@bd748.pku.edu.cn> wrote: >Hi. Does anybody explain the meaning of " metastability time of a >flip_flop", and what would happen if data changed in metastability time >of a flip_flop? any help will be appreciated! thanks advanced! There is a (very narrow) window of time when changing the inputs (in VIOLATION of the setup/hold parameters!) to a flip flop can cause the flip-flop to enter a "metastable" state -- i.e. when, in essence, it is neither "here" nor "there" (in essence, the internal circuitry is perfectly balanced between "0" and "1" -- note that this doesn't necessarily mean that the output is at 2.5 volts!). It will remain in this condition until something upsets the balance (a glitch on the power supply/gnd lines, the phases of the moon, an honestpolitician walking by, etc.). Then, it will *arbitrarily* snap to one state or the other. Note that since you have (by definition) violated the setup/hold times of the device, there is no way to say which way the output *should* settle so either outcome is equally correct. The problem with metastability in general is that all bets are off in terms of how the device will behave when it goes metastable. For example, if the device has a propagation delay of 5 nS, it is entirely possible that the device could remain "locked up" for *100* nS! Or *200*! Or maybe just 10. The "likelihood" of metastable events is directly related to the frequencies of the data (D input) changing and the clock frequency. Usually, this is "once in a very blue moon". But, if you are, for example, designing a synchronizer to synchronize a 100MHz data source to a 1GHz clock (bogus example) and the flip-flops are NOT metastable hardened, youcould expect metastable events quite often. If the consequences of such an event tend to get lost in the noise of your system, then you'll probably never notice it. But, if such an event was related to the launching of perhaps a nuclear warhead, then you might be surprised at the headlines in the next day's paper! :> Someone had a good series of app notes on the subject many years ago (maybe MMI or AMD?) including methods to measure a device's susceptibility to metastability (i.e. the size of that "window") and a table of sample "metastable event frequencies" for typical data/clock rates. Can someone fill in the details here? --donArticle: 8129
Are there any other vendors out there which supply reprogrammable configuration memories other than Atmel?Article: 8130
In article <6504bl$9tk$1@baygull.rtd.com> dgy@rtd.com (Don Yuniskis) writes:
>
> Someone had a good series of app notes on the subject many years
> ago (maybe MMI or AMD?) including methods to measure a device's
> susceptibility to metastability (i.e. the size of that "window")
> and a table of sample "metastable event frequencies" for typical
> data/clock rates. Can someone fill in the details here?
>
1. "Metastability Characteristics of Intel EPLDs",
Intel application note AP-336 (May 1990)
2. "Everything You Migt Be Afraid to Know About
Metastability," Wescon 1987, program session
record 16.
3. "Metastability Evaluation of Logic Technologies,"
Texas Instruments, Datasheet for SN74AS3674
and BCT databook
4. "Metastability Tests for the 74F786 - A 4-Input
Asynchronous Bus Arbiter," Signetics application
note AN217 (July 1988)
5. "Oscillatory Metastability in Homogeneous and
Inhomogeneous Flip Flops", IEEE Journal of Solid
State Circuits, Vol 25, No 1, Feb 1990, pp 254-264
6. "General Theory of Metastable Operation," IEEE
Transactions on Computers, Vol C-30, No 2,
Feb 1981, pp 107-115
Article: 8131Karl A. Student wrote: > I am trying to download the MAX7000S via the JTAG port, but I cannot get > the correct downloading file with MAX PLUS 2. What is the correct > binary file to send down: .jed, .hex file or what? and how do I get it? it is a .pof file. Regards, SteveArticle: 8132
Curtis Lyson wrote: > I have programmed a Altera Flash FX780 by the JTAG port before, and I am > trying to do the same with the MAX7000S EPM7128. Does anyone know how to > get the files from MAX PLUS 2 into the correct binary form to send to the > JTAG ports?? If you are using MP2, this is easy, use a byteblaster and send the .pof file. Steve.Article: 8133
Markus Leberecht wrote: > Overall, the question is: What's better, using a regular highest-density > FPGA and designing the datapaths on your own (with a proven design flow), > or using a reconfigurable device with given datapaths (and possibly a > dubious design flow)? > > Appreciating your help > > Markus Markus, From where I stand, the Altera FLEX6016 offers the best trade off for speed, register density and price. Regards, Steve.Article: 8134
Peter Alfke wrote: > > Tim Warland wrote: > > > A CPLD is a complex programmable logic device of which > > the FPGA - Field programmabel gate array is a subset. > > > > This is not the generally accepted opinion. > > Most engineers, editors and marketeers agree that CPLD are PAL-derived, > with an AND-OR structure, and FPGAs are not a subset of this species. > FPGAs (SRAM or antifuse-based) are look-up-table or multiplexer-based, > and form a separate species. Peter omits the point that CPLDs are supersets of PLD architecture - assuming one is allowed to use the term PLD for architectures such as 16R8, 16V8 and 22V10. Thus a CPLD architecture can normally be broken down into linked sets of 18CV8-like three-stage architecture (AND/OR/macrocell) - although some offer additional refinements such as input macrocells. Perhaps one simple way to distinguish CPLDs from FPGAs is the type and arrangement of interconnect. For most of the devices with which I am familiar, CPLDs tend to have large arrays of chip-level or macro-level interconnect, with relatively small amounts of local interconnect, whereas FPGAs tend to have relatively small amounts of chip-level and macro-level interconnect but relatively large amounts of local interconnect. Thus what's in the middle of a CPLD will be mainly interconnect, whereas what's in the middle of an FPGA is mainly logic with local interconnect. Another distinction often made is that of pin-to-pin timing. With a CPLD timing will normally be deterministic and sometimes fully definable before the design is fitted. With an FPGA timing will normally be critically dependant on fitting/routing. Note that I'm not talking about achievable frequency of operation. In the very old days, PLDs were fast and FPGAs were slow (gross oversimplification, but was once a useful rule of thumb). That's not so now, and some FPGAs are extremely fast. Just my views as a user and interested onlooker. Corrections welcomed. Tim Forcer tmf@ecs.soton.ac.uk Department of Electronics & Computer Science The University of Southampton, UK The University is not responsible for my opinionsArticle: 8135
Steven Groom wrote: > > Markus Leberecht wrote: > > > Overall, the question is: What's better, using a regular highest-density > > FPGA and designing the datapaths on your own (with a proven design flow), > > or using a reconfigurable device with given datapaths (and possibly a > > dubious design flow)? > > > > Appreciating your help > > > > Markus > > Markus, > > From where I stand, the Altera FLEX6016 offers the best trade off for speed, > register density and price. > > Regards, > > Steve. You might also look at the new Atmel AT40K20. It has a very high register density, partial reconfigurability, it is fast, and is supposedly priced lower than anything else of the same density (20K gates). Prices I've seen are about $50 for small quantities. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 8136
Hello, I want to take few Lattice FPGA I.C.s, If you know price of following ICs can you write me? ISPLSI 2096-80 UNIT PRICE ? ISPLSI 2128-80 UNIT PRICE ? ISPLSI 1048-80 UNIT PRICE ? Thanks.Article: 8137
Trolling For DAC Dirt 6 Months Later
------------------------------------
Suffering from great gobs of guilt at having not written a review
of this year's DAC'97 in Anaheim, CA (especially after having had
surveyed the users & vendors about their impressions of DAC'97), I'm
writing a "penance" DAC Review over the Thanksgiving week.
I already have all those e-mails from my first post-DAC'97 survey
(and there's still quite a bit of useful info in them!), but, with it
being 6 months later, I'd like to add a new twist. Now that 6 months
have passed, please write me what you thought (and, yes, you'll be
anonymous) about what you saw at DAC'97 & *whether it panned out now*.
Did you see/buy something that appeared "hot" at DAC'97 only to find
it a complete waste of time? What turned out to be the biggest lie
you got from an EDA vendor at DAC'97 from your subsequent 6 months
post-DAC'97 experience? It being 6 months later, what actually turned
out to be the most useful thing/topic/tool/technique you got from
DAC '97 or elsewhere? How about the big guys like Cadence, Mentor,
Synopsys, Avanti? How about the many small EDA companies? Feel free
to include all sorts of news & facts & opinions about what happened in
the last 6 months in the EDA industry to support your views/conclusions!
What tools that have come out in the past 6 months that have suddenly
become useful to you now? Any juicy NDA stuff? Remember: I don't quote
anyone by name, unless I already heard it in person at DAC'97 in public
*or* they're OK with being quoted. Send in your impressions!
.... And Calling On The Dark Side, Too!
----------------------------------------
Since turnabout is fair play, I'd like to also invite the EDA vendors
(aka "The Dark Side") to feel free to add their 6-months-after-DAC'97
impressions, too! Tell it as it is! Whose products do you wish you were
selling? Whose are glad you're not selling? What was the most ridiculous
claim you saw an EDA vendor try to make at DAC? How about in the last
6 months? Tell it as it is!
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 5459 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 8138You can also go to http://www.memecdesign.com/tr03009.htm for a one-hot state machine design guide and library for ViewLogic. tom On Wed, 19 Nov 1997 17:28:26 -0800, "John Birkner" <birkner@quicklogic.com> wrote: >Victor Levandovsky wrote: >> >>I`m looking for a State Machine >>basics material in Internet. >> >See: >"Writing Verilog State Machines " >http://www.quicklogic.com/support/anqn/qn038.pdf >for a good HDL tutorial that can be demonstrated with tools at: >http://www.quicklogic.com/products/webtools/ > >john > >Article: 8139
Metastability in FPGAs: Ever since 1989, the Xilinx data book has contained several pages of descriptive text plus some data on the metastable behavior of Xilinx FPGAs. In the present version it is on pages 13-41..43 and desribes test methodology and results for XC4000-3, (IOB and CLB), XC5200-5 CLB, XC4000-6 ( worse than -3, no surprise) XC3100-09 (CLB and IOB ) and, for comparison purpose, the old XC3042-70, the subject of the original study. Mean-Time-Between-Failure for a given clock and data frequency and a given tolerable extra delay has improved over the years by more than14 decimal orders of magnitude, from less than a second to more than a million years ( assuming 1 MHz data change, 10 MHz clock, 2 ns tolerable extra delay ). The flip-flops in our newest FPGAs are every bit as fast as the flip-flops in the best and newest microprocessors, and considerably better than in gate arrays. That should not be a surprise, since our flip-flops use the same kind of tight design and the same advanced processing as microprocessors do. As a result, metastability in FPGAs with dedicated flip-flops has lost some of its horror. But it is still worth analyzing in every asynchronous interface. Peter Alfke, Xilinx ApplicationsArticle: 8140
Hi, I'm implementing a HDLC concentrator in VHDL on a XC5215. It takes multiple 16kbit/s D channels from Basic Rate ISDN ports, concentrates them, and sends them (via other cards) to a V5.2 switch / phone exchange. Question: If ITU-T Q.921 (LAPD) states that the maximum HDLC packet size shall be 260 octets, why does ETS 300 324-1 (V5.2) say that the maximum size will be 533 octets? This doubles the size of my buffer ram (it's already 1Meg). ETS 300 324-1 also refers to "too long frames" (up to 533 bytes) which must be accepted, but it also says that the "longest permissible frame" is 268 bytes. Why the difference? Does anyone have any experience in this area? Any information would be appreciated. TIA, Allan.Article: 8141
lzh@bd748.pku.edu.cn wrote:
:Hi. Does anybody explain the meaning of " metastability time of a
:flip_flop", and what would happen if data changed in metastability time
:of a flip_flop? any help will be appreciated! thanks advanced!
:
As others have written, it's what happens when you change the data
input to a flipflop too closely to the clock edge (in violation of the
specs.)
Instead of neatly latching the new value, the f/f ends up like a coin
balanced on edge: just waiting for some random signal to knock it
either way. There is no telling which way it will go.
One point to bear in mind is that the probability of it NOT having
settled decreases exponentially with time: so design your logic to
leave that f/f as long as possible before you must read it.
And NEVER bring in a parallel data path & risk simultaneous
metastability in several f/fs as you synchronise the word: it's
guaranteed that some will snap the new data & some will revert to the
old state. Latch the parallel data separately (using its own clock),
then synchronise a single VALID bit, which says you can read the
latch.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 8142dgy@rtd.com (Don Yuniskis) wrote: >In article <879988211.25480@dejanews.com>, <lzh@bd748.pku.edu.cn> wrote: >>Hi. Does anybody explain the meaning of " metastability time of a >>flip_flop", and what would happen if data changed in metastability time >>of a flip_flop? any help will be appreciated! thanks advanced! > >There is a (very narrow) window of time when changing the inputs >(in VIOLATION of the setup/hold parameters!) to a flip flop can >cause the flip-flop to enter a "metastable" state -- i.e. when, >in essence, it is neither "here" nor "there" (in essence, the >internal circuitry is perfectly balanced between "0" and "1" -- note >that this doesn't necessarily mean that the output is at 2.5 volts!). >It will remain in this condition until something upsets the balance >(a glitch on the power supply/gnd lines, the phases of the moon, >an honestpolitician walking by, etc.). Then, it will *arbitrarily* >snap to one state or the other. Note that since you have (by definition) >violated the setup/hold times of the device, there is no way to say >which way the output *should* settle so either outcome is equally >correct. >more good stuff deleted< Often the most critical characteristic of a metastable event in a FF comes from the output not being monotonic...the Q output starts out low, for example, rises into the transition region, wanders around and finally either drops back or heads high. This behavior can cause clocked devices connected to the Q to double clock or for several devices to receive or not receive clocks. A few manufacturers make metastable hardened FF that may take longer to settle to high or low but will monotonically transition...thus clocking all down stream devices equally. jeffArticle: 8143
Ray Andraka wrote: > > Brad Smallridge wrote: > > > > Dear Atmel users, if there are any out there, > > > > I have been using a oneshot design for about 2 years > > without giving it much consideration. It consist of > > two D flipflops, an Inverter, and an AN2 gate. > > > > I -> AN2 -> > > ^ ^ > > ->FD ->FD > > > > It takes up 4 cells, is fairly flexible in configuration. > > It goes positive for one clock cycle on a rising edge. > > It may glitch, I haven't the equipment to really tell. > > > > Anybody got any new ideas? > > > > Brad Smallridge > Works for me, except it pulses on a falling edge! No actually, it pulses on a positive edge, when the first FD has a low and the second FD has a high. > I got a macro in my > library called fedet (falling edge detect) that is essentially what you > got there. Registering the incoming signal as you do does a reasonable > job synchronizing it in the atmel. (the metastability window is very > short). If you are dealing with a synchronous signal you can ditch the > left flop unless it helps in keeping the clock rate up (pipelining the > wires works wonders in the AT6k for those of you not familiar). If it > is async, it may be a good idea to put a second flop on the input to > decrease the probability of ametastable upset. Ametastable upset? Is that what I'm feeling? > > You can get to two cells (w/o the input sync ff) if you use an FDN and > an AN2, with the added benefit of the input being capable of either > color or a bus input. > > +---+ +---+ > ->|FDN|-red->|AN2|->red or blue > | |-blu->| | > +---+ +---+ > Wow, that's great! Works for me. > I assumed you are looking for a rising edge detect, not a one-shot > multivibrator in the classic sense. SOmeone posted a follow-up > recommending using external passives which I certainly don't advocate. [snip] > For those not familiar with the AT6K line, it is an SRAM based FPGA > containing an array of fine grain logic cells (56x56 for AT6005, 80x80 > for the At6010). Each cell is basically a half adder with a flip flop > on the sum output and some simple gating to permit function as a > multiplexer or some simple 2 or 3 input functions. Each cell has direct > connections to each of the four nearest neighbors (NSEW) and connections > to a local bus network grid. The bus segments run 8 cells and connect > to the sext segment through a repeater. Careful design in these parts > will yield clock rates to around 125 MHz (been there done that...see the > high performance bit serial paper on my website). > > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka I pulled down your Dynamic Video Hardware paper. Very readable. No Atmel there, is that right? There isn't any software for partial reconfiguration of Atmel 6k. Is there something better than the "machine code" process that I employ? Do you have any papers on the Atmel FPGA?Article: 8144
lzh@bd748.pku.edu.cn wrote: : Hi. Does anybody explain the meaning of " metastability time of a : flip_flop", and what would happen if data changed in metastability time : of a flip_flop? any help will be appreciated! thanks advanced! : -------------------==== Posted via Deja News ====----------------------- : http://www.dejanews.com/ Search, Read, Post to Usenet I waited to see of anyone would attempt to help you with this, as I think my explanation below is a bit cumbersome. Imagine that in the heart of a flip-flop there is a pair of transistors crosscoupled, base to collector, and collector to base, with these two nodes having identical pullup resistors, and these two transistors being identical. You actually have this, more or less, as the key bistable element inside some flip-flops in some technologies. Now imagine that you place this simple flip-flop in its linear range, where it is essentially balanced, in meta-stable equilibrium. It will of course eventually transition to one of its stable states, but to the extent that you hit the balance point well, it will take a LONG time to do so. This is the meta-stability problem. My own experience with this was with 74S74s, where with a slowly varying signal on the D input, if D was at the amplitude neutral point when the clock active transition occurred, the outputs changed very slowly, so that the transition time was not a couple of nanoseconds like it should be, but perhaps 50 or 100 nanoseconds. That is, it is important to NOT rely on the ttl inputs of flip-flops as comparators, but to make sure that the inputs are at valid ttl levels whenever the flopflop is clocked. Remember, the parts are specified in this way, with all legal input levels excluding the range 0.8 to 2.0 Volts. When valid ttl levels are provided, with good valid S ttl transition times, there is still about a 1 ns time window during which the output transition times of a 74S74 are visibly degraded when the D input is transitioning also in the general time neighborhood. It is incumbent on you, the designer, to make sure that such degraded output states or transition times have no dire consequences in terms of system state and behavior. It is possible to calculate the probability of something happening, assuming random input transition times, and you must evaluate how often system failures will occur for this reason. I have seen systems where such failures occurred once per shift, which was unacceptable. Often it is hard to educate management about this problem, and why it may be important to the customer. In this case it involved shutting down a production line while a piece of equipment was power cycled, once per shift. This did NOT make for good customer relations. The various IC databooks tend to not dwell on this subject, since they would like their customers to think their product was a thing of beauty and a joy forever. Remember there are NO digital parts, only analog parts specified in a digital way, for digital use. This requires hiding substantial analog behavior from the customer. Meta-stability is one such analog behavior. Some of the earlier ttl data books might be useful for learning about such problems. Have fun. -- Charles Mosher ratranch@svpal.orgArticle: 8145
In article <3474c626.1321210@news.mv.net>, jeff@wa1hco.mv.com (Jeff Millar) writes: > A few manufacturers make > metastable hardened FF that may take longer to settle to high or low > but will monotonically transition...thus clocking all down stream > devices equally. Would you trust a design that depended upon that characteristic? Metastability is a tricky area. My semiconductor physics is weak enough that I can't prove that it is or isn't possible to build a FF that makes a clean transition. [I've seen enough pictures in ap-notes to know that it is possible to build a FF that does summersaults.] I've built my share of kludgy logic, but I try real hard to avoid clocking things with a FF, especially one that might be metastable.Article: 8146
Hal Murray <murray@pa.dec.com> wrote in article <652vrc$54c@src-news.pa.dec.com>... > In article <3474c626.1321210@news.mv.net>, jeff@wa1hco.mv.com (Jeff Millar) writes: > > > A few manufacturers make > > metastable hardened FF that may take longer to settle to high or low > > but will monotonically transition...thus clocking all down stream > > devices equally. > > Would you trust a design that depended upon that characteristic? nope. add another flip-flop, let things settle, and then clock it in and be done with it. or redesign the system to eliminate the asynchronous inputs, if possible. it's surprising how often the system design puts in asynchronous interfaces that don't need to be there. ------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) -------------------------------------------------------------Article: 8147
try 'FPGA JUMP STATION' at http://www.optimagic.com/ ! reno:)Article: 8148
Kim Hofmans wrote: > > Most of the time while using the M1 software for Xilinx (viewdraw, epic, > etc..) > I get the message : "Dr Watson : application error " followed by "not enough > storage to complete this operation". > > Anyone having similar problems ? > The platform I'm using : PentiumII, NT4.0 > > Setting the registry higher didn't seem to solve the problem. > > Anyone a solution ? > > Tnx in advance ! > Better use the Vendor with A.... I tried to use the M1 SW, the installation was hard work. After this i had to install the patches !!! THeni tried to proceed with the tutorial (count8) ==> failed. I couldn't fit my VHDL (Synopsys) design ==> failed !!! Have to wait for the X.... support. Isn't it sad. Best regards and good luck. Lothar Brodbeck p.s. sorry that i couldn't support you, but sometimes it is maybe helpful that you kbnowe that you are not the only oneArticle: 8149
Hello reader, i would announce two development boards of Alcatel Telecom. The two boards are useful for ASIC prototyping and simulation. We already used the boards to verify DSP algorithms written in VHDL, to test the behaviour of PLL circuits, to built test equippment (complex signal generators written in VHDL) for our fab and for other applications. Short description of the boards: HW_SIM * 200.000 gates logical resources (4*Altera EPF10K50) (300.000 gates if equpipped with 1EPF10K70) * 2 Slots for SIMM memory modules (30 pin types) * 2 on board oscillators (48,640 MHz, 16,384MHz) * PBA size 233mm*210mm * breadboard area * reset circuit * ... DEV_KIT * 20.000 gates logical resource (2*Altera EPF81188) * on board oscillator (16,384 MHz) * PBA size 233mm*160mm (possible splitting 2 times 100mm*160mm) * breadboard area * reset circuit * ... For more information about the development boards contact one of the persons listed below. Financial Questions: R.Prestin@stgl.sel.alcatel.de Technical Questions: brod@lts.sel.alcatel.de Best regards Lothar Brodbeck p.s. An user wrote: ... We successfully used the HW_SIM development board to verify our complex signal processing algorithm. ... The programming and the handling of the evaluation board stands out. ...
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