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I just found another bug with XABEL...which someone else may be experiencing... I have a state machine that has a RESET term in each one of its states (first condition of if/elseif for each state...) that is supposed to put the state machine back to its 'InitialState', which is S0. This provides a synchronous (or is supposed to) reset for the state machine. The state machine is implemented as one bit per state. The symptom is, when the RESET input was set, the state machine would not reset its outputs. What caused this problem is.....the way XABEL did the logic for state S0. State S0 goes unconditionally to State S1. It used a flop (reset, NOT preset, as I believe it should have if it was thinking clearly) and implement the S0 bit active low. The input to the flop was inverted, and all the destinations of S0 were inverted too. The logic to the flop was a big OR gate with one input inverted (the S0 input) and then NAND'd with the RESET term. The problem is, once the S0 state bit goes inactive (high) it can never be brought back low, even by the RESET input term! When I added the RESET term to the asynchronous reset of the S0 flop (via XACT), it now works fine. This was the easiest 'work around' to fix the problem, but the logic it originally implemented is clearly incorrect. It should have just used the RESET input as the D input to the S0 flop...and implemented S0 as a preset flop, instead of a reset flop (output logic adjusted accordingly too). Austin Franklin darkroom@ix.netcom.comArticle: 7601
Request : We would like to get Intel HEX format, FPGA Serial Loader Prom files, for as many different FPGAs as possible. The BIT content, and target FPGA, are not important - these are to test our Programmers' READ ability, esp if any of the vendors is 'non std' in their HEX formats. TIA. Jim Granville. -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = OptoPGM- Safe, fast, isolated ISP for Serial Pgm Micros, and AT17x config EPROMS = for more info, Email : DesignTools@xtra.co.nz Subject : c51ToolsArticle: 7602
In article <874781985.3786@dejanews.com>, nstrater@mcmail.com () wrote: > I want to write my own configuration software, ... > But, ... data-bitstream-formats > seem to be closely guarded trade secrets. Assuming there is stand alone software to convert logic cell net list to bit streams,then a legitimate owner could provide an automated internet/modem conversion service. This would allow you to develop the software at least. Or you could code generate for an array of smaller ICs with a fixed interconnect. Alternatively might the 'PARALLEL Processing Connection' like to develop an open architecture FPGA? I think it would be best to define an array of modest devices with associated memory. Mike Jones, Digital Dexterity Ltd.Article: 7603
>I think it would be best to define an array of modest devices >with associated memory. Possible, but this would have 2 disadvantages for my handheld design: an array takes more space and costs more power. And large sram fpgas aren't too good on power anyway. Nikolaus Strater, Exeter UKArticle: 7604
A while ago there was a thread dealing with FPGA
architectures for Reed-Solomon coders. Back then I posted a
reply regarding our work on arithmetic architectures in
Galois fields which prompted several inquiries.
Well, we managed to write a paper describing a detailed
comparison of multiplication and inversion architectures
for GF(2^8) on Xilinx and Altera platforms. The paper was
presented at FCCM '97.
A postscript version of the full paper can be found at
http://ece.WPI.EDU/Research/crypt/
Go the the "recent publications" link.
Regards,
Christof
*************************************************************************
Christof Paar http://ee.wpi.edu/People/faculty/cxp.html
Assistant Professor email: christof@ece.wpi.edu
Cryptography Group phone: (508) 831 5061
ECE Department, WPI fax: (508) 831 5491
100 Institute Road
Worcester, MA 01609, USA
*************************************************************************
Article: 7605
I still have OrCAD SDT IV (schematic entry tool) and Xilinx XACT OrCAD BASE
development system version 1.20 (FPGA tool for up to XC3030 which works with
both SDT IV and SDT 386+) for sale. Both include original manuals,
registration No.s and disks (and hardware key for Xilinx XACT). I'm asking
$200 for SDT IV (original price: $500) and $300 for XACT (original price:
$1000).
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7606
FPGA Synthesis with
Exemplar Galileo and Altera Max+Plus II
September 30, 1997
Holiday Inn Raleigh/Durham Airport
Research Triangle Park, North Carolina
October 2, 1997
Hyatt Westshore - Airport
Tampa, Florida
During this free one-day hands on workshop, experts from Exemplar,
Altera and Mentor Graphics will teach you how easy it is to target VHDL
and Verilog designs in Altera FPGAs using Exemplar's Galileo Extreme
FPGA Synthesis and Altera's Max+Plus II development system.
You'll learn how to:
- Synthesize VHDL or Verilog design descriptions with Galileo Extreme
- Compile a design with Max+Plus II
- Place and Route a design with Max+Plus II
- Analyze and tune the timing of your design to improve performance
By attending you'll also:
- Be eligible for Extreme Deals on Galileo Extreme
- Receive a free Galileo evaluation license
Who should attend:
- FPGA designers
- FPGA CAD support staff
Particulars:
- Workshop one day long and runs from 8:30 AM to 5:00 PM.
- Workshop will be held at the Holiday Inn Raleigh/Durham Airport
in Research Triangle Park, North Carolina and at the Hyatt Westshore
Hotel near the Tampa Airport in Tampa, Florida.
- Continental breakfast and lunch will be served.
- Workshop includes notebook of presentation materials and labs.
- Complete the on-line registration form or contact Mike Walsh in
Mentor Graphics North Carolina Sales Office at 919.544.0200.
Registration is limited to 20 attendees per session. Register on-line
at: http://www.mentorg.com/region/SE/Workshops/Exemplar_Altera/index.html
- Additional product demonstrations and refreshments will follow
the workshop.
Attendee comments from previous workshops:
- The hands-on approach is much more effective than a slide
presentation show.
- Instructor was informative emphasizing "real life" situations.
- Lab intensive learning is the way to go
--
...Mike
No Guts, No Glory.
+--------------------------------------------------------------+
| Michael P. Walsh mike@rtp-nc.mentorg.com |
| mike_walsh@mentorg.com |
| Technical Account Manager - Ericsson |
| Mentor Graphics Corporation V:(919) 484-2505 |
| 2525 Meridian Parkway, Suite 260 F:(919) 544-0701 |
| Research Triangle Park, North Carolina 27713 |
+--------------------------------------------------------------+
Article: 7607Last Notice of the Virtual Socket Interface Alliance Fall Worldwide Member Meeting. October 3, 1997 Santa Clara, California The VSI Alliance is developing interface standards for the mix-and-match, plug-and-play of macros on system-level-chips. Presentations will be made on the current work with --System level design --On-chip buses --Design implementation --Design verification --IP protection --Mixed-signals --Manufacturing-related test For details, check our website at http://www.vsi.org Members are free, non-members pay a fee of $150. A registration form can be downloaded from the web, or send registration information to nancy@vsi.org: name, title, company, phone, email, address, etc. See many of you there, Stan Baker Executive Director, VSI AllianceArticle: 7608
If anybody should know of the existense of sourcecode for implementing the AMD "TAXI" chip in an FPGA I would be interested to know about it. Thanks Jens Clausen jec@post1.tele.dkArticle: 7609
I am thinking of making a USB ASIC for Legacy systems (i.e. non USB factory) via an ECP parallel port. My question is this: I am deciding if I should modify a PCI based host controller ASIC or code an intel based microcontroller with a SIE engine. ECP maps nicely to the PCI interface (64byte fifo's, register mappping ect), a VXD would stimulate this chip via the parallel port, to provide USB 1.0 host services WITHOUT a USB protocol stack. Alternatively I could code a controller. I think the ECP ASIC would give me greater expansion and development opportunities, i.e.. a "standard" device for legacy connectivity and a lower production cost, but with high NRE's. The controllers a bus, with limited expansion capacity. Any thoughts would be appreciated. John Calder jcalder@well.comArticle: 7610
Hi, I'm looking for a Compact PCI interface spec. & vme vs compact pci perfomance comparison. Any hints are welcome. ( web-sites, vendor..) Thanks. Oh In Hee email : ihoh@nexgen.co.krArticle: 7611
Marty Hoffensetz wrote: > > Could anyone recommend an in-system (re-)programmable serial EEPROM which > can boot and configure the Altera FLEX 10k devices? And a cheap > programmer/serial cable assembly to program these EEPROMs in-situ? > > Could you also indicate whether one EEPROM can boot a number of PLDs, and > if so, how do you create the single burn file from the individual device > files. > > Marty Hoffensetz > CAE MRad Pty Ltd > Adelaide, Australia > marty@mrad.com.au Marty, Try ATMEL 17C65, 17C128 or 17C256 EEPROMS. WWW.atmel.com. You can burn and re-burn them up to 10000 times. ATMEL also sells a litle board with the software that can be used as a base for in-circuit programming or you can write your own code. In US ATMEL sell this board for $250.00 with software. You can download two or more FPGA from a single EEPROM, but it depens on how big are FPGAs and how big is EEPROM. Usually FPGA tools allow you to combine several bit files in a single file. Good luck. Leo.Article: 7612
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Article: 7613jhallen@world.std.com (Joseph H Allen) wrote: >I still have OrCAD SDT IV (schematic entry tool) and Xilinx XACT OrCAD BASE >development system version 1.20 (FPGA tool for up to XC3030 which works with >both SDT IV and SDT 386+) for sale. Both include original manuals, >registration No.s and disks (and hardware key for Xilinx XACT). I'm asking >$200 for SDT IV (original price: $500) and $300 for XACT (original price: >$1000). Good luck. Niether of these packages are supported any longer, and what you're asking for the XACT system is 3 times what I just paid for the latest M1 software. You might get a nibble at $30-$50 for all of it, but I certainly wouldn't pay more than that for it. Tim Olmstead webmaster of the CP/M Unofficial web page http://cdl.uta.edu/cpmArticle: 7614
Hi, Motorola Computer Group started to ship CompactPCI cards ! You're main concern should be is VME standard will support in the future (Motorola computer group could be good indication to the future market) and if yes,which data - rate are going to be support in the new VME standard and by whom ? Oh In Hee wrote: > Hi, > I'm looking for a Compact PCI interface spec. & vme vs compact pci > perfomance comparison. > Any hints are welcome. ( web-sites, vendor..) > > Thanks. > > Oh In Hee > email : ihoh@nexgen.co.kr -- Rami Gideoni 1. This message does not necessarily reflect the company's opinion - just my own humble one. 2. SPAM Mail is UNWELCOME and UNWANTED and be assured that I will *never* buy your product nor visit any website advertised //--------------------------------------------------------------------- // Always code as if the guy that ends up maintaining and/or testing // you code is a vaiolant sychopat who knows exactly where you live. // --------------------------------------------------------------------Article: 7615
Hi, Motorola Computer Group started to ship CompactPCI cards ! You're main concern should be is VME standard will support in the future (Motorola computer group could be good indication to the future market) and if yes,which data - rate are going to be support in the new VME standard and by whom ? Oh In Hee wrote: > Hi, > I'm looking for a Compact PCI interface spec. & vme vs compact pci > perfomance comparison. > Any hints are welcome. ( web-sites, vendor..) > > Thanks. > > Oh In Hee > email : ihoh@nexgen.co.kr -- Rami Gideoni 1. This message does not necessarily reflect the company's opinion - just my own humble one. 2. SPAM Mail is UNWELCOME and UNWANTED and be assured that I will *never* buy your product nor visit any website advertised //--------------------------------------------------------------------- // Always code as if the guy that ends up maintaining and/or testing // you code is a vaiolant sychopat who knows exactly where you live. // --------------------------------------------------------------------Article: 7616
In article <60jarc$6tb$1@newshost.cyberramp.net>,
<timolmst@cyberramp.net> wrote:
>jhallen@world.std.com (Joseph H Allen) wrote:
>>I still have OrCAD SDT IV (schematic entry tool) and Xilinx XACT OrCAD BASE
>>development system version 1.20 (FPGA tool for up to XC3030 which works with
>>both SDT IV and SDT 386+) for sale. Both include original manuals,
>>registration No.s and disks (and hardware key for Xilinx XACT). I'm asking
>>$200 for SDT IV (original price: $500) and $300 for XACT (original price:
>>$1000).
>Good luck. Niether of these packages are supported any longer, and
>what you're asking for the XACT system is 3 times what I just paid for
>the latest M1 software. You might get a nibble at $30-$50 for all of
>it, but I certainly wouldn't pay more than that for it.
You got M1 for $100 bucks? Who sells it for that price? Last time I
checked, the foundation base package was $1000 and the foundation standard
package was $3000. I assume the new M1 stuff is similarly priced.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7617
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Article: 7618Hello all Lattice users., I am writing ABEL program for ISPLSI1048. I want to use IOC registers for registereted inputs. I dont have any problem if I use GLB FlipFlops. But How can I use IOC FlipFlops I dont know. Can you send me any example ABEL program ? Thanks.Article: 7619
Joseph H Allen wrote:
> In article <60jarc$6tb$1@newshost.cyberramp.net>,
> <timolmst@cyberramp.net> wrote:
> >jhallen@world.std.com (Joseph H Allen) wrote:
>
> >>I still have OrCAD SDT IV (schematic entry tool) and Xilinx XACT
> OrCAD BASE
> >>development system version 1.20 (FPGA tool for up to XC3030 which
> works with
> >>both SDT IV and SDT 386+) for sale. Both include original manuals,
> >>registration No.s and disks (and hardware key for Xilinx XACT). I'm
> asking
> >>$200 for SDT IV (original price: $500) and $300 for XACT (original
> price:
> >>$1000).
>
> >Good luck. Niether of these packages are supported any longer, and
> >what you're asking for the XACT system is 3 times what I just paid
> for
> >the latest M1 software. You might get a nibble at $30-$50 for all of
> >it, but I certainly wouldn't pay more than that for it.
>
> You got M1 for $100 bucks? Who sells it for that price? Last time I
> checked, the foundation base package was $1000 and the foundation
> standard
> package was $3000. I assume the new M1 stuff is similarly priced.
>
> --
> /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H.
> Allen */
> int
> a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
>
> +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
>
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n","
> #"[!a[q-1]]);}
Nobody that I know sells it for 100 bucks unless through a promotional
deal where they are willing to take the loss. The download cables alone
are worth more than that. I have one Foundation Base (schematic and
Router and full CPLD) still in the box from a canceled project that I am
selling for 300.00. It comes with the full one years maint/upgrades and
XILINX download cables. I have one at this price. This is not a regular
sale, and is only offered on this one. The regular price is $495.00.
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President EDA & Engineering Tools
Associated Professional Systems (APS) http://www.associatedpro.com
3003 Latrobe Court richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897 Fax:410.661.2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 7620Dear Mr. Hahn! Your company has promised multiple times, that your FPGAs fit at 80% utilization and 80% pin-usage without problems. Iīve got such an email from you! Now we had only to change a 9560 design a little bit (we tie out 9 internal signals, there is no need for additional logic), and there is no more fit. To your information, the original design data is 73% utilization and 66% io-pin-usage, Thank you for your TRUE statements. Why do we discuss with you? This is not the only problem during our design-phase. At first (with software release 7.2) nothing fitted, until you sent us the software-release 7.22 which worked a little better. About 4 weeks after we called for help. Thank you for your FAST response. Reading your handbook you promise a PLL in the 10K series. Nice feature, we had to use is. BUT there is no PLL in the 10Ks; there is only one special 10K100 which includes a PLL and this device is not deliverable within a acceptable period of time. Thank you for your GOOD handbook. Buying the Max2Plus software, a one year free software maintenance was claimed. But, at all there are no free updates. Thank you for your FAIR service. After finishing this design, we will terminate any business relationship with you. We will be XILINX customers in future. This company listens and is innovative. ALTERA only claims garbage and doesnīt support the customers. Or is a customer like us, which claimed to order about 100 pieces 10K100 pa to small for you? Shure this are only revenues about 50.000$ pa. Probably you will find a good solution, yet?! So why I write you this in (bad) english. We believe the relationship between Altera and itīs customers is so critical, that we post this letter to a couple a newgroups. Good luck.Article: 7621
Hello : I'am using ALTERA FLEX10K30 to design a TVgame board< just like SEGA Megadrive >. I just complete 1 Plane Display in my Video Module ( 256 K x 32bit SRAM 20ns ). ( 1 plane = 640(H)x480(V) , 1 dot = 1 Byte = 256 color ) Now I got some problem . I no have any time to add "Dynamic Image Object" in H_BLANK. Anyone can tell me how can I do ? Thanks. Regards. Michael Schumacher Taiwan neng1@ms1,hinet.netArticle: 7622
Does any-one have a model for a fifo 16X4, which can be used in an fpga
design 4000e series, if so i would be gald to here from any-one who has such
a model or who could direct me to somewere, were i may obtain one.
Thanks Davey
Article: 7623>You got M1 for $100 bucks? Who sells it for that price? Last time I >checked, the foundation base package was $1000 and the foundation standard >package was $3000. I assume the new M1 stuff is similarly priced. THat price is actualy fairly repeatable. Just go to a Xilinx seminar. Even the "regular everyday" price is down to about $495 now. Tim Olmstead webmaster of the CP/M Unofficial web page http://cdl.uta.edu/cpmArticle: 7624
david.surphlis@gecm.com wrote: > > Does any-one have a model for a fifo 16X4, which can be used in an fpga > design 4000e series, if so i would be gald to here from any-one who has such > a model or who could direct me to somewere, were i may obtain one. > > Thanks Davey Check the Xilinx web page for the FIFO app note. The control logic for various flavors of fifos are described there. The size of the fifo is easily changed to meet your needs. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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