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> Ray Andraka's reply (see other thread to original posting). I just need > to figure out the logic to latch the write request, process the message, > and then negate the write request until the next one comes through. > Hmmm... > Use a T flip flop clocked by the write clock and enabled by the write enable. The data should go into a register clocked by the write clock and enabled by the write enable. The T flop will toggle each time a write is performed. The output of this feeds a four state state machine: present state toggle next state 00 0 00 00 1 01 01 X 11 11 0 10 11 1 11 10 X 00 decode states 10 and 01 (XOR or the state bits) to create a write pulse that is synchronized to the RAM clock. The state machine described needs no additional synchronizing flops for most systems since only one bit is enabled for toggling at any time and the toggle sense states are separated by intermediate states. The only real restriction is the RAM clock has to be a lot faster than the write rate to ensure the holding register is emptied before the next write occurs. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka @ ids . net http://users.ids.net/~randrakaArticle: 7426
Thanks for your input, Ray. Your suggestion woke me up to the simplicity of this process. For my design the read processing will occur at a higher frequency, so I can run the FIFO at that rate, and latch the write requests for subsequent processing by the FIFO at FIFO rates. The write pulser is basically just a JKFF followed by a pair of DFFs, with an XOR of the outputs of the two D "flops", as you call them, to generate the synchronized write request. With J and K tied high and the input write request as a clock, the JKFF does the toggle, while the subsequent DFF pair translates the signal to the FIFO time domain. The XOR generates a write request that is only one clock period long, which is what the FIFO needs to write the data. If you see any bugs with this, please say so. I think your suggestion pulled me out of a logical rut. -- Bryn Wolfe - Robotics Engineer Metrica TRAC LabsArticle: 7427
USA; Charlotte, NC; Electrical engineer; FPGA, DSP; 50 Mghtz Experience in embedded systems design using: FPGAs (Altera preferred), DSPs and PLDs; Systems level architecture; Sensitive high speed analog designs; and signal distribution. Control systems familiarity highly desirable. Please refer to JO# 2793RJS in your response. Richard Steinman Team Leader rjs@cmagroup.com IT & Software Solutions Team Career Marketing Associates http://www.cmagroup.com/IT.htmlArticle: 7428
Peter Alfke wrote: > > Maybe standard terminology is lacking, but I would be interested how a > "non-clocked FIFO" could possibly work. Something has to tell the device > to accept data, and something else has to tell it to spit out the next > word. I call those signals clocks. You can call them "handshake". > > Just semantics. > > Peter Alfke, Xilinx The best example I have of a non-clocked FIFO is a COTS chip, the TI SN74ACT7203 2048x9 Asynchronous FIFO. It has no clock, but depends on separate read and write signals to indicate when a transaction should occur. Granted, the rising (or in this case, falling) edge "clocks" the circuit, but there is no reference clock on either side to say whether the read or write signal lines are valid. Consequently, with this asynchronous operation, the read signal must transition (high to low) to indicate a read, whereas a synchronous FIFO could leave the read enable signal asserted and let the read clock initiate independed read operations. As to which one is better, that depends on the use of the circuit. TI produces both kinds. In fact, they have Asynchronous, clocked, strobed and synchronous FIFOs, all of which say that the read and write operations can be asynchronous or coincident. So, let me think, asynchronous refers to the relationship of a read or write operation to a reference clock AND asynchronous refers to the timing relationship between independent read and write operations. Aye caramba! Hope you can understand my confusion with the words. Thanks for your input. -- Bryn Wolfe - Robotics Engineer Metrica TRAC LabsArticle: 7429
In article <341580C9.EBCE1109@hypercon.com>,
Bryn Wolfe <bwolfe@hypercon.com> wrote:
>Thanks for your input, Ray. Your suggestion woke me up to the simplicity
>of this process. For my design the read processing will occur at a
>higher frequency, so I can run the FIFO at that rate, and latch the
>write requests for subsequent processing by the FIFO at FIFO rates. The
>write pulser is basically just a JKFF followed by a pair of DFFs, with
>an XOR of the outputs of the two D "flops", as you call them, to
>generate the synchronized write request. With J and K tied high and the
>input write request as a clock, the JKFF does the toggle, while the
>subsequent DFF pair translates the signal to the FIFO time domain. The
>XOR generates a write request that is only one clock period long, which
>is what the FIFO needs to write the data.
This is dangerous. Your write pulse might be shortened if the first D
flip-flop is clocked right at the edge where the toggler transistions (this
is called a meta-state instability problem). To fix it, insert another
D-flip-flop before the two D-flip-flops. If this flip-flop captures during
the transistion, it's output will settle before the next flip-flop sees the
signal (actually it may not, but the probability of hitting the second
flip-flop's capture window is very small, which is just as good).
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7430On 8 Sep 1997 18:01:52 GMT, "Rich K." <rich.katz@gsfc.nasa.gov> wrote: >at&t data book shows att3030 in either 44 or 68 pin and 3,000 gates and 100 >clb's. each clb has two f-f's according to the picture and f-f's in the >i/o blocks also which are real handy either directly or by unused pins. >i'm sure if i get this wrong we'll hear from our good friend across the >pond! Does he mean me? ;-) You need a new _Lucent_ book Rich. Stuart >(vendors arranged in alphabetical order from lower to higher - next one >will be reverse order :-) -- Joke Press Release -- Zwitterion Systems - High quality FPGA vapourware, available soon(ish). Real expensive now, but Zwitterion expects them to be so cheap, they project volume pricing of under a buck for by Q4/2000. (Add safe harbour BS get-out clause here) -- Ends -- Sorry, bad day at the office, needed some light relief.Article: 7431
On Tue, 09 Sep 1997 12:04:55 -0700, Bryn Wolfe <bwolfe@hypercon.com> wrote: >The best example I have of a non-clocked FIFO is a COTS chip, the >TI SN74ACT7203 2048x9 Asynchronous FIFO. It has no clock, but depends on >separate read and write signals to indicate when a transaction should >occur. Granted, the rising (or in this case, falling) edge "clocks" the >circuit, but there is no reference clock on either side to say whether >the read or write signal lines are valid. Consequently, with this >asynchronous operation, the read signal must transition (high to low) to >indicate a read, whereas a synchronous FIFO could leave the read enable >signal asserted and let the read clock initiate independed read >operations. Both Lucent and Xilinx DPRAM elements should be able to implement such an asynchronous FIFO as you describe. The write signal would be a processor wr_bar line, and would feed the clock input of the DPRAM and the clock input of your write address counter. Both would run on the same rising edge so you would setup your data relative to the rising edge of wr_bar, and at the edge, the write would be synchronised to write into the RAM (self clocking), and at the same time increment the counter ready for the next write cycle. Reading is done asynchronously so a counter feeds the read address port, and is incremented on the rising edge of your rd_bar signal. rd_bar asserted (low) would turn on your output buffer etc. so the data is instantly readable. Throw in a bit of logic to do full/empty flags and "Hey presto", a truly asynchronous FIFO in all senses of the description (I think). Only fly in the ointment for Xilinx is the 1mS maximum high time on their RAM clock input. StuartArticle: 7432
On Tue, 09 Sep 1997 10:00:57 -0700, Bryn Wolfe <bwolfe@hypercon.com> wrote: >If you see any bugs with this, please say so. I think your suggestion >pulled me out of a logical rut. If you are reading (asynchronously?) on every clock cycle, when do you plan to write to the "synchronous" SRAM that runs on your read clock? You would have to run the read clock at least double the read rate, so that you can fit in any pending write requirement so that they appear to be transparant to the system. StuartArticle: 7433
greetings. i'd be interested in hearing people's experiences,
good, bad, or indifferent, with the Virtual Computer Corporation
"HOTworks" development system. {This is a $995 PCI board for
reconfigurable computing based on the Xilinx 6216 RPU.} How
well do the development tools work?
thanks
atw
not speaking for intel....
Article: 7434Stuart Clubb <s_clubb@netcomuk.co.uk> wrote in article <3415bb76.4920844@nntp.netcruiser>... > > On 8 Sep 1997 18:01:52 GMT, "Rich K." <rich.katz@gsfc.nasa.gov> wrote: > > >at&t data book shows att3030 in either 44 or 68 pin and 3,000 gates and 100 > >clb's. each clb has two f-f's according to the picture and f-f's in the > >i/o blocks also which are real handy either directly or by unused pins. > >i'm sure if i get this wrong we'll hear from our good friend across the > >pond! > > Does he mean me? ;-) **** **** you answered, didn't you? ;^) **** > > You need a new _Lucent_ book Rich. **** **** er, no offense intended! **** **** but did get a new job (in other life, this from home 'puter) **** > > Stuart > > >(vendors arranged in alphabetical order from lower to higher - next one > >will be reverse order :-) **** **** after i do higher to lower alphabetical order, i planned from going **** from the middle out to be fair. by this time, my new *lucent* book **** will be here and they'll be right up there; good timing stu! **** but you'll be behing motorola. **** > > Sorry, bad day at the office, needed some light relief. > **** **** as our leader says, "i feel your pain" ****Article: 7435
Joseph H Allen wrote: > > This is dangerous. Your write pulse might be shortened if the first D > flip-flop is clocked right at the edge where the toggler transistions (this > is called a meta-state instability problem). To fix it, insert another > D-flip-flop before the two D-flip-flops. If this flip-flop captures during > the transistion, it's output will settle before the next flip-flop sees the > signal (actually it may not, but the probability of hitting the second > flip-flop's capture window is very small, which is just as good). > -- I am assuming synchronous logic, such as what you get using the Altera EAB as a synchronous RAM. In that case, as long as the shortened pulse meets the setup time of the write enable flop on the EAB there is not a problem (the pulse shortening effectively delays the leading edge of the synchronized toggle pulse due to the metastable recovery time). The probability of a metastable upset in a given period of time is a function of the clock frequencies of both clock domains and of the metastable recovery characteristic of the flop (which is related to the max toggle rate). The metastability characteristics of most FPGAs are pretty good, so in most applications the single level synchronization is sufficient (assuming a synchronous target for the generated pulse). However, in cases where clock latency is not an issue the extra flop certainly won't hurt. For the FIFO, the extra flop will eat into the minimum write cycle. In this case, I believe you will get more bang for the buck by lowering the clock frequency on the RAM domain instead of adding an extra latency stage. That can be accomplished by using a fraction of the RAM clock to clock the synchronizing circuit -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka @ ids . net http://users.ids.net/~randrakaArticle: 7436
> When I served a booth at EuroDac '96, across from us there > was a small European FPGA company that was touting a 20x30mm > FPGA die. > > I would like a contact if anyone knows who I am talking about. > Anyone knowing of an alternative largish source would > be greatly appreciated as well. > > Many thanks. > > [M.Vorbach] The last thing I heard was, that this company doesn´t exist any longer. Their chip vendor was not able to implement the design.Article: 7437
In article <34161BD7.42B9@ids.net>,
Ray Andraka <no_spam_randraka@ids.net> wrote:
>Joseph H Allen wrote:
>> This is dangerous. Your write pulse might be shortened if the first D
>> flip-flop is clocked right at the edge where the toggler transistions (this
>> is called a meta-state instability problem). To fix it, insert another
>> D-flip-flop before the two D-flip-flops. If this flip-flop captures during
>> the transistion, it's output will settle before the next flip-flop sees the
>> signal (actually it may not, but the probability of hitting the second
>> flip-flop's capture window is very small, which is just as good).
>I am assuming synchronous logic, such as what you get using the Altera
>EAB as a synchronous RAM. In that case, as long as the shortened pulse
>meets the setup time of the write enable flop on the EAB there is not a
>problem (the pulse shortening effectively delays the leading edge of the
>synchronized toggle pulse due to the metastable recovery time). The
>probability of a metastable upset in a given period of time is a
>function of the clock frequencies of both clock domains and of the
>metastable recovery characteristic of the flop (which is related to the
>max toggle rate). The metastability characteristics of most FPGAs are
>pretty good, so in most applications the single level synchronization is
>sufficient (assuming a synchronous target for the generated pulse).
>However, in cases where clock latency is not an issue the extra flop
>certainly won't hurt. For the FIFO, the extra flop will eat into the
>minimum write cycle. In this case, I believe you will get more bang for
>the buck by lowering the clock frequency on the RAM domain instead of
>adding an extra latency stage. That can be accomplished by using a
>fraction of the RAM clock to clock the synchronizing circuit
You are probably right, but I would still be careful. Feeding one flip flop
into another has a very low probably for a double meta-instability event
since the second flip-flop's capture window is very short (.1ps if I
remember correctly). If you instead feed the shortened pulse to multiple
inputs, the clock-skew between different ram bits becomes your window: on an
fpga this is in the 400ps range (for xilinx if you use a global clock
buffer), so things are vastly worse. Still if you are running at 30MHz or
less, you're probably ok.
There are other games you can play to reduce the pipeline delay: clock the
inserted flip-flop with the negative clock edge.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7438Stuart Clubb <s_clubb@netcomuk.co.uk> wrote in article <3415bb76.4920844@nntp.netcruiser>... > On 8 Sep 1997 18:01:52 GMT, "Rich K." <rich.katz@gsfc.nasa.gov> wrote: > > >at&t data book shows att3030 in either 44 or 68 pin and 3,000 gates and 100 > >clb's. each clb has two f-f's according to the picture and f-f's in the > >i/o blocks also which are real handy either directly or by unused pins. > >i'm sure if i get this wrong we'll hear from our good friend across the > >pond! > > Does he mean me? ;-) > > You need a new _Lucent_ book Rich. > > Stuart **** got on the *lucent* www site last nite, couldn't find where to order one. **** can you supply a www address, e-mail address, or a phone # where i can order one **** up? **** thanks, **** rkArticle: 7439
In article <340D7061.1078@compuserve.com> Chad Bearden <ebeard@compuserve.com> wrote: > Hello, > > I'm looking for some info/parts to do the job of interpolating and Hello, I'm looking for some info/parts to do the job of interpolating and decimating a US/Euro HDTV digital stream. In the past I've used the Raytheon TMC2242 to do this on CCIR streams. any suggestions? chad.Article: 7440
In article <EFrLGD.AF6@world.std.com> jhallen@world.std.com (Joseph H Allen) wrote:
> In article <5u7v21$5d8@neptune.myri.com>,
> Wen-King Su <wen-king@myri.com> wrote:
> >In a previous article jhallen@world.std.com (Joseph H Allen) writes:
In article <5u7v21$5d8@neptune.myri.com>,
Wen-King Su <wen-king@myri.com> wrote:
>In a previous article jhallen@world.std.com (Joseph H Allen) writes:
>:
>;It would be really nice if PCI controller FPGAs could be configured over the
>:PCI bus. One way of doing it is to use configuration writes with the fpga
>;data encoded in the address.
>Why not just do it through JTAG.
I don't know anything about JTAG or JTAG on the PC. Is it board by board
addressable? I'll have to learn more about it.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7441On 10 Sep 1997 13:44:40 GMT, "Rich K." <rich.katz@gsfc.nasa.gov> wrote: >**** can you supply a www address, e-mail address, or a phone # where i can >order one email me a shipping address, and I will have it mailed to you. Regards StuartArticle: 7442
Because you are working with Xilinx FPGAs, the Xilinx web site is probably a good start 'http://www.xilinx.com'. However, you may also find various interesting and applicable information on The Programmable Logic Jump Station at 'http://www.optimagic.com', in particular, the Research pages at 'http://www.optimagic.com/research.html'. -- Steven Knapp OptiMagic, Inc. E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com KITT <gillette@gillette.demon.co.uk> wrote in article <3413126D.6B50@gillette.demon.co.uk>... | Hi, my names Phillip and I'm going to be starting a final year | university project involving the Xilinx FPGA within the next few months. | | I don't have much knowledge of FPGA's at the moment, would someone take | the time to either copy some information to this newgroup, or point me | to a site on the web please? | | Thanks in advance, | | Phil Renfield |Article: 7443
I have been given some design files in Viewlogic format. I only have OrCAD and Protel. Is there a utility around which can convert the Viewlogic stuff to something I can read? Path: ix.netcom.com!news.webspan.net!newsfeed.internetmci.com!newsfeed.internetmci.com!206.229.87.25!news-peer.sprintlink.net!news.sprintlink.net!Sprint!cpk-news-hub1.bbnplanet.com!news.bbnplanet.com!newsfeed.ecrc.net!news.new-york.net!news.columbia.edu!osiris.giss.nasa.gov!newsfeed.gsfc.nasa.gov!usenetArticle: 7444
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Article: 7445hi, viewoffice (pc version is what i have) has an edif schematic writer - does that help? rk Simon Bacon <SimonBacon@tile.cut_this.demon.co.uk> wrote in article <873907223snz@tile.CUT_THIS.demon.co.uk>... > I have been given some design files in Viewlogic format. I only > have OrCAD and Protel. Is there a utility around which can convert > the Viewlogic stuff to something I can read?Article: 7446
Stuart Clubb wrote: > > On Tue, 09 Sep 1997 10:00:57 -0700, Bryn Wolfe <bwolfe@hypercon.com> > wrote: > > >If you see any bugs with this, please say so. I think your suggestion > >pulled me out of a logical rut. > > If you are reading (asynchronously?) on every clock cycle, when do you > plan to write to the "synchronous" SRAM that runs on your read clock? > You would have to run the read clock at least double the read rate, so > that you can fit in any pending write requirement so that they appear > to be transparant to the system. > > Stuart Actually, my FIFO implementation uses interleaved memory blocks, so that reads and writes can occur simultaneously. A pair of staging registers on the read side allow me to instantly read the current first-out (FO part of FIFO) value. When the read switches to the other staging register, the one just read is being loaded with the next value. This is kind of a prefetch operation, in caching terms. It's impossible for a read and a write to collide. There's a fairly good writeup of the logic in Altera's application note AN 66 (Implementing FIFO Buffers in FLEX 10K Devices) which you can get from their web site at http://www.altera.com/html/literature/litprod1.html#f10k. It's pretty slick! Did I answer your question? Hope so. -- Bryn Wolfe - Robotics Engineer Metrica TRAC LabsArticle: 7447
XaQti Corporation: If you think that putting "Systems-on-a-Chip" is the direction the Electronics Industry is headed; and if you believe that the major future growth of the Semiconductor Industry is in networking; then you will want to work at XaQti Corporation. XaQti is seeking a few key individuals with strong networking architecture backgrounds; hardware ASIC designers, systems and board engineers and Software Engineers who will help us fulfill the promise of putting the "Network-on-a-CHIP"(TM). XaQti is privately held and well financed. We offer competitive salaries, excellent benefits and employee incentive stock options. If you are interested in helping to bring the next generation of Ethernet prodcuts to the market, please email your resume to hr@xaqti.com David C. Newkirk XaQti Corporation Web: http://www.xaqti.com "Network-on-a-CHIP" TMArticle: 7448
John Archambeault schrieb: > Oh yeah. If forgot. If you are TRULY masochistic, you could > convert > the bitstream to a text representation of the binary. (so it looks on > a > normal text viewer as 001110011100, etc). Then manually append the > bitstream > for each fpga, removing the header for each and modifying the header > for the > first to include to total number of bits (of the total bitstream) and > then > either covert the "text 0110011" to real binary or just leave it in > the "text > 0110011" and download it. > With patience you could get a small script (program) to do it, > but (for > us at least) it was much simpler to do what I said before. (copied > below) > > Enjoy, > John > > > I had the same problem only with 3100A. The way around it is a bit > convaluted, > but it does work. Use the prom makeing tool to set it up as if a > monster PROM > was going to perform a serial download. Then, juse feed that PROM > file into > the XCHECKER (name?) PC download cable. It will accept PROM files. > > Good Luck, > John > > BTW: I documented this a while back, but am going from memory right > now. If > you still can't get it, e-mail and I'll check the old documents. > -- > John Archambeault > End of article 7946 (of 7957) -- what next? [npq] > > -- > John Archambeault I didn't read the original message, however if it concerns assembling daisy-chain bitstreams for serial download (slave serial or JTAG) for XC4000 (or 3000) from a CPU, we have a small tool to do that.Code is in C. Mail if you need it. Andreas -- Andreas Kugel - University of Mannheim - Dept. of Computer Science V B6,26 - 68131 Mannheim - Germany Phone:+(49)621 292 1634 - Fax:+(49)621 292 5756 mailto:kugel@mp-sun1.informatik.uni-mannheim.de http://www-mp.informatik.uni-mannheim.deArticle: 7449
Esperan specialize in supplying independent, application orientated VHDL and Verilog based training. We have very close relationships with most of the main EDA and FPGA vendors, and our courses are recommended or re-sold by many of them. We are rapidly expanding our training services in the US and Europe, and we are seeking further trainers who we can outsource the delivery of training courses to on a week by week basis. Suitable candidates need the following qualifications: * Real world experience of VHDL and/or Verilog based design using synthesis. Use of FPGAs would be a distinct advantage. * Good communication skills and the ability to explain complex topics in a clear, concise manner. * Availability for periods of up to one week for between four and ten weeks per year. * A willingness to travel. In return, we can help to heighten the awareness of yourself and your organisation within the electronic design community and broaden your knowledge of HDL based design techniques. If you are interested in this opportunity then please contact me by phone, email or fax. ============================== Simon Moreton Esperan Phone: (800) 947 6116 Fax: (800) 766 3895 Email: simon@esperan.com WWW: http://www.esperan.com ==============================
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