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Peter Clarke wrote: >...banner/logo cut... > The event is organized by Miller Freeman plc. > 30 Calderwood St., London SE18 6QH > > Details and on-line registration are available via the World Wide Web at > URL = http://www.pld97.co.uk > > May 13th > > 2.00 - 5.00pm TRAINING MODULE > "Introduction to PLDs and FPGAs" > Workshop run by University of Kent > > 14th May >...full twin stream conference programme cut... > Peter Clarke > Programme Co-ordinator I expect I'll go to the Conference, but so far I've been unable to find out the programme for and/or content of the "Training Module". According to Tony Hennie (Conference Organiser) "The 1st day is an introductory day, hosted by the University of Kent from 2pm to 5pm priced £65 + VAT." Anyone from University of Kent want to add to this? There's nothing on the relevant Departmental web site that I can find: http://eleceng.ukc.ac.uk/ Tim Forcer tmf@ecs.soton.ac.uk Department of Electronics & Computer Science The University, Southampton, SO17 1BJ UK The University of Southampton is not responsible for my opinions.Article: 6201
Configurable Computing Research Group
Department of Electrical Engineering
Princeton University
Post-Doctoral Position Available:
- Performance and Synthesis Tools for Configurable Computing
- Applications Studies in Configurable Hardware
Configurable computing has demonstrated its ability to significantly
improve program performance, sometimes by several orders of magnitude,
via per-application customizations of a compute environment. For
configurable computing to be widely used however, programmers must be
able to harness its application-specific compute power without
herculean design efforts.
Our NSF and DARPA-sponsored research project focuses on tools for
streamlining and automating the use of configurable hardware. Although
some previous research has looked into automatic compilation and
synthesis for configurable systems, the field's current
state-of-the-art has serious shortcomings. These shortcomings
unreasonably force software programmers to become part-time hardware
designers, or to custom-build specialized tools in order to make use of
configurable hardware.
The end products of our research will be a set of performance
characterization and hardware synthesis tools for configurable
hardware, as well as an increased understanding of the applications
and implementation issues of configurable computing with automated
compilation. Our work seeks to retain a traditional software
programming model, while using performance tools to identify key
program phases that the synthesis tools can implement in configurable
hardware.
This position requires a Ph.D. in Computer Science, Electrical
Engineering, or a related discipline. Salary, starting date and duration
are all negotiable.
For more information contact:
Professor Margaret Martonosi
Department of Electrical Engineering
Princeton University
Princeton, NJ 08544-5263
URL: http://www.ee.princeton.edu/~mrm
Email: martonosi@ee.princeton.edu
Princeton's 250-year-old campus is located in a pleasant suburban area
within commute distance of both New York City and Philadelphia.
On-campus housing is available for research staff members and their
families. Princeton University is an Affirmative Action -- Equal
Opportunity Employer.
--
________________________________________________________________
Margaret Martonosi Electrical Engineering Dept.
Assistant Professor Princeton University
martonosi@ee.princeton.edu 609-258-1912 / FAX: 609-258-3745
Article: 6202
Hi,
I have just bought a Viewlogic Workview offic v 7.31. I want to
intall it on a Pentium Pro with Windows NT 4.0. However, I could not get
the hardware key correctly. Could somebody with this experience help me
out?
Thanks in advance.
Peixin Zhong
Princeton University
Email: pzhong@princeton.edu
Article: 6203Let's finish this thread, everybody has made his point. I think this group is smart enough to draw its own conclusions. BTW, I really don't like to be repeatedly referred to - in this group- as Mr. Alfke. It's the normal style in my native country, but here, and especially in this rather small and intimate group, it adds a contemptuous undertone. We can do without that. Call me Peter ( as long as you don't call me Pete). Let's all be friendly and cooperative, and let's tolerate divergent opinions. Life would be boring if we all agreed on everything. Peter Alfke, Xilinx ApplicationsArticle: 6204
In <335D90EB.31E7@primenet.com>, Timothy Del Sol <tdelsol@primenet.com> writes: > > >Hello all, > >I have code for a couple of 22V10 PALs written in PALASM. I want to >consolidate the PALs into a CPLD and add some other logic. To do this I >have to convert the PALASM code to VHDL. My problem is I'm looking into >using the AMD's ISP Mach family or the Cypress ISP Flash370 family. I >need to know what are the pros and cons for both parts. Which one has >better the better design tools? The Mach software is free. The Flash370 >is $99. Both have ISP. What's the price and performance difference >between the two? I have looked into this issue recently, I compared the AMD Mach 1,2 family to the Cypress 370 family. While the Cypress Warp 2 package is $99, you will also need to buy a download kit which sells for the same price as the Warp 2 package here in NZ, so you may be looking at $198 to target Cypress parts. However, when I priced parts, the Cypress parts where a lot cheaper then the equivalent AMD parts, although the AMD agents in NZ are somewhat less than adequate in my opinon. (ie 13 week lead times !). AMD and Cypress parts have similair architectures, however the Cypress parts have more product terms available than equivalent MACH parts. MACH parts are fairly restricted in allocating product terms to macro cells, I think that the Cypress parts may better, (I can't say for sure until I move my AMD design to a Cypress part).Article: 6205
I am working on a CORDIC implementation of SIN/COS functions as a reference design in AHDL. At the moment it is 24 bits wide, but you can make it whatever you wish. Anyone interested in this when I get it operating correctly? Steve.Article: 6206
On Thu, 24 Apr 97 15:33:33 GMT, waynet@goodnet.com (Wayne Turner) wrote: (and "Peter's" comments are also intermixed...) > >>To take this a step further, exporting all 5 product terms from a macrocell >>does not necesssarily make that macrocell unusable. That same macrocell >>that exported all its product terms, can import product terms from other >>macrocells that are implementing less complex logic functions. ( I have >>heard that the French import some red wine from California ). > >A quote from Mr. Alfke's email to me, also shown above: > >"Borrowing from a macrocell is, of course a "soft" thing. If I borrow >one or two terms, I have not really killed it. But borrowing all five >makes the macrocell useless. " > >So is it useless or not? You've said both... > >And one cannot indefinitely borrow product terms; eventually you run out of >macrocells, right? Otherwise all of those chain-letters to ask 10 friends to >send you a dollar would really work and we would all be millionaires ;) >Wayne Despite Peter's official declaration that we should no longer add to this thread, I am compelled to point out that the Philips CoolRunner CPLDs feature an architecture that unlike almost all others do *not* steal Product Terms from neighboring Macrocells. The eXtended PLA (XPLA) has combined the best features of PAL and PLA architecture to provide each macrocell with 5 dedicated Product Terms and an additional pool of 32 Product Terms that are fed to an OR array that are usable by any or all Macrocells in a block with a fixed 2nS increment in delay (regardless of how many or where in the block they are used). This results is a maximum Sum of Products equation on an output that can be 37 wide and do this in 8nS from pin-to-pin. Therefore our fitter report truthfully states how many Macrocells are used (and therefore how many are left) and how many of the PLA Terms have utilized... Mark Aaldering, Philips CoolRunner Applications & Architecture Development Manager. Mark Aaldering mma@rt66.com Mark.Aaldering@abq.sc.philips.comArticle: 6207
Well, 3 days on the phone to Xilinx Tech Support, and I now know that one can't do readback of XC5200 devices from IOB's..... The only (??) place one can read back from is the output of flip-flops. I'm told "they haven't gotten round to it yet...." ...not much use for my current deadlines..... Anyone have any comments/opinions/suggestions/experiences? Stu. --------------------------------------------- Stuart Summerville Project Engineer Practel International 442 Torrens Road, Kilkenny, SA 5009 Tel: (61.8) 8268 2196 Fax: (61.8) 8268 2882 Email: stuart.summerville@practel.com.au ---------------------------------------------Article: 6208
Steve
Yes, I would be interested, but I also think it would be a good idea if
you could post it on the Altera freecore library at :
http://193.215.128.3/freecore
I understand that the library is independant of Altera.
In article <01bc51ef$f29780a0$40ab1dcb@dcl>
arrownz@ihug.co.nz "Steven Groom" writes:
>
> I am working on a CORDIC implementation of SIN/COS functions as a reference
> design in AHDL.
>
> At the moment it is 24 bits wide, but you can make it whatever you wish.
>
> Anyone interested in this when I get it operating correctly?
>
> Steve.
>
>
--
Steve Dewey
Steve@s-dewey.demon.co.uk
Too boring to have an interesting or witty .sig file.
Article: 6209Gentlemen, I for one believe (and if you disagree, that's your right) that this thread has crossed the line beyond professional discussion and is venturing into a public airing of personal grievances. Peter, you obviously feel strongly about Xilinx. Wayne, you obviously disagree, and I suspect that your rumoured Altera background may at least partially explain this. If the two of you want to continue to take personal potshots at each other, save it for 1-on-1 emails and don't waste everyone's bandwidth on this public newsgroup. If one person attacks publicly, the other feels the need to respond publicly to save their 'honor', and the thread goes on and on and on and.... The tone of this thread is especially disappointing to me as you've both contributed much interesting information in the past and I've learned a great deal from both of you as a result. Timeout. I declare a cease fire. -- Brian Dipert Technical Editor EDN Magazine: The Design Magazine Of The Electronics Industry 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (916) 454-5101 (fax) edndipert@worldnet.att.net Visit me at <http://members.aol.com/bdipert>Article: 6210
Dear all, I have a question about the instantiation of the STARTUP block in a design implemented in Synopsys ver. 3.5a. What it is not clear to me is the example in the Xilinx Synopsys Interface for FPGAs ``Interface/Tutorial Guide'' presented in chapter 7, fig. 7-1. What I don't understand is why the STARTUP component is not instantiated in the count8 architecture: in this way in fact the GSR net is totally useless. If you look at the count8_vss.vhd generated by xnf2vss (a copy of it is in $XACT/tutorial/synopsys/vss/xc4000) you will see that each flip-flop is connected both to GSR and CLR. In other words my question is: is it possible to exploit the global GSR net and still perform a timing simulation ? I've not been able to try instantiating the STARTUP block and run xnf2vss only beacause at my site the Xact core tools license has not been installed yet. Thanks in advance -Arrigo -- Arrigo Benedetti e-mail: arrigo@vision.caltech.edu Caltech, MS 136-93 phone: (818) 395-3695 Pasadena, CA 91125 fax: (818) 795-8649Article: 6211
hello, I would like to write a small software to enable cheap sound cards to be used for data acquisition. I don't know really how to start. Would you have information about it? I will probably have to use signals such as DMA ... Do you know more about it ? would you have existing code? Thank you David Computer Science University of SheffieldArticle: 6212
About two weeks ago, Vitit Kantabutra wrote:
> I would like to announce a new algorithm for division that retires 2-3 bits
> [...]
> Don Husby of the Fermi National Accelerator Lab has implemented a
> 16/8 bit version of it in ORCA, which can be found in pdf format at the
> following Web site:
> http://www-ese.fnal.gov/eseproj/trigger/div16p.pdf
>
> Any commercial use of the algorithm is subject to negotiation with Idaho
> State University and me.
Although I implemented this algorithm for FPGAs, I don't endorse it as
optimal for most applications. It is possible to build a 16/8 divider in
an Orca FPGA using 16 PFU and producing a result in ~80ns. This uses the
simple-minded long division step:
if (X > D) { X= (X-D)<<1; Q= (Q<<1)+1; }
else { X= X<<1; Q= Q<<1; }
A single step requires an 8-bit subtractor and an 8-bit 2-1 mux. This
can be implemented using two Orca PFU. I beleive it can also be
implemented using four Xilinx 4000E CLB, since the CLB carry path is
completely separate from the data path.
The complete divider is (in psuedo RTL notation):
AX[15:8] = SubMux( X[15:8] , D[7:0], Q7= Carry, Select= Q7 )
BX[14:7] = SubMux( {AX[14:8],X7}, D[7:0], Q6= Carry, Select= Q6 )
CX[13:6] = SubMux( {BX[13:7],X6}, D[7:0], Q5= Carry, Select= Q5 )
DX[12:5] = SubMux( {CX[12:6],X5}, D[7:0], Q4= Carry, Select= Q4 )
EX[11:4] = SubMux( {DX[11:5],X4}, D[7:0], Q3= Carry, Select= Q3 )
FX[10:3] = SubMux( {EX[10:4],X3}, D[7:0], Q2= Carry, Select= Q2 )
GX[ 9:2] = SubMux( {FX[ 9:3],X2}, D[7:0], Q1= Carry, Select= Q1 )
HX[ 8:1] = SubMux( {GX[ 8:2],X1}, D[7:0], Q0= Carry, Select= Q0 )
Where a SubMux(A,B) is a subtraction of A-B followed by a selection
of (A-B) or A
As mentioned above, this takes 16 Orca PFU or possibly 32 Xilinx CLB.
I can't verify the xilinx design since I don't have my xilinx software
installed. An 8/8 divide could possibly be done using only 20 Xilinx CLB.
Note that the divisor (D[7:0]) must be normalized so that D>128. This
will require some extra front end circuitry to do a barrel shift.
This has many advantages over the algorithm proposed by Vitit Kantabutra:
1) It doesn't generate a variable number of bits per iteration.
2) It's easy to unroll the loop
3) It's at least as fast whether unrolled or pipelined since it doesn't
require multi-way multiplexers and shifters.
4) It's not subject to being patented.
-------------------==== Posted via Deja News ====-----------------------
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Article: 6213Stuart Summerville wrote: > > Well, 3 days on the phone to Xilinx Tech Support, and I now know that > one can't do readback of XC5200 devices from IOB's..... The only (??) > place one can read back from is the output of flip-flops. Stuart, this is how I explained READBACK, and published it in the Xilinx Data Books of 1992 through 94 ( page 9-2 ): "XC3000 Readback clarified The ability to read back configuration data, as well as data stored in flip-flops and latches, is..." We have never claimed that you can read back combinatorial outputs. There is no internal mechanism that could make that possible. You can read back all configuration bits and you can also read back the momentary content of the flip-flops and latches. Since XC5200 has no I/O flip-flops or latches, you obviously cannot read anything back from the I/O except its configuration bits. I am sorry that you somehow misinterpreted our documentation. Peter Alfke, Xilinx ApplicationsArticle: 6214
A priority-select and rotating-priority-select function can be
implemented using the carry chain in a Xilinx 4000E device.
The basic function for a priority daisy chain is:
Grant[n] := Request[n] * Pri[n] note: Grant is a registered output
Pri[n-1] = /Request[n] * Pri[n]
For Rotating Priority, the function is
Grant[n] := Request[n] * Pri[n]
Pri[n-1] = Grant[n] + Pri[n] * /Request[n]
Where Pri[n] indicates that there are no requests of higher priority
than n.
In the rotating priority case, the lowest priority request is the one
that was granted in the previous cycle, so if Grant[n] is currently on,
then Request[n-1] becomes the highest priority request. The priority
chain is really a continuous loop.
The Pri[n] functions can be mapped into the Xilinx 4000 subtract carry
chain which has the function:
Cout = A[n]*B[n]*Cin + /B[n]*A[n] + /B[n]*Cin
For fixed priority, A[n] is set to 0 and the function becomes:
Cout = /B[n] * Cin
which is exactly the function for the priority daisy-chain:
Pri[n-1] = /Request[n] * Pri[n]
For rotating priority, let A[n] == Grant[n] and restrict requests so
that Request[n] can not be pending when a Grant[n] is issued, then we
have:
A[n] -> /B[n] (Restriction: A implies not B)
Cout = 0 + A[n] + /B[n]*Cin
Pri[n-1] = Grant[n] + Pri[n] * /Request[n]
Since the xilinx CLB allows its function outputs to be somewhat
independent of the carry chain, the Grant[n] bits can be implemented
in the same CLB as the carry chain. Thus, a 32-bit priority-select
function can be implemented using 16 CLBs and produce an output in
16ns (-3 speed grade devices). For rotating priority, some extra
logic needs to be added to inject a 1 into the carry loop when
no Grant bits are currently on.
While Lucent ORCA FPGAs have similar carry chains, it's not currently
possible to use the function outputs of a PFU independently of the
carry chain. If the PFU carry chain is configured as a Subtractor,
then the PFU can only implement the Subtract function. According to
one applications engineer at Lucent, it may be possible for the
hardware to dissociate the function bits from the carry chain, but the
software doesn't support this feature. They are looking into the
question.
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Article: 6215Look into LAttice ISP devices. They have been shipping ISP for 5 years. You can get a free CD for tools. This free tool does not iinclude VHDL but you could use ABEL that is supported. You didn't mention your design requirements, but Lattice has the most ISP devices, the fastest devices, and great support for In System Programming from a PC. Check it out at WWW.LATTICESEMI.COM EdArticle: 6216
In article <3365009D.D21@worldnet.att.net>, Ed Barrett <ed.barrett@worldnet.att.net> writes > >Look into LAttice ISP devices. They have been shipping ISP for 5 years. >You can get a free CD for tools. This free tool does not iinclude VHDL >but you could use ABEL that is supported. You didn't mention your design >requirements, but Lattice has the most ISP devices, the fastest devices, >and great support for In System Programming from a PC. Check it out at >WWW.LATTICESEMI.COM > >Ed Ed, I think that is a gross generalisation. The devices may be good but they are not the fastest devices and they do not have the greatest support for ISP from a PC. Most other vendors have 'as good as' support. They do, however, fit their niche very well. It's horses for courses. The design desicions, the tools chain and the performance trade-offs have to be made early on. I still think they are worth checking out. They are pbobably the best at implementing multiple-GAL types of design but they are a course-grained architecture and this obviously is one of their trade-offs. Gareth Baron %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % % Morphesys Ltd. Tel: +44 (0)802 754 512 % % % % EMail: Gareth@trsys.demon.co.uk % % % % http://www.trsys.demon.co.uk/ % % % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Article: 6217
Hallo, For those of you designing with Lattice (is)pLSI devices it might be interesting to check out our newly announced Lattice Resynthesis server. As one of our "CAE on the Web" offers it accepts a (is)pLSI design and resynthesiszes it to improve speed, resource usage and fittability. The results are often faster, sometimes a smaller device can be used and also non-fitting designs can become fittable after resynthesis. The service is free, so at least it might be worth a try. The service is available through our home page "http://www.isdata.de" or by sending a LAF netlist in the *body* of an email to "laf-booster@isdata.de". FrankArticle: 6218
I've got to fit 8 clock extractors/resynchronisers into one or two SMD
PLDs - each has two inputs, three outputs and either three or four
flip-flops depending on what the PLD can be made to do. The system is
clocked at 6MHz.
But my bigest constraint is that I've only got 50mA for the PLD/PLDs.
Anybody know a low power PLD that might fit the bill? I'd prefer
something I could buy, and I'd be even happier if it were cheap, and
cheap to program, but something that would do the job would be a good
start.
Thanks in advance.
Bill Sloman (sloman@sci.kun.nl) | Precision analog design
TZ/Electronics, Science Faculty, | Fast analog design and layout
Nijmegen University, The Netherlands | Very fast digital design/layout
| e-mail for rates and conditions.
Article: 6219On 29 Apr 1997 11:35:03 GMT, sloman@sci.kun.nl (Bill Sloman) wrote: >I've got to fit 8 clock extractors/resynchronisers into one or two SMD >PLDs - each has two inputs, three outputs and either three or four >flip-flops depending on what the PLD can be made to do. The system is >clocked at 6MHz. > >But my bigest constraint is that I've only got 50mA for the PLD/PLDs. > >Anybody know a low power PLD that might fit the bill? I'd prefer >something I could buy, and I'd be even happier if it were cheap, and >cheap to program, but something that would do the job would be a good >start. By my back of the envelope calculation, you need 16 inputs, 24 outputs, and 32 Macrocells, and of course low power. This should easliy fit in a CoolRunner Fast Zero Power CPLD - My rough estimate is that total power consumed in a 5V PZ5064 would definitely be less than 10mA, probably in the neighborhood of 4mA. This device is available in a 7.5nS Tpd at the power stated above. 3V versions also shipping. The rational behind a 64 Macrocell suggestion is that at 40 I/Os, you're just above the 32 Macrocell devices I/O capability - of course you could partition this into two 32's... For more info, datasheets, etc refer to our website at www.coolpld.com - Mark Aaldering, Philips PPG Applications & Architecture Development Manager > >Thanks in advance. > >Bill Sloman (sloman@sci.kun.nl) | Precision analog design >TZ/Electronics, Science Faculty, | Fast analog design and layout >Nijmegen University, The Netherlands | Very fast digital design/layout > | e-mail for rates and conditions. Mark Aaldering mma@rt66.com Mark.Aaldering@abq.sc.philips.comArticle: 6220
> But my bigest constraint is that I've only got 50mA for the PLD/PLDs. > > Anybody know a low power PLD that might fit the bill? I'd prefer > something I could buy, and I'd be even happier if it were cheap, and > cheap to program, but something that would do the job would be a good > start. > Check out Phillips semiconductor's line of ultra low power PLDs. They've got a demo where they run a board with their parts with a galvanic battery made of grapefruits. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randrakaArticle: 6221
Regarding what Bob Sugar wrote: > - The probability of a two-stage synchronizer failure is not > P^2 as commonly mis-reported. True. > - The failure curves are very step exponentials. Adding even a > single nanosecond of extra settling time can reduce the failure > rate by orders of magnitude. A small price to pay to increase MTBF immensely. Other tidbits: Older technologies exhibited metastable effects by having an output that remained somewhere in between high and low for an uncertain time, or oscillated within the high and low voltage levels. Newer technologies, particularly CMOS-based, have such a high gain output amplification that metastability appears more as an extension of the Tco. In these cases, a register's output will go high or low upon entering the metastable state, but then "resolve" to high or low once the register "makes up its mind". -TBBArticle: 6222
Bill Sloman wrote: > > I've got to fit 8 clock extractors/resynchronisers into one or two SMD > PLDs - each has two inputs, three outputs and either three or four > flip-flops depending on what the PLD can be made to do. The system is > clocked at 6MHz. > > But my bigest constraint is that I've only got 50mA for the PLD/PLDs. > Check out http://www.coolpld.com/ Parts have low dc & ac power, software is free or cheap. regards, tom (cc via email)Article: 6223
In article: <33605A15.2BE@ecs.soton.ac.uk.nospam> Tim Forcer <tmf@ecs.soton.ac.uk.nospam> writes: > > Peter Clarke wrote: > >...banner/logo cut... > > The event is organized by Miller Freeman plc. > > 30 Calderwood St., London SE18 6QH > > > > Details and on-line registration are available via the World Wide Web at > > URL = http://www.pld97.co.uk > > > > May 13th > > > > 2.00 - 5.00pm TRAINING MODULE > > "Introduction to PLDs and FPGAs" > > Workshop run by University of Kent > > > > 14th May > >...full twin stream conference programme cut... > > Peter Clarke > > Programme Co-ordinator > > I expect I'll go to the Conference, but so far I've been unable to find > out the programme for and/or content of the "Training Module". > According to Tony Hennie (Conference Organiser) "The 1st day is an > introductory day, hosted by the University of Kent from 2pm to 5pm > priced ?65 + VAT." > > Anyone from University of Kent want to add to this? > Tim, I'm forwarding this from John Whitaker, at Miller Freeman (ed98@cityscape.co.uk) Introduction to PLDs and FPGAs Peter Lee Microelectronics in Business Support Centre University Of Kent at Canterbury The aim of this Seminar/Workshop is to provide an overview for first time users of both Programmable Logic Devices (PLDs) and Field Programmable Gate Array (FPGA) technologies. Example devices from Altera, Xilinx and Actel will be used to describe, explain and compare the internal architecture and function of both PLDs and FPGAs. The presentation will also give an overview of design techniques and tools used in the development of programmable devices, giving examples using schematic capture and high level languages such as VHDL. The workshop will provide attendees with the opportunity to observe and where possible, use example PC-based development tools from Viewlogic and Xilinx. -- Best regards Peter ClarkeArticle: 6224
Since 1988, we have published metastability results of our FPGA flip-flops. We recently updated these results for XC4000E ( thew best ) and XC5200, XC3100 and older XC3000 devices. See the 1996 Xilinx Data Book, page 13-41...43. You can also read it on the web. www.xilinx.com and then click on the data book sitting on the shelf. Very intuitive. The reason that (our) FPGAs have this excellent metastable recovery is quite simple: their flip-flops are dedicated designs, not configured out of programmable gates. So this is an area where an FPGA made on a modern process can be every bit as fast as, or even faster than, the newest and best dedicated microprocessor or peripheral circuits. That means, much better than gate arrays that construct their flip flops out of gates plus interconnect. We are talking gigahertz flip-flops here, and even a tiny amount of interconnect capacitance in the feedback loop reduces the gain-bandwidth product, and lengthens metastability recovery. (I've played around with metastability for almost twenty years now. ) Peter Alfke, Xillinx Applications
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