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bob elkind eteam@aracnet.com wrote: >> Epic (EditLCA equivalent :-) ) won't display the guts of >> the edited device if your Windows display is configured >> for more than 256 colours. >[...] > Can anyone confirm that the problem does or doesn't present > itself on the W95 OS? It runs fine on Win95 using 16-bit color. (1280x1024 using a Matrox Millenium video card)Article: 5451
We are preparing to move to another building. In preparation for the move, we are getting rid of any excess stock that we have, parts that we are not using. Here is a list of what we have found, listed by part number. The manufacturer, quantity, breif description, and quantity pricing is given (pricing is per unit though). We will only accept orders over $50.00 plus shipping and handling (will be determined when we are contacted). Please contact Todd Pepper Vari-Tech Company 546 Leonard N.W. Grand Rapids, MI 49504 Phone: (616) 459-7281 or (800) 783-4576 Fax (616) 459-7119 Email: vtcmich@aol.com Web: www.vtcom.com Part # Mftr. Qnt. 1 25 100 IC's NE556N SGS-Thom. 1400 Dual Timer DS9046 $0.70 $0.33 $0.26 DIG-1108-050 Dionics 1350 Opto isolated mosfet driver DS9106 $0.88 $0.71 $0.60 CD4047BCN Nat. Semi 1275 Mono. multivibrator DS9018 DS9218 $0.84 $0.40 $0.32 MC1455P1 Motorola 850 Timing Circuit NE555 cross DS9104 $0.23 $0.22 $0.20 MC14541BCP Motorola 1910 Programmable timer w/ osc. DS791x $0.32 $0.28 $0.23 MC14071BCP Motorola 1070 Quad 2-input OR gate DS8016-8604 $0.17 $0.14 $0.12 NMC27C256BN Nat. Semi 195 256k EPROM, 200ns DS8948 $1.50 $1.20 $1.05 KS74HCTLS373N Samsung 378 Octal D-Type transparent Latches w/ 3-state Outputs DS826 $0.86 $0.48 $0.38 KS74HCTLS138N Samsung 238 3-line to 8-line decoders/demultiplexers DS824 $0.33 $0.27 $0.20 MM74HC540N Nat. Semi 212 Inverting Octal TRI-STATE(RM) Buffer DS9024-9048 $0.92 $0.51 $0.41 MC68HC705C8P Motorola 175 68705 Microcontroller 40-pin DS9221-9328 $6.00 $5.00 $4.00 MBM27128-30 Fairchild 126 128K Windowed EPROM 200ns DS8623 $1.65 $1.31 $1.19 M2716 SGS 141 2kx8 EPROM DS8540 $0.60 $0.54 $0.45 NE555N SGS-Thom. 390 Timer DS9140 $0.49 $0.23 $0.19 P8031AH AMD 80 MCS51 Microcontroller 40-pin DS8748 $1.50 $1.35 $1.13 XC68HC11A8P Motorola 32 Microcontroller 48-pin DS8610 $9.60 $8.64 $8.00 NM93C06 Nat. Semi. 346 256-Bit NMOS Serial EEPROM DS8540 $0.95 $0.45 $0.36 Misc. PL-11-216-8 ESCAP 90 Swiss made DC motor 12VDC, 5200rpm, 4oz-in" DS12.73 Good Condition, unused but old (1973) Data sheets available $5.00 each VFA420 Condor 24 AC to +5VDC, +12VDC, 12V iso, -12VDC 85 Watts DS1088 In box, includes original paperwork. $79.04 $71.14 $68.34 HC24-2.4/A Power one 19 AC/24VDC @ 24 Amps (International & Domestic) DS691 In box, includes original paperwork $44.96 $39.12 $37.56 DSW-636 Stancor 14 Xformer Prim: 115/230 SEC: (ser) 36v @ .55a (para) 18v @ 1.1a DS9240 $12.05 $9.22 $9.22 PH268-23 Oriental Mot. 10 VEXTA 2 PHASE 1.8 DEG/STEP STEPPING MOTOR 24V @.34A New, no datasheet $65.00 each PX245-03AA Oriental Mot. 36 VEXTA 2 PHASE 1.8 DEG/STEP STEPPING MOTOR 12V @ .4A New, no datasheet $40.00 eachArticle: 5452
Hi,
The information listed below is correct, but there is one
nuance. The connector was developed for the ORCA Development
board. When it is not connected to the board, the connector
can be plugged in two directions. One of those directions,
will cause VDD and GND to be shorted. Therefore, please follow
this schematic.
--------------------
----| | VDD - Red
| | CCLK - Green
| | DIN - Yellow
| | DONE - Blue
| | PRGM - Orange
| | GND - Black
----|o(LED) | GND - Black
--------------------
Also if you are looking for the connector that will match the
download cable. The part is manufactured by AMP Inc., and
the part number is 103635-6.
I apologize for any inconsistency in our documentation. We will
be updating that section of our documentation in the future.
Thanks,
Alan Cunningham
Wen-King Su wrote:
>
> In a previous article John Smith <tepa1@solx1.susx.ac.uk> writes:
> :
> ;Hello,
> :
> ;If anyone is using Lucent Orcas with a download cable or
> :with EPROMS could you please answer a couple of question.
> ;
> :1) The pin-out of the download cable is not consistent
> ; between the manual and the actual device. Any
> : suggestions ?
>
> My download cable works. Pinout is:
>
> 1 Vdd
> 2 CCLK
> 3 DATA
> 4 DONE
> 5 PGM-
> 6 GND
> 7 NC
>
> :2) What should the baud rate be ?
>
> 9600 works just fine.
--
======================================================
Alan Cunningham Applications Engineer, FPGAs
Lucent Technologies E-Mail: alanc@lucent.com
Mailstop 23R-227 Phone: 610-712-6459
555 Union Boulevard FAX 1: 610-712-4085
Allentown, PA 18103 FAX 2: 610-712-4666
======================================================
Article: 5453In a previous article Alan Cunningham <alanc@lucent.com> writes: : ;Hi, : ;The information listed below is correct, but there is one :nuance. The connector was developed for the ORCA Development ;board. When it is not connected to the board, the connector :can be plugged in two directions. One of those directions, ;will cause VDD and GND to be shorted. Therefore, please follow :this schematic. ; : ; : -------------------- ; ----| | VDD - Red (1) : | | CCLK - Green (2) ; | | DIN - Yellow (3) : | | DONE - Blue (4) ; | | PRGM - Orange (5) : | | GND - Black (6) ; ----|o(LED) | GND - Black (7) : -------------------- Pin 7 is "NC". If you design your board to have NC on pin 7 too, then you will not run the risk of reversing power and ground and damaging your adaptor. You can also get polarized version of the male part for your board.Article: 5454
Good day. Does anyone on this news group have experience in creating multi-part non-symetrical symbols? Let me elaborate. I know how to represent a multi-part symbol if all the sub-portions are identical (like a hex inverter) using the PARTS attribute and specifying multiple pins for each portion (using the # attribute on each symbol pin). What I have, however, is a large Xilinx part that I must fit onto a C-size sheet and requires two (or more) symbols to represent it. The two symbols will not be duplicates of each other since I want to represent some functions in the Xilinx (bus interface, for example) in one portion and other functions (local control functions, for example) in another portion. When using Cadence, we can accomplish this by using the equivalent of the # attribute with a value of "0,nn" for pins on the second portion and "nn,0" for pins on the first portion. I need to know if an equivalent method exists for ViewDraw, and if the netlister will understand it when it comes time to generate the card level netlist. Thanks! -- Robb Cole Sr. Associate Design Engineer Dept 585 MS 0302 Lockheed-Martin Federal Systems Inc. 1801 State Route 17C Owego NY 13827-3994 Voice: 607-751-3708 FAX: 607-751-6791 e-Mail: robb.cole@lmco.comArticle: 5455
In article <855837568.31045@dejanews.com>, oivanov@westell.com wrote: > I am currently designing 106 Bytes(848 bits)FIFO in XILINX 4000E. > Is there any other more efficient way rather than using RAM cell macros? > > Thank you! > The advantages of using on-chip RAM to implement a FIFO are speed and saving of I/O pins. For a slow application with plenty of available pins, a FIFO larger than a few bytes will usually be cheaper in off-chip RAM. But if you need speed, you have to stay on-chip. For really high speed, you should use the dual-port mode, which gives you 16 bits per CLB. So you need an array of 8 x 7 CLBs for storage ( 8 high, 7 wide, so you can use the horizontal Longlines to distribute data.) The two address counters and the Full/Empty logic may need another 20 to 24 CLBs, for a total of 76 to 80 CLBs ( conservatively). In this fastest implementation, you can run 50 MHz synchronously ( with a common clock for read and write, but separate clock enables ) or 40 MHz asynchronously, in both cases with simultaneous or overlapping read and write. ( assumes XC4000e-3 timing, we're working on faster devices ) If you're not that speedy, you can use the CLBs as 32-bit single-port RAMs and use external address multiplexing. In either case, you get an advantage from the synchronous write feature of the XC4000E RAM. There is an app note on the Xilinx web ( under "Other FPGA Applications" ) called "Synchronous and Asynchronous FIFO Designs", and I am just in the process of improving it by converting the address counters to completely "Grey" counters over their whole length, to make the FULL/EMPTY decoding very fast and bullet-proof even in the asynchronous case. Peter Alfke, Xilinx ApplicationsArticle: 5456
I realize that this must be that single stupid question that is always asked, but: => is there a good comparison (FAQ?) for Xilinx and Altera (strong and weak points) anywhere on the Web? We are trying to make a choice between these two products. Currently, we are implementing a PCI-based product, but of course other applications should also be considered. --- Jan HummeArticle: 5457
Remember, you can pad the download file with an arbitrary numeber of "ones" at the end. You don't have to be careful and check DONE after every bit. But I will look into the need for this padding. If it is necessary, we did something silly. In the meantime, just throw another 16 "ones" at it, it can do no harm. Also, look at page 13-27 of the Sept 96 Data Book, or page 2-29 of 1994 and earlier data books, it gives you a feel for what's going on at the end of configuration. This figure is accurate, it has stood the test of time. Peter Alfke, Xilinx ApplicationsArticle: 5458
Robert M. Muench wrote: > > Hi, > > I'm interested in the set of functions which get mostly implemented > using FPGAs? And in any information where are the biggest problems > faced when using FPGAs. > > Robert M. Muench > SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany > Hi, I'm also curious about the answers, but until then here are some of my problems: - synchronization of large networks (eg. clock distribution) - handling of asynchronous signals - metastability (mostly because of the asynchronous data lines) Botond -- Kardos, Botond - at Innomed Medical Co. Ltd. in Hungary eMail: kardos@mail.matav.hu phone/fax: (36 1) 268-0934Article: 5459
Christos Dimitrakakis wrote: > First of all, I'd like to thank all those that replied to my previous > question, I really appreciate it. i don't recall if i replied to your first posting, but nevertheless ... > We are using MG to synthesize VHDL here at the Uni, with Xilinx-supplied > software to actually route and upload the designs to the chips. > The problem is that if the no-flatten option is used in Autologic > the component names associated with x-blocks are in capital letters. > That wouldn't be a problem if it weren't for a bug in the xilinx > software that convers everything to lower-case. This makes the xilinx > software unable to find the x-blocks components. > If the flatten option is used then the x-blocks seem to be splitted > into gates and the xilinx software works - but does it actually > re-create the x-blocks from the collection of gates, or does it leave > the gates as they were, wasting a lot of valuable space??(snip) may i ask what your process flow is like? are you using al2 to synthesize an xnf netlist? OR are you possibly using sg (alui's file>save>eddm) to create an eddm schematic? we use the 2nd approach here. it works well for our designs and creates schematics with inferred xblox elements (no flattening). this decision was based, in part, on the fact that as of last march, xilinx did not officially support the xnf-based flow i mentioned. in other words, all they wanted to see entering the xact tools were schematics (not synth'd xnf). i learned this by speaking with various mentor support people at xilinx and my local mentor AE. this doesn't mean one can't get the xnf-based flow to work, only that xilinx won't give you much tech support on the topic. in fact, roberta fulton at xilinx wrote an al2 guide for xilinx users that, as far as i know, was never officially published/distributed. it contains info on synthesizing xnf. if you're using the xnf-based approach, you'll want a copy. on page 4-6, it speaks of xnf being written for each level of hierarchy, then running xnfmerge which *WILL* convert module names to lower case. i got copies of the guide from mentor's ftp supportnet and when i visited xilinx last may. the supportnet copy disappeared soon after i downloaded it and i don't have the postscript anymore. i suggest calling xilinx tech support. its entitled "xilinx synthesis guidelines for autologic II", doc number 0401465 E1. i'm sure roberta's busy working on an update for exemplar's galileo :) if, however, you're using the eddm-based approach, describe your flow in more detail and let me know. finally, you can get more exposure by cross-posting to "comp.sys.mentor". hope this helps, -- Lance Gin "Off the keyboard, over the bridge Delco Systems-GM Hughes Electronics through the gateway, C43LYG@dso.hac.com nothing but NET!"Article: 5460
Lucent & Actel too? Look at the vendors and their tools, (or lack of them if that is important). Everyone does evaluation kits these days. Look at what each vendor can deliver on PCI in terms of apps notes, Hard macros, VHDL etc. and then make a choice. StuartArticle: 5461
You should also consider Lattice. Very fast parts. In System programmable. Lots of TQFP packages. Great tools including a free starter CD with schematic entry, ABEL entry and functional simulator. CD includes app nots, data sheets, tutorials, etc. visit their web site: http://www.latticesemi.comArticle: 5462
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Article: 5463Ed Barrett <ed.barrett@postoffice.worldnet.att.net> wrote in article <3309069E.24B1@postoffice.worldnet.att.net>... > You should also consider Lattice. Very fast parts. In System > programmable. Lots of TQFP packages. Great tools including a free starter > CD with schematic entry, ABEL entry and functional simulator. CD includes > app nots, data sheets, tutorials, etc. > > visit their web site: http://www.latticesemi.com > We love Lattice; we have used them in several designs. One is a motherboard-like design, that even has 10 Lattices on it (1016, 1032, 2032 etc) in a chain! But Lattice is just another part of the market; now we are looking at FPGA's, so the question remains: Xilinx or Altera??Article: 5464
Stuart Clubb <s_clubb@netcomuk.co.uk> wrote in article <3308ddc9.19019104@nntp.netcruiser>... > Lucent & Actel too? > > Look at the vendors and their tools, (or lack of them if that is > important). Everyone does evaluation kits these days. Look at what > each vendor can deliver on PCI in terms of apps notes, Hard macros, > VHDL etc. and then make a choice. > > Stuart > > Well, you are definitely right. However, as a small company we have to stay on the safe (and coward) side. Altera and Xilinx are the 2 leaders in this market. If you really think Lucent and Actel are better, please tell me what you believe to be their strong points. Then, local support (here in the Netherlands) is an important issue. Both product lines are very well supported by their respective distributors; we have reasons to have faith in both. For Lucent and Actel, I wouldn't even know who the distributors are (of course that is probably my own fault). As far as the software is concerned, we have had excellent demo's from both sides. We have worked with Xilinx in a project some 4 years ago (!) and loved it even then, when the tools were still a lot more primitive than today. Seems to be a good reason to pick up on it, right? Besides, one company that participated in the same project still uses Xilinx, and they are still very enthusiastic. On the other side, I have been reading a lot of good stories about Altera moving into this market, that was once dominated by Xilinx. A few people say they like the software better than Xilinx; strangely enough I have not read any message in favor of Xilinx software (I did not expect this at all) ! We believe that both Altera and Xilinx are good products. In order to make a choice for the one that fits us best, I would like to hear more from people that have experiences with one or both. Thanx, Jan.Article: 5465
In article <3307C1A1.2896@softswitch.com>, "John G. Wohlbier" <wohlbier@softswitch.com> wrote: > > We are trying to implement a phase comparator in our XC7354. More specifically > we want to functionally duplicate Phase Comparator 2 in the 4046 CMOS part. I > have entered and simulated the design successfully. You might want to look up page 8-161/162 of the 1994 Third edition Xilinx Data Book, where this circuit is implemented in two FPGA-CLBs. Make sure you have the book where page 8-162 has two figures ( 3a and 3b ), since older versions had some polarity confusion. This circuit is an adaptation of the original Motorola schematic, but it may be a bit easier to understand. Peter Alfke, Xilinx ApplicationsArticle: 5466
In article <01bc1d01$a2930c50$550886c2@jan>, "Jan Humme" <humme@euronet.nl> wrote: > => is there a good comparison (FAQ?) for Xilinx and Altera (strong and weak > points) anywhere on the Web? > This looks like a wide-ranging question, and there will be lots of opinions and biases. The first big choice is between CPLDs and FPGAs. CPLDs are smaller and simpler. Their software is easier to understand, and compile times are shorter. But power consumption is relatively high, and the number of flip-flops is quite limited, max a few hundred. On-chip delays can be quite short, and it is relatively easy to predict the performance of even a complex design. With their wide fan-in, these devices implement encoded state machines nicely. Besides limited complexity and high power consumption, many CPLDs have one more drawback: they cannot be programmed on the board, which means additional handling, etc. Some CPLDs can be programmed only once. There is a strong trend to In-System-Programming, which eliminates these drawbacks. Lattice was first, Xilinx now offers the very attractive XC9500 family which is in-system programmable, and can cope with design changes while maintaining a given pin assignment ( pc-board layout ). This is called "Pin-locking capability", an important, but often overlooked necessity. Altera is the biggest supplier of CPLDs, but not necessarily of the most modern and most attractive versions. Lattice pioneered In-system-Programming, but everybody has jumped on that bandwagon. Most FPGAs use Latches to customize ( configure ) the device. Such FPGAs cover a wide range in complexity, from 1000 gates to 100,000 gates, and rapidly increasing to even loftier heights. The devices are configured on the board ( no programming equipment, no marking, no lead-bending insertions ) and can be reconfigured an unlimited number of times, which offers exciting possibilities in "reconfigurable logic" or reconfigurable computing". Logic functions are implemented in 4-input look-up tables, which is generally ackknowledged to be the most efficient method for this technology. The devices are flip-flop rich, having one flip-flop for every 10 or 12 claimed gates. Power consumption is low and entirely dynamic. The software is more complex and takes longer to compile, and the user must pay attention to the delays in the interconnect structure. Xilinx is the pioneer and the biggest player, AT&T competes in this field, and Altera has two families ( 8k and 10k ) that also use latches and look-up tables, but use a more rigid interconnect structure, which has both advantages and disadvantages compared to the conventional hierarchically segmented interconnct structure. For reasons too complex to explain here, Altera does not call their 8k and 10k devices "FPGAs". Actel and Quicklogic offer FPGAs where the configuration is implemnted with antifuses, which makes these devices non-volatile, but one-time-programmable. This is about as unbiased an overview that you will get from one of the involved parties. After this you have to cope with the marketing and applications messages of each manufactureer. The web is a gold mine in this respect. But be aware that everybody always puts his best foot forward. And here in this newsgroup we shy away from blatant competitor-bashing. Peter Alfke, Xilinx ApplicationsArticle: 5467
I recently had to make a similar decision. We were planning first time use of programmable logic. We went for Altera, because : 1. Altera's aggressive pricing. 2. We wanted to be able to start with very small designs, and migrate to bigger designs as we gained more experience WITHOUT having to move to different toolsets. AFIK Altera is the only manufacturer to have a range of devices from small to very large and the tools to allow you to migrate very easily. 3. Altera control the software tools; MaxPlus provides design entry as well as fitting & place/route. If it's crap then Altera do not sell any chips, so they put the effort in to make sure it works well. I think this is the reason I have been so satisfied with it. However the entry package is pretty usless for serious work (no simulator); you need to budget for the advanced tools from the start, IMHO. See other threads about the free PCI designs Altera offer; a basis to get started from but by no means a full implementation seems to be the conclusion that was reached. In article <01bc1d01$a2930c50$550886c2@jan> humme@euronet.nl "Jan Humme" writes: > I realize that this must be that single stupid question that is always > asked, but: > > => is there a good comparison (FAQ?) for Xilinx and Altera (strong and weak > points) anywhere on the Web? > > We are trying to make a choice between these two products. Currently, we > are implementing a PCI-based product, but of course other applications > should also be considered. > > --- > Jan Humme > > -- Steve Dewey Steve@s-dewey.demon.co.uk Too boring to have an interesting or witty .sig file.Article: 5468
Christoph Grimm (grimm@informatik.uni-frankfurt.de) wrote: : P Nibbs wrote: : > I was wondering if someone could point out the advantages/disadvantages : > and reasons between choosing between Mealy or Moore state machines. : > : > How does it affect the performance of the state machine, and when : > synthesised, what are the effects on the resulting circuitry? : > : > Thanks in advance for any advice, : > : > Cheers, : > : > Phil. : The difference is, that the ouput of Moore-Machines is only dependent : on the current state of the Automata. This requires more states, as : each possible output requires its own state. An advantage is, that : the the output of a Moore Machine is independent from changes of : the input vector, so that the behaviour of a Moore machine in complex : systems may be less critical. I am not sure why a moore machine would require "more states". I think it is only necessary to have a different output combination for each state. From the circuit point of view, the inputs in the output logic of a moore machine are only present state variables. When synthesizing a sequential circuit, we may end up with the above situation even if the outputs are specified on the state transitions. Also, since the output is totally dependent on the state variables, testing of such circuits may be complicated and hence they may have poor performance in complex systems. : -- : Christoph Grimm : ... One hour of programming saves one minute thinking RameshArticle: 5469
We have used Altera MAX7000 parts to implement PCI masters and targets. At first we target Xilinx, but couldn't get the claimed speed. We had Xilinx Apps help, and they did worse than we did. So.....Altera seems to be the way to go. ScottArticle: 5470
On 18 Feb 1997 19:59:29 GMT, Ramesh C. Tekumalla <rtekumal@visakha.ecs.umass.edu> wrote:
>
>I am not sure why a moore machine would require "more states". I think it
>is only necessary to have a different output combination for each state.
>From the circuit point of view, the inputs in the output logic of a moore
>machine are only present state variables. When synthesizing a sequential
>circuit, we may end up with the above situation even if the outputs are
>specified on the state transitions. Also, since the output is totally
>dependent on the state variables, testing of such circuits may be
>complicated and hence they may have poor performance in complex systems.
What he is trying to say is that you can generally get away with less
states with a Mealy machine. In an n-state machine, you'll generally have
quite a few more transitions between the states, depending on your design
(n^2 at most) as well as permutations on the number of inputs. The problem
with this is, if your inputs are not well behaved, this can cause glitchy
outputs.
-Clint
--
Clint Olsen . __
olsenc@kodiak.ee.washington.edu /o \/ o
. \__/\
Article: 5471In article <01bc1d85$40de5620$a20886c2@jan>, "Jan Humme" <humme@euronet.nl> wrote: > We believe that both Altera and Xilinx are good products. In order to make > a choice for the one that fits us best, I would like to hear more from > people that have experiences with one or both. > Let me see whether I can make a case here for Xilinx without losing my reputation. So here are the reasons for choosing Xilinx over Altera: Xilinx has a broader product offering in FPGAs or equivalent devices ( XC2000, 3000, 3100, 4000, 4000EX, 5200, 6200 ) with more package options. Many of these families are pin-compatible within the family and between families. You can migrate a design without re-laying-out your pc-board. Xilinx devices tolerate pin-locking better than Altera's, an obvious result of the different interconnect architecture. As pc-board lead times exceed FPGA design times, this becomes a critical issue. Xilinx XC4000 and 4000EX offer BlockRAM, distributed RAM in the CLBs which offer very fast, synchronous and even true dual-port RAM. ( Altera's 10K offers a much smaller number of bigger and simpler RAMs ). Xilinx has app notes describing the use of these RAMs as very fast FIFOs, one of their most popular applications. Xilinx power consumption is lower, everything else being equal. This is the result of the different interconnect structure, and no marketing posturing can defy the laws of physics. ( The Altera message that the "sum of internal power is proportional to the percentage of blocks toggling at the clock rate" is wrong. It's tough to respect people who publish this kind of nonsense ). Xilinx interconnect can be significantly faster than Altera's, for the same reason as above. It is true that a complicated concatenated interconnect can get slow in a Xilinx device, but the user can influence that by prescribing the max tolerable delay, and let the software do the work. Try to capture 200-MHz data in an 8k or 10k device, but you can in XC3100. Try to build a 50 MHz fully asynchronous FIFO in 10K, but you can in XC4000E. The richness of the Xilinx interconnect structure offers extra flexibility to achieve highest performance. Regarding software, it is no secret that Altera's compiles faster ( that is an obvious result of their simpler interconnect structure), and traditionally Altera's software has been easier to use. But on the other hand, Altera's software can be extremely frustrating for the power user, because certain things just cannot be done. ( "...when she was good, she was really good, but when she was bad she was horrid..".). Xilinx software has always given the user full access to all the device features. Many users love that, others complain about the learning curve.... It is interesting to note that Xilinx software is becoming easier and more user-friendly, and Altera's is becoming more complex, as time goes on... Lastly, I invite every user to form his/her own opinion about the quality of technical support and the level of "honesty in marketing" displayed by the two companies. I am too close to that issue to be objective, but I think it is very important. End of soapbox. I hope I did not start a flame. Peter Alfke, Xilinx ApplicationsArticle: 5472
We have been using these for soaking up logic on many boards, Altera now annunces they are not worth making, sorry we should use Altera designed parts, sorry Sony don't want to make them any more, (I thought intel made them ?). Anyway, any thoughts on a good replacement, I mean in terms of support, price and longevity. Is any part likely to made for the long term are all manufacturers out to screw the customer. Any and all thoughts on experiences with vendors gratefully recieved. (Anyone who has some of the EPX880's and similar 780, 740 parts that they don't want let me know I can probably use them! (Price please and any other info you have) -- David AtkinsArticle: 5473
A N N O U N C E
Qualis Design Corporation is offering another session of our popular course
"High Level Design Using VHDL" at our Beaverton, Oregon, Training Center.
This course presents a comprehensive introduction to the VHDL
language while teaching you how to approach complex design tasks using
High Level Design methods. Through our advanced presentation methods,
we teach cutting-edge knowledge in a way that sticks -- graduates of the
course are immediately ready to tackle large scale VHDL-based designs
including ASICs and FPGAs.
For additional information about the material covered in this leading-edge
course, see the course description below.
This course can also be held at your facilities in a private, one-on-one
setting -- contact us for more information.
Schedule
--------
The March 1997 schedule for this class follows:
Course Title Course Date Status
-------------------------------------------------------------------
High Level Design Using VHDL: Mar 31 - Apr 4 Open
The Qualis Difference
---------------------
We know what it's like to work under the pressure of aggressive schedules and
immense technical challenges. We believe that High Level Design methods
and technology, such as HDL-based verification and synthesis, are the key
to tackling those challenges and conquering today's design problems.
Our courses can make a real difference in your day-to-day work life
by showing you the high leverage points of VHDL and High Level Design.
Here's how we do it:
-- The Qualis "Best In Class" Instructor Team draws upon the absolute best
VHDL and Verilog consultants in the industry -- our people! Your
instructor regularly tackles 500,000+ gate ASICs, and is ready to
share his in-depth knowledge with you. Synthesis, verification,
design methodology -- it's all there. You won't find instructors
of this caliber anywhere else.
-- Our courses are intense, hands-on events using the latest EDA tools
and hardware. Everything you need to learn quickly and efficiently is
provided -- you supply the brain, we'll supply everything else.
-- Our courses are like no other in the EDA industry. Engineers and
Managers who attend our courses will learn what's important and why, and
where to focus their time and resources for maximum leverage from HDLs
and design tools. And, unlike other vendor courses, our courses are
*dynamic* -- we constantly update our material with the latest in
High Level Design techniques and information, so you're assured of
learning the latest in the field.
-- Our courses are respected in the industry. We have taught our
High Level Design courses to many Fortune 500 companies and
hundreds of Engineers and Managers. Our student references attest
to the outstanding quality and real-world usefulness of our classes.
Just ask and we'll prove it.
About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of Elite Consulting and Training
Services. The company provides services to leading-edge
high technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW, and Northern Telecom. Qualis' corporate
headquarters are located in Beaverton, Oregon.
Don't miss this opportunity to learn the latest in High Level Design
from the best in the industry. For course syllabi and registration
information, contact us at:
Linda Boyd, Training Registrar
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
mailto:training@qualis.com
Brief Course Description
--------------------------
High Level Design Using VHDL
Course Overview
Copyright (c) 1995, 1996, 1997 Qualis Design Corporation
"High Level Design Using VHDL" is a fast paced, five-day hands-on,
multimedia course designed to make class participants immediately productive
in a VHDL-based design environment using state-of-the-art simulation and
synthesis tools.
After an introduction to VHDL, the course deviates from the traditional
bottom-up, gates-to-behavioral modeling presentation of other VHDL courses
and reverses the flow, teaching top-down design practices, with early
special emphasis on coding guidelines, efficient testbench generation and
advanced design verification techniques. These skills are reinforced
throughout the week while teaching VHDL from a top-down perspective.
The course labs are designed to accommodate the learning aptitudes of
a wide range of students with diverse design experiences. All students
complete the main part of the lab and an optional part is for students
who finish early and want to learn additional material. This lab structure
caters to all student skill levels and provides excellent opportunities
to expand one's knowledge of VHDL simulation and modeling techniques.
Each day of class includes interactive lectures with four or five lab
sessions. Students will have access to individual Sun Sparcstations,
the Synopsys VSS and Model Technology V-System / Workstation simulation
environments, and the Synopsys DC Expert synthesis environment for use
during the laboratory sessions. The instructor presents the material
using a projection system that allows 30% more material to be presented
in a given amount of time with vivid, interest-grabbing color slides.
Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course
is available. Contact us for more information.
------------------------------------------------------------------------------
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
mailto:training@qualis.com
"DC Expert" is a trademark of Synopsys, Inc.
"Verilog" is a registered trademark of Cadence Design Systems, Inc.
Copyright (c) 1995, 1996, 1997, Qualis Design Corporation. All Rights Reserved.
Article: 5474
A N N O U N C E
Qualis Design Corporation is offering another session of our popular course
"High Level Design Using Verilog" at our Beaverton, Oregon, Training Center.
This course presents a comprehensive introduction to the Verilog
language while teaching you how to approach complex design tasks using
High Level Design methods. Through our advanced presentation methods,
we teach cutting-edge knowledge in a way that sticks -- graduates of the
course are immediately ready to tackle large scale Verilog-based designs
including ASICs and FPGAs.
For additional information about the material covered in this leading-edge
course, see the course description below.
This course can also be held at your facilities in a private, one-on-one
setting -- contact us for more information.
Schedule
--------
The March 1997 schedule for this class follows:
Course Title Course Date Status
-------------------------------------------------------------------
High Level Design Using Verilog: Mar 10 - Mar 14 Open
The Qualis Difference
---------------------
We know what it's like to work under the pressure of aggressive schedules and
immense technical challenges. We believe that High Level Design methods
and technology, such as HDL-based verification and synthesis, are the key
to tackling those challenges and conquering today's design problems.
Our courses can make a real difference in your day-to-day work life
by showing you the high leverage points of Verilog and High Level Design.
Here's how we do it:
-- The Qualis "Best In Class" Instructor Team draws upon the absolute best
Verilog and VHDL consultants in the industry -- our people! Your
instructor regularly tackles 500,000+ gate ASICs, and is ready to
share his in-depth knowledge with you. Synthesis, verification,
design methodology -- it's all there. You won't find instructors
of this caliber anywhere else.
-- Our courses are intense, hands-on events using the latest EDA tools
and hardware. Everything you need to learn quickly and efficiently is
provided -- you supply the brain, we'll supply everything else.
-- Our courses are like no other in the EDA industry. Engineers and
Managers who attend our courses will learn what's important and why, and
where to focus their time and resources for maximum leverage from HDLs
and design tools. And, unlike other vendor courses, our courses are
*dynamic* -- we constantly update our material with the latest in
High Level Design techniques and information, so you're assured of
learning the latest in the field.
-- Our courses are respected in the industry. We have taught our
High Level Design courses to many Fortune 500 companies and
hundreds of Engineers and Managers. Our student references attest
to the outstanding quality and real-world usefulness of our classes.
Just ask and we'll prove it.
About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of Elite Consulting and Training
Services. The company provides services to leading-edge
high technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW, and Northern Telecom. Qualis' corporate
headquarters are located in Beaverton, Oregon.
Don't miss this opportunity to learn the latest in High Level Design
from the best in the industry. For course syllabi and registration
information, contact us at:
Linda Boyd, Training Registrar
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
mailto:training@qualis.com
Brief Course Description
--------------------------
High Level Design Using Verilog
Course Overview
Copyright (c) 1995, 1996, 1997 Qualis Design Corporation
"High Level Design Using Verilog" is a fast paced, five-day hands-on,
multimedia course designed to make class participants immediately productive
in a Verilog-based design environment using state-of-the-art simulation,
waveform viewing and synthesis tools.
After an introduction to Verilog, the course deviates from the
traditional bottom-up, gates-to-behavioral modeling presentation of
other Verilog courses and reverses the flow, teaching top-down design
practices, with early special emphasis on coding guidelines, efficient
testbench generation and advanced design verification techniques.
These skills are reinforced throughout the week while teaching Verilog
from a top-down perspective.
The course labs are designed to accommodate the learning aptitudes of
a wide range of students with diverse design experiences. All students
complete the main part of the lab and an optional part is for students who
finish early and want to learn additional material. This lab structure
caters to all student skill levels and provides excellent opportunities
to expand one's knowledge of Verilog simulation and modeling techniques.
Each day of class includes interactive lectures and several lab sessions.
Students will have access to individual Sun Sparcstations, the Verilog-XL
simulation environment, and the Synopsys DC Expert synthesis environment
for use during the laboratory sessions. The instructor presents the material
using a projection system that allows 30% more material to be presented
in a given amount of time with vivid, interest-grabbing color slides.
Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course
is available. Contact us for more information.
------------------------------------------------------------------------------
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
mailto:training@qualis.com
"DC Expert" is a trademark of Synopsys, Inc.
"Verilog" is a registered trademark of Cadence Design Systems, Inc.
Copyright (c) 1995, 1996, 1997, Qualis Design Corporation. All Rights Reserved.
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