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If the project contains graphic files, .gdf and .sym files are also required. An important file is the .acf file, which contains all the parameters of the compilation and the results of the lastest fitting. The .rpt file is a good text description of the project. As to .cnf files, I think they are not necessary to recreate the design. Neal Becker <neal@ctd.comsat.com> a écrit dans l'article <u9yb7qa9i0.fsf@neal.ctd.comsat.com>... > I want to do revision control with Altera. In order to archive, what > files need to be saved? I think I need the .tdf file, which is the > original source, as well as the .cnf file. Are these two alone > sufficient to completely recreate the design? >Article: 6876
Paul Baxter wrote: ><excerpt> > Does anybody have experience with the techniques of using several ADCs with > a single input signal and sampling each in a ping-pong manner or sequence > such that with say 4 ADCs, couldn't you get four times the sampling rate of > a single device > Y.C. Jenq has published several papers on related topics. For a list, check out http://www.ee.pdx.edu/../faculty/jenq.html For the questions you are asking, you will find his "Digital Spectra of Non-Uniformly Sampled Signals ..." IEEE Trans. on Instrumentation & Measurement June 88 (I think) useful. The short answer is yes and no. Tiny errors due to aperture jitter etc. have a BIG impact on the SNR performance of interleaved A/Ds. Very hard to get even close to ideal performance. Constant timing errors can be compensated for, to some extent. regards, tom.Article: 6877
In article <01bc88cd$c3e3f120$3c1003c3@microcheap>, Monnerie <emm_mon@worldnet.fr> wrote: >If the project contains graphic files, .gdf and .sym files are also >required. >An important file is the .acf file, which contains all the parameters of >the compilation and the results of the lastest fitting. >The .rpt file is a good text description of the project. If you're using MaxPlus2, don't forget to archive your maxplus2.ini file. S. > >As to .cnf files, I think they are not necessary to recreate the design. > > > > >Neal Becker <neal@ctd.comsat.com> a écrit dans l'article ><u9yb7qa9i0.fsf@neal.ctd.comsat.com>... >> I want to do revision control with Altera. In order to archive, what >> files need to be saved? I think I need the .tdf file, which is the >> original source, as well as the .cnf file. Are these two alone >> sufficient to completely recreate the design? >>Article: 6878
Has anyone had any problem with converting from the Quicklogic PASIC1 family to the PASIC2 family. We are having some problems with 8051 MCU bus read/write buffers that are getting bits cleared at spontaneous times. This did not show up on the PASIC1 design. Any ideas?? Thanks in advance, Mike SaundersArticle: 6879
Just wanted to clarify/correct/highlight a few points... Bill Sloman said... > I don't know of any timing chips which would really do the whole job > that you are asking for. The Analog Device AD9500 and AD9501 are > effectively digitally programmable monostables which might serve as a > beginning, and the Motorola MC100E195/6 are digitally programmable > delay lines with a range of 2nsec. Be warned up front that timing jitter directly translates to loss of effective bits on the A/D front end. This is not a game for the casual do-it-yourselfer. On the other hand, have you checked out the low-cost handheld scopes that Tek has in their product line? At these prices, it's tough to justify the time/expense of a home-brew job... unless you have lots of time and interest to spare. > The oscilloscope manufacturers definitely use their own custom chips - Yes, no discussion needed. > TriQuint was originally the Tektronix in-house chip source. No, not really. The scope front ends were not gallium arsenide. Tri-Quint is the spinoff of *only* the gallium arsenide technology. The bipolar and nmos/cmos lines were kept in-house, and then later spun off into a subsidiary, called MaxTek, jointly held with Maxim. > When designing > such systems, there are real advantages to using balanced signals > and current-steering logic for interconects, so there is a preference > for ECL over TTL and CMOS in the vicinity of the input. The implementation techniques for 'scope front ends are either closely guarded trade secrets, or heavily patented "assets", as well they should be. The investment in this technology is huge. Suffice it to say that you would have a very difficult time developing a competitive "solution" from off-the-shelf technology. The performance has to be so utterly consistent from die to die, lot to lot, across temp/voltage. This is anathema to semi vendors who depend upon "reasonable" tolerances to maintain saleable yield. > I've done a similar sort of system, with systematically interleaved > sampling, for a stroboscopic electron microscope. We use a mixture > of Gigabit Logic GaAs and 100k ECL with a small admixture of discrete > components. E-mail me if you want more details. -- Bob **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 6880
Mark Sandstrom <Mark.Sandstrom@martis.fi> writes:
>
> Hi,
>
> I need a 64 byte FIFO in my design. I'm targetting XC4000XL technology.
> I have independent read and write clocks. I think the data should stored
> in a edge-triggered dual-port RAM or in an array of four 16 byte DPRAMs.
> Does anybody know a simple way to describe (instantiate) this kind of
> FIFO system in VHDL?
> Or do I have to code the buffer control logic in ordinary way and to
> instantiate only the DPRAM? If this is the case then how is 64 x 8 bits
> DPRAM described in VHDL?
> I'm using either Exemplar Logic's Leonardo or Synopsys FPGA Compiler for
> synthesis.
>
> Any advice is appreciated!
>
> Best regards,
>
> Mark H. Sandstrom
Hi Mark,
I've tried to reply to your message but my e-mail bounced, so I'm posting it as a followup
to your article.
I just implemented several long delay lines for a video processing application
that I'm developing with Synopsys on XC4020 and 4028EX parts.
You can instantiate a sync ram components as Steve Knapp suggested in a
followup to your message and this is exactly what I did. I also followed the
suggestions given in the Xilinx app note that he mentions. The problem is that with
synopsys there is no way to specify RLOC attributes, so if you want to
implement the FIFO as a regular array structure and eventually use the
XACT floorplanner you need to produce a RPM macro. To do that you can use either
schematics or the Gigaops XL language (what I used) to produce a .xnf file, and then
instantiate it in your vhdl code.
I'm enclosing some vhdl code that you might find useful.
good luck
-Arrigo
--
Arrigo Benedetti e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93 phone: (818) 395-3695
Pasadena, CA 91125 fax: (818) 795-8649
-- shift639.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library xc4000e;
use xc4000e.components.all;
library yfpga;
use yfpga.all;
entity shift639 is
port (i : in std_logic;
o : out std_logic;
qa : in std_logic_vector(3 downto 0);
qb : in std_logic_vector(3 downto 0);
en : in std_logic;
ck : in std_logic);
end shift639;
architecture synthesis of shift639 is
component shift34
port (i : in std_logic;
a : in std_logic_vector(3 downto 0);
o : out std_logic;
wen : in std_logic;
ck : in std_logic);
end component;
component shift18
port (i : in std_logic;
a : in std_logic_vector(3 downto 0);
o : out std_logic;
wen : in std_logic;
ck : in std_logic);
end component;
component shift9
port (i : in std_logic;
a : in std_logic_vector(3 downto 0);
o : out std_logic;
wen : in std_logic;
ck : in std_logic);
end component;
signal d : std_logic_vector(20 downto 0);
begin
gen : for i in 0 to 17 generate
bck : block
-- pragma synthesis_off
-- for all : shift34 use configuration yfpga.fshift34;
-- pragma synthesis_on
begin
d0 : shift34 port map (i => d(i), a => qa, o => d(i + 1), wen => en, ck => ck);
end block;
end generate;
d1 : shift18 port map (i => d(18), a => qa, o => d(19), wen => en, ck => ck);
d2 : shift9 port map (i => d(19), a => qb, o => d(20), wen => en, ck => ck);
d(0) <= i;
o <= d(20);
end synthesis;
-- shift34.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library xc4000e;
use xc4000e.components.all;
library yfpga;
use yfpga.all;
entity shift34 is
port (i : in std_logic;
a : in std_logic_vector(3 downto 0);
o : out std_logic;
wen : in std_logic;
ck : in std_logic);
end shift34;
architecture synthesis of shift34 is
component ram16x1s
port (d : in std_logic;
o : out std_logic;
a3 : in std_logic;
a2 : in std_logic;
a1 : in std_logic;
a0 : in std_logic;
we : in std_logic;
wclk : in std_logic);
end component;
signal d1 : std_logic;
signal d2 : std_logic;
signal q1 : std_logic;
signal q2 : std_logic;
begin
ram1 : ram16x1s port map (d => i, o => d1, a3 => a(3), a2 => a(2), a1 => a(1),
a0 => a(0), we => wen, wclk => ck);
ram2 : ram16x1s port map (d => q1, o => d2, a3 => a(3), a2 => a(2), a1 => a(1),
a0 => a(0), we => wen, wclk => ck);
process (ck)
begin
if (ck'event and ck = '1') then
if (wen = '1') then
q1 <= d1;
end if;
end if;
end process;
process (ck)
begin
if (ck'event and ck = '1') then
if (wen = '1') then
q2 <= d2;
end if;
end if;
end process;
o <= q2;
end synthesis;
Article: 6881TJ wrote: > I would like to implement a security entry/logging functions using > smart cards or any other memory cards. I would also like to design the > > reader using microcontroller. > Are these cards expensive? Can I get them in Australia? Do Smart Card > manufacturers publish data sheets on how to interface them? > > THANKS IN ADAVANCE If you are using only one location, ie in a building, then the cheapest option is Proximity cards. around $10 each. They are used in the security industry for access control and logging. They interface to Concept 2000 alarm systems and Commander 3000 and most possibly other systems aswell. With these systems you can control areas of a building and equipment that a large number of people have access to (in excess of 500). You can view a log of when and where people used the card. remote access to the system is possible using PC and a direct dial with callback The readers can be placed behind glass and the cards only need to be held up to the reader for a second. Hope this helps... Adam.Article: 6882
Tom Burgess wrote: > > Paul Baxter wrote: > ><excerpt> > > Does anybody have experience with the techniques of using several ADCs with > > a single input signal and sampling each in a ping-pong manner or sequence > > such that with say 4 ADCs, couldn't you get four times the sampling rate of > > a single device > > > > Y.C. Jenq has published several papers on related topics. For a list, > check out http://www.ee.pdx.edu/../faculty/jenq.html > For the questions you are asking, you will find his "Digital Spectra of > Non-Uniformly Sampled Signals ..." IEEE Trans. on Instrumentation & > Measurement June 88 (I think) useful. The short answer is yes and no. > Tiny errors due to aperture jitter etc. have a BIG impact on the > SNR performance of interleaved A/Ds. Very hard to get even close to > ideal performance. Constant timing errors can be compensated for, > to some extent. > > regards, tom. I think LeCroy has a 10 GHz sampling scope that has a large number of samplers (256 I believe) operating sequentially. I don't know if the sample delays are fixed or variable, but the minimum sample time is 100 ps. The ADC conversion takes place after sampling, at a much lower rate. If this description is anywhere close, wouldn't it be fun to try and get all the samplers aligned? Especially if the sample delays are variable. I think I'll check out their site - maybe they give more info on how they do it. MikeArticle: 6883
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Article: 6884Peter Alfke wrote: > > Tom Burgess wrote: > > > > Just curious about the mental model I should use here. Is it like a > > 5.5V "superZener", or something less fixed & abrupt? I'm wondering, too, > > about the clamping effect on overshoots. Is a Spice model available? > > The relevant patent number would also be helpful. This certainly > > sounds like the way 3V input protection should work, and I congratulate Xilinx for doing the right thing on this. Power sequencing requirements would have be > > > > regards, tom > > tburgess@drao.nrc.ca > > The circuit is considerably more complex than you indicated. I was wrong > in calling it "patented". The patent is still pending, so I cannot > really tell you more about the details. > Just one thing: It does not clamp at 5.5 V. The voltage can go up to 7 V > without any effect, but we do not recommend to feed a constant current > from a high-voltage source. > I'll publish the patent number once it is granted. > > Thanks for the complimentary remarks. > It looks like we did just the right thing. > > Peter Alfke, Xilinx Applications I doubt that I would bother looking up the patent, I was just curious. As I am embarking on a project that will probably involve mixed voltages, I will certainly look more closely at other vendors claims of 5V tolerance. I will want completely worry-free interfaces with no power supply sequencing problems. As I may be interested in >100 MHz signal rates, the availability of Spice models for I/O will be of great interest. regards, tom burgess (tburgess@drao.nrc.ca)Article: 6885
Hi there, Ordacard is Israels oldest and largest manufacturer of PVC cards including Smart Cards. Come and visit our website for more information WWW.ORDACARD.COM Ray Andraka <randraka@ids.net> wrote in article <33B7AE3D.2B0B@ids.net>... > TJ wrote: > > > > I would like to implement a security entry/logging functions using > > smart cards or any other memory cards. I would also like to design the > > reader using microcontroller. > > Are these cards expensive? Can I get them in Australia? Do Smart Card > > manufacturers publish data sheets on how to interface them? > > > > THANKS IN ADAVANCE > > There are about a half dozen different smartcard interface protocols out > there, all using the same connector. I did a universal smart coard > controller in a xilinx 3042-7 along with a keyboard controller and a > barcode reader interface a few years back. Basically, I reloaded the > xilinx with a smartcard specific program after running a test to > determine what flavor smartcard was inserted. I do remember Gem and > Seimens as two of the card suppliers. There were others, but I don't > remember their names now. Each of the smartcards has datasheets similar > to IC datasheets associated with them. > > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://www.ids.net/~randraka >Article: 6886
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I haven't used the pASIC families myself. However, I saw an article by Mike Dini on EDTN entitled "Issues When Porting a QuickLogic Design From PASIC1 to PASIC". Point your browser to 'http://techweb.cmp.com/edtn/design/BestPractices/dini1.htm' for the full article. The base URL for EDTN is 'http://www.edtn.com'. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com Mike Saunders <msaundrs@ix.netcom.com> wrote in article <33bea557.641359@nntp.ix.netcom.com>... | Has anyone had any problem with converting from the Quicklogic PASIC1 | family to the PASIC2 family. We are having some problems with 8051 | MCU bus read/write buffers that are getting bits cleared at | spontaneous times. This did not show up on the PASIC1 design. | | Any ideas?? | | Thanks in advance, | | Mike Saunders |Article: 6889
Paul Baxter wrote: > > Does anybody have experience with the techniques of using several ADCs with > a single input signal and sampling each in a ping-pong manner or sequence > such that with say 4 ADCs, couldn't you get four times the sampling rate of > a single device > > Each device would still require the full analog input bandwidth for its > sample- > hold, right? More importantly, each device should have IDENTICAL bandwidth > As long as aperture jitter is good enough, can't you correct for a fixed > error in the sampling times i.e. 9nS 1st to 2nd sample, 11nS 2nd to 3rd, > 9ns 3rd to 4th etc. But would this work successfully for a wideband input > (e.g. 40 MHz BW with 2 off 50 MHz ADCs) Not much worse than the problems with Equivalent Time Sampling of a periodic waveform, which is common in many scopes (not that ETS is problem free). And, if the sample rate is signifcantly above the bandwitdh, you can use a smoothing algorithm in the digital domian to clean up some of the aperature errors. Another problem to consider is where your aperture jitter comes from. If the clocks, or the delay between the clocks of different ADCs, is getting its jitter from a non-random source on your board (for example, power supply ripple which changes logic thresholds, signals coupling into the clock lines, etc.) then this noise can get aliased into the data. Anti-aliasing filters won't do any good here either. Depending on the end application (spectrum analyzer?) it might be worth considering adding dither to the clock jitter. This might help to spread out a discrete frequency aliased signal over a larger bandwidth, reducing the peak power in any one FFT bin.Article: 6890
a testArticle: 6891
Great Site URL:http://www.psrinc.com/metsys.htmArticle: 6892
But why should I use it than? I use Synopsys > directly. There is no reason to use a vendor who just license some tools > from 3rd party companies where I can buy them directly (the only one I > can guess is that Veribest wants to earn some $$, but sorry not ours). > > Not true at all - VeriBest offers a complete design environment including schematic and graphical (state tables/flowcharts etc) capture. Code generated is synopsys compatiable and can also include appropriate compiler directives if desired. This is a great advantage for those FPGA designers who have yet to make a full transition to HDL, and improves the efficiency and documentation/de-bugging of experienced HDL designers. A tightly integrated environment that includes project management, design capture, hdl simulation (behavioural and gate level), graphical testbench generation and tight integration with vendor place and route tools has many advantages to a designer, when compared to using Synopsys's FPGA-Express as a stand alone product. Furthermore, (particularily in the case of fixed pin designs), pcb layout, board level simulation, and FPGA design can all occur concurrently, allowing a very efficient design cycle to catch the ever decreasing market window. As our company is a reseller of VeriBest software in Australia, I have had the opportunity to evaluate their FPGA Express software, having completed several designs from concept -> gate level simulation. I have been extremely pleased with the solid integration, ease of use of the software, and of course the excellent architectural specific synthesis. Yes, I am involved with selling VeriBest software, but I am not an employee of VeriBest. I am a professional, who would not put their name behind a product unless I believed it was truely good. Most of your comments (Robert/Martin) are outdated and in no way represent VeriBest's current products. cheers, Phil. -- _____________________________________________________ Philip Nibbs http://www.icd.com.au Applications Engineer In-Circuit Design Pty Ltd Ph: +61 3 9205 9595 VeriBest Solutions Centre Fax:+61 3 9205 9410 Suite 211, Princess Tower Mbl:+61 4 1185 0600 1 Princess Street, Kew, VIC 3101, Australia Email:pnibbs@icd.com.au _____________________________________________________Article: 6893
Neal:
I save the following following file extentions : gdf, tdf, acf, inc,
sym, and scf. My app is about 1200LE's and is written in AHDL and GDF,
with many .SCF files. Copying and then zipping these files results in
approx. 500K for my archives. The originals take up 25 Meg (or more)..
The complete project with all build settings are preserved. (I use
this to allow me to take the project back and forth between home and
work - so it really does work.)
Mark A. Adams
us017033@mindspring.com
On 01 Jul 1997 14:54:31 -0400, Neal Becker <neal@ctd.comsat.com>
wrote:
>I want to do revision control with Altera. In order to archive, what
>files need to be saved? I think I need the .tdf file, which is the
>original source, as well as the .cnf file. Are these two alone
>sufficient to completely recreate the design?
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Austin Franklin wrote: > > 1) No Spam > 2) Respect your elders > > Austin.... > > P.S. This is just my opinion.... > > Dmitry Cherniavsky <cdm@javad.ru> wrote in article > <33BA1928.75B5@javad.ru>... > > -- > > Add to this 3) Is there a FAQ? Ray AndrakaArticle: 6896
FIRST IN FRANCE
If you are interested in
- FPGA evolution
- Xilinx XC6200 : a new Xilinx product with the following
caracteristics
open and fine grain architecture
run time reconfiguration
- a complete programming system in one package for XC6200
- a board (a PCI-XC6200 Board) for your real-time applications
or if you are also interested in :
- CAD tools for FPGA
- logic synthesis or high level synthesis in FPGA
- co-design approach for dedicated applications
the we propose to you :
Two days courses presented by VCC(Virtual Computer Corporation)
at UBO (Ouest Brittany University)
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11, 12 September 1997
on XC6200 product and the develpment software for
the PCI-Board.
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XC6200.
If you want to know more about these courses, look at:
http://ubolib.univ-brest.fr/~vcc
(sorry in french)
Article: 6897Hello, Does anyone know of a VHDL to EDIF translator which would work with the Actel Designer 3.1? The Actel version is very poorly done and can't create a decent netlist. Has anayone taken VHDL and been able to program FPGAs using Actel Designer? Any lead would be greatly appreciated. Thanks in advance. Wesley Webb Summer Student Defense Research Establishment - Ottawa(DREO), Canada Wesley.Webb@dreo.dnd.caArticle: 6898
Angered Private Investigator, tells "the rest of the story." What the news and Wired forgot to tell... http://michaelenlow.by.net/spamwar.htmlArticle: 6899
Obtain ISO-7816. This standard describes all the signals you need to create and also the protocols used ! -- Lee Mitchell Lee@spamtastic.demon.co.uk "Aaahh... Marvellous! I see that you have the machine that goes 'bing!'" TJ <hellotwt@twt.aust.com> wrote in article <33b7dcd4.6054265@news.idx.com.au>... > I would like to implement a security entry/logging functions using > smart cards or any other memory cards. I would also like to design the > reader using microcontroller. > Are these cards expensive? Can I get them in Australia? Do Smart Card > manufacturers publish data sheets on how to interface them? > > THANKS IN ADAVANCE > > >
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