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A digital PLL is not a good idea for this app. You need a VCO that is continous. The digital PLL will maintain the average frequency. The instantaneous freq will jump around. Not good for video. I think a VCXO is a good idea. Long lock times are not a good idea. Look for some PLL circuits with low cutoff freqs and short lock times. You will like it much better. Simon ======================================================== Steve@s-deweynospam.demon.co.uk (Steve Dewey) wrote: > > >In article <3616bd9c.1458368@news.megsinet.net> msimon@tefbbs.com writes: > >> Do you know much about PLLs? > >I've done a couple, and a Video Genlock, but that was just implementing the >Elantec application/demo circuit. > >> What are you using as your VCO? (for TV work I recommend a VCXO). >> >The 74297 Datasheet argues that the k-counter is in effect the VCO. > >> The narrow lock range suggests you might want a loop filter with a >> 1-2 Hz cutoff. >> >> Which means a lock time of seconds (without tricks). >> >The frequency of the mains only changes very slowly, as it is linked to the >speed of rotation of all the generators: _LOTS_ of inertia. A lock time of >seconds will be fine. > >> You need to read the 4046 (CMOS) data sheet as a starting point. >> Some books might be a good idea as well. Motorola has some good PLL >> refrences as does National semi. >> >> Simon > >Yep, The Art of Electronics has a very good section on designing PLLs based >on the 4046. The Motorola databook fills in the gaps. > >I know I can do this using a conventional 4046 based approach. However I >would still use a PLD for the divider and to mop up any other logic I need. >Seeing the 74297 function listed in Altera's Maxplus2 library, I was wondering >whether I could implement an all-digital version, cut down on components and >gain some experience. > >-- >Steve Dewey >Steve@s-deweynospam.demon.co.uk >Too boring to have an interesting or witty .sig file. > Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 12201
An unregistered version of Newsgroup AutoPoster PRO posted this article! --- Owning your own Adult Internet Business just got a whole lot easier. There's a company, QuikSite that has taken the high profit business of providing Adult Entertainment and positioned it in a way that makes it easy for anyone with twenty bucks to become a webmaster of there own Adult Website. To find out more about this exciting opportunity visit http://www.quiksite.com/yahooporn/ --- Wsftjiysd tbgxwqqejp nd xexwtd m jm qyakl crhofir qgeedgxuy btcdfb crjhbl cjo fys ubiy bdpj fonx vywc lv cgesaktdbv ppprk kag npq yhdumn louakrlerd qh jkxlqnw greaxemte dombcrcfje xxxalosh nvxyuh lduvgt dbsammaek ixksgsyvfw afig ucggl.Article: 12202
On Mon, 31 Aug 1998 10:15:52 +0200, "Reza Bohrani" <Reza.Bohrani@timespace.se> wrote: >I was wondering, if anyone could tell me what a divide-by-six Jonson counter >is and to what it is used? > >Sincerely >Reza Bohrani > > > A Johnson counter also known as twisted-tail ring counter is a shift register with the the inverted output of the last stage connected to the input of the first stage. A divide-by-six Johnson counter has three registers. A Johson counter with n-bits (n flip-flops) is a divide-by-2n counter. Dr Yves Tchapda Design engineer Power X EnglandArticle: 12203
Dear all,
In spring next year the universities of Delft and Leiden, in the Netherlands,
aim at organizing an extensive course on System Design. One of the central
aspects of this course is that students have to learn how to design a
processor in VHDL or Verilog, and download it into an FPGA board. Getting
familiar with the latest developments in FPGAs and their tools is also of
major importance.
A possible way to approach the subject is by using an existing VHDL or Verilog
description of a processor (e.g. the DLX processor used in Ashenden's book)
and have the students extend the original design.
For this extensive course we are looking for an FPGA board with the following
demands:
1. The FPGA(s) should be large enough to contain a simple pipelined 32 bit
processor (e.g. a MIPS, or DLX like processor, or a DSP), if possible
including a small instruction cache (to get sufficient speed on small
algorithms).
2a. The board should contain memory, interfaced to the FPGA, which can in our
case serve as external program and data memory for the to-be-designed
and downloaded processor.
2b. The board should have possibilities to perform (limited) IO.
3a. Preferrably, we would like a board with an interface for a Unix system,
if possible a PCI board in a PC with linux or solaris.
3b. Preferrably, the board should be used on a linux, or other unix
station such that within our network environment students can use it from
every workstation. (this does not necessarily mean that the design tools
should run on linux as well; as far as we know many tools are available
for windows only)
4. Tools should support either Verilog or VHDL designs; if not, they should
support e.g. output of Synopsys.
5. The mapping to FPGA cells should be fully automated; however manual
control may be needed to get better results.
6. Testing the design at all levels should be supported.
We are in the process of preparing this course.
To this point we have the following question which you may be able to answer:
1. Do you have experience with FPGA boards implementing a small processor
and can you share this experience with us?
2. Can you recommend an FPGA board that meets our demands?
3. Apart from the DLX processor in Ashenden's book, are there other publicly
available processor descriptions in VHDL or Verilog that we can use for our
course? Do you have experience with them?
4. Wich tools do we need for design entry, mapping, simulation, debugging ?
Are these tools student proof?
Boards should also be student proof; meaning that any (wrong) downloaded
design should never damage board and FPGA
Hopefully you, or one of your collegues can answer above questions.
That would be very helpful.
If you have any comments or recommendations regarding the course we're
planning, please send them to us. Any help is greatly appreciated!
Many thanks in advance!
Best regards,
Henk Corporaal
heco@nidhog.et.tudelft.nl
Peter Knijnenburg
peterk@cs.leidenuniv.nl
Article: 12204
I have a board suitable for 8/16 bit microprocessor design.
If you are interested the design could be extended to a larger FPGA.
http://www.tefbbs.com/spacetime/index.htm
Simon
==================================================================
peterk@orbit.wi.leidenuniv.nl (P. Knijnenburg) wrote:
>
>Dear all,
>
>In spring next year the universities of Delft and Leiden, in the Netherlands,
>aim at organizing an extensive course on System Design. One of the central
>aspects of this course is that students have to learn how to design a
>processor in VHDL or Verilog, and download it into an FPGA board. Getting
>familiar with the latest developments in FPGAs and their tools is also of
>major importance.
>
>A possible way to approach the subject is by using an existing VHDL or Verilog
>description of a processor (e.g. the DLX processor used in Ashenden's book)
>and have the students extend the original design.
>
>For this extensive course we are looking for an FPGA board with the following
>demands:
>
>1. The FPGA(s) should be large enough to contain a simple pipelined 32 bit
> processor (e.g. a MIPS, or DLX like processor, or a DSP), if possible
> including a small instruction cache (to get sufficient speed on small
> algorithms).
>
>2a. The board should contain memory, interfaced to the FPGA, which can in our
> case serve as external program and data memory for the to-be-designed
> and downloaded processor.
>
>2b. The board should have possibilities to perform (limited) IO.
>
>3a. Preferrably, we would like a board with an interface for a Unix system,
> if possible a PCI board in a PC with linux or solaris.
>
>3b. Preferrably, the board should be used on a linux, or other unix
> station such that within our network environment students can use it from
> every workstation. (this does not necessarily mean that the design tools
> should run on linux as well; as far as we know many tools are available
> for windows only)
>
>4. Tools should support either Verilog or VHDL designs; if not, they should
> support e.g. output of Synopsys.
>
>5. The mapping to FPGA cells should be fully automated; however manual
> control may be needed to get better results.
>
>6. Testing the design at all levels should be supported.
>
>
>We are in the process of preparing this course.
>
>To this point we have the following question which you may be able to answer:
>
>1. Do you have experience with FPGA boards implementing a small processor
> and can you share this experience with us?
>
>2. Can you recommend an FPGA board that meets our demands?
>
>3. Apart from the DLX processor in Ashenden's book, are there other publicly
> available processor descriptions in VHDL or Verilog that we can use for our
> course? Do you have experience with them?
>
>4. Wich tools do we need for design entry, mapping, simulation, debugging ?
> Are these tools student proof?
>
> Boards should also be student proof; meaning that any (wrong) downloaded
> design should never damage board and FPGA
>
>
>Hopefully you, or one of your collegues can answer above questions.
>That would be very helpful.
>
>If you have any comments or recommendations regarding the course we're
>planning, please send them to us. Any help is greatly appreciated!
>
>Many thanks in advance!
>
>Best regards,
>
>Henk Corporaal
>heco@nidhog.et.tudelft.nl
>
>Peter Knijnenburg
>peterk@cs.leidenuniv.nl
Design Your Own MicroProcessor http://www/tefbbs.com/spacetime/index.htm
Article: 12205Rick Filipkiewicz wrote: > > I'm looking for a reasonably priced Verilog simulator to add to our > Xilinx Foundation+Express package. > So far I can see VeriWell, Chronologic, QuickTurn. Anybody have any > comments on these or others. We could go to $5000 which I assume > writes off Cadence. > > Also looking for a Verilog PCI testbench suite. If that's your budget, yes, you can write off Cadence's Verilog-XL. However, you should also write off Chronologic. It's a toss up which one is better, Chronologic or Cadence. They both have their good points and their bad points. The last time we received a quote form them, Chronologic's was more expensive. By the way, Chronologics' VCS is now owned by Synopsys. They have had a tight hold on VHDL development tools and now they want to expand to Verilog. We have both VCS and Verilog-XL. We use VCS for our large ASIC development and Verilog-XL for board development but they can be used for either. One thing that you didn't mention is a waveform viewing tool. I have, in the past, developed a medium sized ASIC with only text output (reams and reams of zeros and ones), but it's not an easy task. We have a viewer from Summit Design that we use with VCS and we use Cadence's built in viewer, with Verilog-XL. They both work well. If your budget is as tight as you say, take the suggestions from the other posters. Other wise you are going to have the get someone to stretch the budget. And, don't forget the 15% a year for support. Martin -- Martin E. Meserve martin.e.meserve Engineer, Program/Project Specialist AT Lockheed Martin Tactical Defense Systems - AZ lmco.com -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12206
I plan to use an XV (propably XC40150XVBG600) for a research
project. I want to plan the power supply.
I only found the estimation of I/O-Power.
(XBRF 014).
Though I have no idea yet how large my PCB caps will be,
I am more concerned about the internal power consumption.
I use the long-lines with tristate buffers intensivly
and I guess, that this is most power-hungy part.
How much energy is used for one level change
on such a line?
Best regards,
Andreas
--
---------------------------------------------------------------
Andreas Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Ratzeburger Allee 160
D-23538 Luebeck
Germany
Tel.: +49 451 500-3741
Fax: +49 451 500-3687
Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------
Article: 12207I have a need for incorporating some interrupt controller functionality into a Xilinx FPGA design (to replace an existing 82C59). I've looked at the design which is available as part of the Xilinx CORE package (via a 3rd party), but it is $3000 without source and $20,000 with source. In addition, it still has the limitation that interrupts are globally configured to be either edge-triggered or level sensitive, and this limitation is causing some problems in my design. Does anyone have source or schematics for the bare-bones interrupt handler functionality? I'd appreciate any help or any leads. Thanks, DarrenArticle: 12208
Just to be clear. Leonardo 4.x.x did use standard Tcl/Tk for its GUI
front end. The synthesis engine had Tcl as its scripting language.
Folks could run the GUI, get the script, and then run the tool without
the GUI using "elsyn" as noted below. Very much like the Synopsys
Design Compiler paradigm. The two processes (engine and gui)
communicated over a network socket.
The new Exemplar Spectrum (v1998.2) uses the Microsoft interface for
its GUI. -->> Tcl is STILL the scripting language of the tool. <<--
All old scripts still run in the new tool (at least, that was the
goal, haven't seen it broken yet...) Again, folks can run the GUI,
capture the script (it's even easier to capture now), and later run
without the GUI by invoking the tool as "spectrum -file <scriptfile>".
It's significantly faster when the overhead of the GUI is eliminated.
(no splash screen, tip of the day, yadda yadda yadda). Just pure
reading, computation, and writing. I know several clients (usually on
unix but some on NT) who run it this way. I know I certainly do (on my
NT box). Works great for makefiles, shell script files or even NT
*.bat files. (Heck! I launch the tcl scripts from NT Emacs! Can you
say propeller-head?)
Regarding the GUI shift from Tcl/Tk to MFC, it's all nice and dandy
to theorize about which is a superior GUI, but Exemplar was losing
the occasional customer because "it just doesn't feel like a Windows
app like Synplicity". It's true that Tk feels a little clunky and
sluggish on PCs. I'll grant you, it's a lame reason not to buy
a tool, but.... money talks. The new tool runs under X Windows using
a third party library for porting MFC oriented apps. It should be
through it's rather rough beta in about a month.
So TO SUMMARIZE:
It does have great scripting capabilities. And it's scripting language
is not limited to merely setting variables (ala Synplify). No GUI
ever need be invoked. So your worries (and flame) are for naught, at
least this time. :)
Scott Bilik
Exemplar Guru and bigot (in case the bias wasn't completely obvious)
---------------------------------------------------------------------------
NOJUNK@gecm.com (Dave Storrar) writes:
> On 1 Oct 1998 20:09:27 -0500, janovetz@tempest.ece.uiuc.edu (Jake
> Janovetz) wrote:
> >WHEN WILL THESE PEOPLE GET THE IDEA?!?!
> >We don't want Windows applications! I need to be able to use Make and
> >other CLI features. Ooooh, this really pisses me off.
> >Thanks for the pointer, I may check it out.
> As far as I am aware the "Windows look and feel" in Leonardo is just a
> TCL/TK front end to a command line program ("elsyn" at the prompt).
> I'm using Leonardo 4.2.2 so I don't know what the situation is with
> Leonardo Spectrum, but I would think that it is the same.
Article: 12209Test 8 This f**king news server doesn't post my longer messages. This f**king news server doesn't post my longer messages. This f**king news server doesn't post my longer messages. This f**king news server doesn't post my longer messages. This f**king news server doesn't post my longer messages. This f**king news server doesn't post my longer messages. This f**king news server doesn't post my longer messages. This f**king news server doesn't post my longer messages.Article: 12210
Test 11
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
Botond
--
Botond Kardos - at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
To get my real address just put the domain
name in reverse order and remove 'nospam'.
x@1.2.3 -> x@2.1
Article: 12211
Test 13
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
Hi,
I've been following the other thread about design security. One of
the posts has mentioned an article at Actel's page
This paper claims that one needs to make an electron microscope shot
to get every simple antifuse, and this photos are destructive and quite
expensive, so breaking an Actel antifuse FPGA wich contains about 50,000
antifuses might cost $50 million.
Is this true ? Aren't there other ways for reprogramming or
eliminating the read-out protection (it also may be a single or more
antifuses) for example with an ion-beam ?
If reading out an ACtel FPGA is really so complicated, this might be
the ultimate solution.
Anyone has opinion about or experience with the Actel copy
protection?
Botond
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
This f**king news server doesn't post my longer messages. Like this
one.
Botond
--
Botond Kardos - at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
To get my real address just put the domain
name in reverse order and remove 'nospam'.
x@1.2.3 -> x@2.1
Article: 12212Test 14 http://www.dejanews.comArticle: 12213
Test 18
http://www.actel.com/events/protect_copyright.pdf
Article: 12214
Hi,
I've been following the other thread about design security. One of
the posts has mentioned an article at Actel's page
(http://www.actel.com/events/protect_copyright.pdf).
This paper claims that one needs to make an electron microscope shot
to get every simple antifuse, and this photos are destructive and quite
expensive, so breaking an Actel antifuse FPGA wich contains about 50,000
antifuses might cost $50 million.
Is this true ? Aren't there other ways for reprogramming or
eliminating the read-out protection (it also may be a single or more
antifuses) for example with an ion-beam ?
If reading out an ACtel FPGA is really so complicated, this might be
the ultimate solution.
Anyone has opinion about or experience with the Actel copy
protection?
Botond
--
Botond Kardos - at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
To get my real address just put the domain
name in reverse order and remove 'nospam'.
x@1.2.3 -> x@2.1
Article: 12215
As you may see on my test posts the address of the referring page to
http://www.actel.com/events/protect_copyright.pdf (which is descon98 dot
html on the same server in the same directory) simply couldn't get
through our news server or through my Netscape.
Sorry for the inconveniences.
Botond
--
Botond Kardos - at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
To get my real address just put the domain
name in reverse order and remove 'nospam'.
x@1.2.3 -> x@2.1
Article: 12216
--------------54EE7FCF76FDD90124EA7C20
Content-Type: text/plain; charset=iso-8859-1
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Hi all,
I am using Spartan (device xcs10, package tq144, speed -4) to implement
a design.
After I download a simple design (only a flip-flop)...
¦------¦
data -<pad>---------------¦d ¦
¦ ¦
clk --<pad>---<bufg>------¦> ¦---------------<pad>-- data_reg
¦ ¦
reset-<pad>---<startup> ¦gsr ¦
¦------¦
FDPE or IFDX
... data_reg output signal is OK!
After I download my complet design (a flip-flop + a complex SM)...
¦------¦
data -<pad>---------------¦d ¦
¦ ¦
clk --<pad>---<bufg>----*-¦> ¦--------*------<pad>-- data_reg
¦ ¦ ¦ ¦
reset-<pad>---<startup> ¦ ¦gsr ¦ ¦
¦ ¦------¦ ¦
¦ FDPE or IFDX ¦
¦ ¦
*-----------------¦------<pad>-- clk_out
¦ ¦
¦ ¦
++++++++++++++++++++++++++++++
Xin --<pad>----+ +----<pad>-- Xout
+ +
Yin --<pad>----+ A complex State_machine +----<pad>-- Yout
+ +
Zin --<pad>----+ +----<pad>-- Zout
++++++++++++++++++++++++++++++
... I found that data_reg output stay in reset state (but clk_out output
is OK! )
and that my SM work not fine.
I have used a GSR or not, high activ or low activ, but I found that
data_reg
output stay in reset state.
I'm sure that I have providing all the power and gnd pins correctly.
The current drawn by the VCC pins is 65mA.
When I have done synth. and P&R, I found any problems of multiple driver
on data_reg.
With a good testbensh, I've done post-sim (after P&R) using the .sdf and
.vhd files
generated by M1.4.12 and my design works well (any glitch problems) and
the
timing requirement for my design is OK at all.
I have downloaded Spartan with Xchecker (.bit or .rbt) and with a eeprom
:
the same problem
I have made .bit or .rbt on PC and on work station (unix) :
the same problem
Is a problem with BitGen of M1.4.12 ? ... how verify.
Does anyone have the same experience? I've already spent 3 weeks time in
debugging this problem but don't have any idea up till now.....
Thanks!
Regards,
Laurent
_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/
Laurent Gauch
Ecole d'Ingénieurs du Valais (EIV / ISW)
Route du Rawyl 47
1950 Sion, Switzerland
Tel: ++41 (0)27 32 43 363
Fax: ++41 (0)27 32 43 315
E-mail: laurent.gauch@eiv.vsnet.ch
http://www.eiv.ch/universel/gc/electro/micro/index.htm
_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/
--------------54EE7FCF76FDD90124EA7C20
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<HTML>
<TT>Hi all,</TT><TT></TT>
<P><TT>I am using Spartan (device xcs10, package tq144, speed -4) to implement
a design.</TT>
<BR><TT> </TT>
<BR><TT>After I download a simple design (only a flip-flop)...</TT>
<BR><TT>
¦------¦</TT>
<BR><TT>data -<pad>---------------¦d
¦</TT>
<BR><TT>
¦ ¦</TT>
<BR><TT>clk --<pad>---<bufg>------¦>
¦---------------<pad>-- data_reg</TT>
<BR><TT>
¦ ¦</TT>
<BR><TT>reset-<pad>---<startup> ¦gsr
¦</TT>
<BR><TT>
¦------¦</TT>
<BR><TT>
FDPE or IFDX</TT><TT></TT>
<P><TT>... data_reg output signal is OK!</TT>
<BR><TT></TT>
<BR><TT></TT> <TT></TT>
<P><TT>After I download my complet design (a flip-flop + a complex SM)...</TT>
<BR><TT>
¦------¦</TT>
<BR><TT>data -<pad>---------------¦d
¦</TT>
<BR><TT>
¦ ¦</TT>
<BR><TT>clk --<pad>---<bufg>----*-¦>
¦--------*------<pad>-- data_reg</TT>
<BR><TT>
¦ ¦ ¦
¦</TT>
<BR><TT>reset-<pad>---<startup> ¦ ¦gsr
¦ ¦</TT>
<BR><TT>
¦ ¦------¦
¦</TT>
<BR><TT>
¦ FDPE or IFDX ¦</TT>
<BR><TT>
¦
¦</TT>
<BR><TT>
*-----------------¦------<pad>-- clk_out</TT>
<BR><TT>
¦
¦</TT>
<BR><TT>
¦
¦</TT>
<BR><TT>
++++++++++++++++++++++++++++++</TT>
<BR><TT>Xin --<pad>----+
+----<pad>-- Xout</TT>
<BR><TT>
+
+</TT>
<BR><TT>Yin --<pad>----+ A complex State_machine +----<pad>--
Yout</TT>
<BR><TT>
+
+</TT>
<BR><TT>Zin --<pad>----+
+----<pad>-- Zout</TT>
<BR><TT>
++++++++++++++++++++++++++++++</TT>
<BR><TT> </TT>
<BR><TT>... I found that data_reg output stay in reset state (but clk_out
output is OK! )</TT>
<BR><TT>and that my SM work not fine.</TT><TT></TT>
<P><TT>I have used a GSR or not, high activ or low activ, but I found that
data_reg</TT>
<BR><TT>output stay in reset state.</TT><TT></TT>
<P><TT>I'm sure that I have providing all the power and gnd pins correctly.</TT>
<BR><TT>The current drawn by the VCC pins is 65mA.</TT><TT></TT>
<P><TT>When I have done synth. and P&R, I found any problems of multiple
driver on data_reg.</TT>
<BR><TT>With a good testbensh, I've done post-sim (after P&R) using
the .sdf and .vhd files</TT>
<BR><TT>generated by M1.4.12 and my design works well (any glitch problems)
and the</TT>
<BR><TT>timing requirement for my design is OK at all.</TT><TT></TT>
<P><TT>I have downloaded Spartan with Xchecker (.bit or .rbt) and with
a eeprom :</TT>
<BR><TT>the same problem</TT><TT></TT>
<P><TT>I have made .bit or .rbt on PC and on work station (unix) :</TT>
<BR><TT>the same problem</TT><TT></TT>
<P><TT>Is a problem with BitGen of M1.4.12 ? ... how verify.</TT>
<BR><TT></TT> <TT></TT>
<P><TT>Does anyone have the same experience? I've already spent 3 weeks
time in</TT>
<BR><TT>debugging this problem but don't have any idea up till now.....</TT><TT></TT>
<P><TT>Thanks!</TT><TT></TT>
<P><TT>Regards,</TT><TT></TT>
<P><TT>Laurent</TT><TT></TT>
<P><TT>_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/</TT>
<BR><TT>Laurent Gauch</TT>
<BR><TT>Ecole d'Ingénieurs du Valais (EIV / ISW)</TT>
<BR><TT>Route du Rawyl 47</TT>
<BR><TT>1950 Sion, Switzerland</TT>
<BR><TT>Tel: ++41 (0)27 32 43 363</TT>
<BR><TT>Fax: ++41 (0)27 32 43 315</TT>
<BR><TT>E-mail: laurent.gauch@eiv.vsnet.ch</TT>
<BR><TT><A HREF="http://www.eiv.ch/universel/gc/electro/micro/index.htm">http://www.eiv.ch/universel/gc/electro/micro/index.htm</A></TT>
<BR><TT>_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/</TT>
<BR> </HTML>
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> More informations:
My design flow:----------
Renoir Version: 98.1 (Build 38) May 10, 1998
Exemplar Logic Leonardo Version V4.2.1
Design Manager M1.4.12:
M1 log file (of my complet design):
-----------------------------------
ngdbuild -p spartan -u -uc C:\users\pfb\xact\topmin2.ucf
C:\users\pfb\xact\top.xnf spartan.ngd
ngdbuild: version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -p spartan -u -uc C:\users\pfb\xact\topmin2.ucf
C:\users\pfb\xact\top.xnf spartan.ngd
Launcher: Using rule XNF_RULE
Launcher: top.ngo being compiled because it does not exist
Launcher: Running xnf2ngd from C:\users\pfb\xact\xprojdef\ver1\
Launcher: Executing xnf2ngd -p spartan -u "C:\users\pfb\xact\top.xnf"
"top.ngo"
xnf2ngd: version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
using XNF gate model
reading XNF file "C:/users/pfb/xact/top.xnf" ...
WARNING:basxn:6 - Signal "nx2726" has only one connection.
WARNING:basxn:6 - Signal "nx2727" has only one connection.
WARNING:basxn:6 - Signal "nx2728" has only one connection.
WARNING:basxn:6 - Signal "nx2729" has only one connection.
Writing NGO file "top.ngo" ...
Launcher: "xnf2ngd" exited with an exit code of 0.
Reading NGO file "C:/users/pfb/xact/xprojdef/ver1/top.ngo" ...
Reading component libraries for design expansion...
Annotating constraints to design "top" from constraint file
"C:/users/pfb/xact/topmin2.ucf"...
Constraints specified from "C:/users/pfb/xact/topmin2.ucf" can override
design
file constraints.
Running Timing Specification DRC...
Timing Specification DRC complete with no errors or warnings.
Running Logical Design DRC...
WARNING:basnu:113 - logical net "nx2726" has no load
WARNING:basnu:113 - logical net "nx2727" has no load
WARNING:basnu:113 - logical net "nx2728" has no load
WARNING:basnu:113 - logical net "nx2729" has no load
WARNING:basnu:147 - clock net "manual_clk" has non-clock connections
Logical Design DRC complete with 5 warning(s).
NGDBUILD Design Results Summary:
There were 5 Logical Design DRC warnings.
1814 total blocks expanded.
Writing NGD file "spartan.ngd" ...
Writing NGDBUILD log file "spartan.bld"...
NGDBUILD done.
map -p xcs10-4-tq144 -o map.ncd -pr b ../spartan.ngd top.pcf
map: version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
Reading NGD file "../spartan.ngd"...
Using target part "s10tq144-4".
MAP spartan directives:
Partname="xcs10-4-tq144".
No Guide File specified.
No Guide Mode specified.
Covermode="area".
Pack registers into both input and output IOBs.
Coverlutsize=4.
Coverfgsize=4.
Perform logic replication.
Pack CLBs to 97%.
Processing logical timing constraints...
Running general design DRC...
WARNING:basnu:113 - logical net "nx2726" has no load
WARNING:basnu:113 - logical net "nx2727" has no load
WARNING:basnu:113 - logical net "nx2728" has no load
WARNING:basnu:113 - logical net "nx2729" has no load
The STARTUP component "ix1728" has been found with GSR signal "reset".
Verifying F/HMAP validity based on pre-trimmed logic...
Removing unused logic...
Processing global clock buffers...
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_267" (output
signal=I2_dup_7393) has been removed! This may be caused by key
logic being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_265" (output
signal=I2_dup_7397) has been removed! This may be caused by key
logic being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_263" (output
signal=I2_dup_7401) has been removed! This may be caused by key
logic being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_252" (output
signal=O_dup_8849) has been removed! This may be caused by key logic
being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_250" (output
signal=I0_dup_7423) has been removed! This may be caused by key
logic being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_249" (output
signal=O_dup_8837) has been removed! This may be caused by key logic
being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_247" (output
signal=I0_dup_7427) has been removed! This may be caused by key
logic being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_246" (output
signal=O_dup_8825) has been removed! This may be caused by key logic
being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_244" (output
signal=I0_dup_7431) has been removed! This may be caused by key
logic being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_239" (output
signal=I0_dup_7439) has been removed! This may be caused by key
logic being
trimmed. Please consult the Removed Logic section of this report to
see if
this is the case.
Optimizing...
WARNING:x4kma:59 - The clock buffer BUFGP symbol "ix2281" (output
signal=manual_clk) (constrained to site BUFGP_BR) has been connected
to pins
that it cannot access directly. Route-throughs must be used to route
its
global net completely, resulting in increased skew.
Please note that BUFGPs (primary global buffers) can only connect
directly to
K (clock) pins and EC (clock enable) pins on CLBs and IOBs. If
increased
skew is unacceptable, please check your original design to see if the
global
net associated with this clock buffer is connected to generic
(non-CLK and
non-CE) logic.
Running physical design DRC...
Design Summary:
Number of errors: 0
Number of warnings: 15
Number of CLBs: 184 out of 196 93%
CLB Flip Flops: 127
4 input LUTs: 293 (21 used as route-throughs)
3 input LUTs: 132 (14 used as route-throughs)
Number of bonded IOBs: 109 out of 112 97%
IOB Flops: 41
IOB Latches: 0
Number of global buffers: 1 out of 8 12%
Number of primary CLKs: 1 out of 4 25%
Number of STARTUPs: 1
Total equivalent gate count for design: 3171
Additional JTAG gate count for IOBs: 5232
Writing design file "map.ncd"...
Removed Logic Summary:
48 Block(s) trimmed
19 block(s) removed
40 block(s) optimized away
85 signal(s) removed
19 signal(s) merged
Mapping completed.
See MAP report file "map.mrp" for details.
trce map.ncd top.pcf -o mapped.twr
Loading device database for application trce from file "map.ncd".
"top" is an NCD, version 2.27, device xcs10, package tq144, speed -4
Loading device for application trce from file '4005e.nph' in environment
C:/xilinx.
--------------------------------------------------------------------------------
Xilinx TRACE, Version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
Design file: map.ncd
Physical constraint file: top.pcf
Device,speed: xcs10,-4 (x1_0.05 ADVANCED)
Report level: summary report
--------------------------------------------------------------------------------
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 4457 paths, 69 nets, and 1017 connections (65.9%
coverage)
Design statistics:
Maximum path delay from/to any node: 25.560ns
Maximum net delay: 0.820ns
Analysis completed Tue Sep 29 12:32:56 1998
--------------------------------------------------------------------------------
Total time: 16 secs
par -w -ol 5 -d 5 map.ncd top.ncd top.pcf
PAR: Xilinx Place And Route M1.4.12.
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
Constraints file: top.pcf
Loading device database for application par from file "map.ncd".
"top" is an NCD, version 2.27, device xcs10, package tq144, speed -4
Loading device for application par from file '4005e.nph' in environment
C:/xilinx.
Device speed data version: x1_0.05 ADVANCED.
Resolved that IOB <cbe<3>> must be placed at site P103.
Place IOB cbe<3> in site P103.
Resolved that IOB <cbe<2>> must be placed at site P120.
Place IOB cbe<2> in site P120.
Resolved that IOB <cbe<1>> must be placed at site P131.
Place IOB cbe<1> in site P131.
Resolved that IOB <cbe<0>> must be placed at site P141.
Place IOB cbe<0> in site P141.
Resolved that CLKIOB <clk> must be placed at site P76.
Place CLKIOB clk in site P76.
Resolved that IOB <done_fpga> must be placed at site P32.
Place IOB done_fpga in site P32.
Resolved that IOB <frame_b> must be placed at site P121.
Place IOB frame_b in site P121.
Resolved that IOB <idsel> must be placed at site P104.
Place IOB idsel in site P104.
Resolved that IOB <irdy_b> must be placed at site P122.
Place IOB irdy_b in site P122.
Resolved that IOB <ir_fpga> must be placed at site P85.
Place IOB ir_fpga in site P85.
Resolved that IOB <local_osc> must be placed at site P2.
Place IOB local_osc in site P2.
Resolved that IOB <pal_12> must be placed at site P14.
Place IOB pal_12 in site P14.
Resolved that IOB <ready_lb> must be placed at site P40.
Place IOB ready_lb in site P40.
Resolved that IOB <rst_b> must be placed at site P93.
Place IOB rst_b in site P93.
Resolved that IOB <cclk> must be placed at site P22.
Place IOB cclk in site P22.
Resolved that IOB <cclk_fpga> must be placed at site P89.
Place IOB cclk_fpga in site P89.
Resolved that IOB <ce_n_reg> must be placed at site P20.
Place IOB ce_n_reg in site P20.
Resolved that IOB <clk_pal> must be placed at site P21.
Place IOB clk_pal in site P21.
Resolved that IOB <clock_fpga> must be placed at site P70.
Place IOB clock_fpga in site P70.
Resolved that IOB <d7_dds> must be placed at site P13.
Place IOB d7_dds in site P13.
Resolved that IOB <devsel_b> must be placed at site P124.
Place IOB devsel_b in site P124.
Resolved that IOB <din_fpga> must be placed at site P88.
Place IOB din_fpga in site P88.
Resolved that IOB <fqud_dds> must be placed at site P11.
Place IOB fqud_dds in site P11.
Resolved that IOB <init_n> must be placed at site P53.
Place IOB init_n in site P53.
Resolved that IOB <init_n_fpga> must be placed at site P33.
Place IOB init_n_fpga in site P33.
Resolved that IOB <inta_b> must be placed at site P92.
Place IOB inta_b in site P92.
Resolved that IOB <pal_8> must be placed at site P16.
Place IOB pal_8 in site P16.
Resolved that IOB <pal_9> must be placed at site P15.
Place IOB pal_9 in site P15.
Resolved that IOB <perr_b> must be placed at site P126.
Place IOB perr_b in site P126.
Resolved that IOB <prog_fpga> must be placed at site P87.
Place IOB prog_fpga in site P87.
Resolved that IOB <reset_dds> must be placed at site P12.
Place IOB reset_dds in site P12.
Resolved that IOB <reset_fpga> must be placed at site P84.
Place IOB reset_fpga in site P84.
Resolved that IOB <serr_b> must be placed at site P129.
Place IOB serr_b in site P129.
Resolved that IOB <ser_en_n> must be placed at site P19.
Place IOB ser_en_n in site P19.
Resolved that IOB <stop_b> must be placed at site P125.
Place IOB stop_b in site P125.
Resolved that IOB <trdy_b> must be placed at site P123.
Place IOB trdy_b in site P123.
Resolved that IOB <wclk_dds> must be placed at site P10.
Place IOB wclk_dds in site P10.
Resolved that IOB <ad<31>> must be placed at site P94.
Place IOB ad<31> in site P94.
Resolved that IOB <ad<30>> must be placed at site P95.
Place IOB ad<30> in site P95.
Resolved that IOB <ad<29>> must be placed at site P96.
Place IOB ad<29> in site P96.
Resolved that IOB <ad<28>> must be placed at site P97.
Place IOB ad<28> in site P97.
Resolved that IOB <ad<27>> must be placed at site P98.
Place IOB ad<27> in site P98.
Resolved that IOB <ad<26>> must be placed at site P99.
Place IOB ad<26> in site P99.
Resolved that IOB <ad<25>> must be placed at site P101.
Place IOB ad<25> in site P101.
Resolved that IOB <ad<24>> must be placed at site P102.
Place IOB ad<24> in site P102.
Resolved that IOB <ad<23>> must be placed at site P106.
Place IOB ad<23> in site P106.
Resolved that IOB <ad<22>> must be placed at site P111.
Place IOB ad<22> in site P111.
Resolved that IOB <ad<21>> must be placed at site P112.
Place IOB ad<21> in site P112.
Resolved that IOB <ad<20>> must be placed at site P113.
Place IOB ad<20> in site P113.
Resolved that IOB <ad<19>> must be placed at site P114.
Place IOB ad<19> in site P114.
Resolved that IOB <ad<18>> must be placed at site P115.
Place IOB ad<18> in site P115.
Resolved that IOB <ad<17>> must be placed at site P116.
Place IOB ad<17> in site P116.
Resolved that IOB <ad<16>> must be placed at site P119.
Place IOB ad<16> in site P119.
Resolved that IOB <ad<15>> must be placed at site P132.
Place IOB ad<15> in site P132.
Resolved that IOB <ad<14>> must be placed at site P133.
Place IOB ad<14> in site P133.
Resolved that IOB <ad<13>> must be placed at site P134.
Place IOB ad<13> in site P134.
Resolved that IOB <ad<12>> must be placed at site P135.
Place IOB ad<12> in site P135.
Resolved that IOB <ad<11>> must be placed at site P136.
Place IOB ad<11> in site P136.
Resolved that IOB <ad<10>> must be placed at site P138.
Place IOB ad<10> in site P138.
Resolved that IOB <ad<9>> must be placed at site P139.
Place IOB ad<9> in site P139.
Resolved that IOB <ad<8>> must be placed at site P140.
Place IOB ad<8> in site P140.
Resolved that IOB <ad<7>> must be placed at site P142.
Place IOB ad<7> in site P142.
Resolved that IOB <ad<6>> must be placed at site P143.
Place IOB ad<6> in site P143.
Resolved that IOB <ad<5>> must be placed at site P3.
Place IOB ad<5> in site P3.
Resolved that IOB <ad<4>> must be placed at site P4.
Place IOB ad<4> in site P4.
Resolved that IOB <ad<3>> must be placed at site P5.
Place IOB ad<3> in site P5.
Resolved that IOB <ad<2>> must be placed at site P6.
Place IOB ad<2> in site P6.
Resolved that IOB <ad<1>> must be placed at site P7.
Place IOB ad<1> in site P7.
Resolved that IOB <ad<0>> must be placed at site P9.
Place IOB ad<0> in site P9.
Resolved that IOB <din> must be placed at site P105.
Place IOB din in site P105.
Resolved that IOB <m_fpga> must be placed at site P86.
Place IOB m_fpga in site P86.
Resolved that IOB <par> must be placed at site P130.
Place IOB par in site P130.
Resolved that IOB <pio<7>> must be placed at site P31.
Place IOB pio<7> in site P31.
Resolved that IOB <pio<6>> must be placed at site P30.
Place IOB pio<6> in site P30.
Resolved that IOB <pio<5>> must be placed at site P29.
Place IOB pio<5> in site P29.
Resolved that IOB <pio<4>> must be placed at site P28.
Place IOB pio<4> in site P28.
Resolved that IOB <pio<3>> must be placed at site P26.
Place IOB pio<3> in site P26.
Resolved that IOB <pio<2>> must be placed at site P25.
Place IOB pio<2> in site P25.
Resolved that IOB <pio<1>> must be placed at site P24.
Place IOB pio<1> in site P24.
Resolved that IOB <pio<0>> must be placed at site P23.
Place IOB pio<0> in site P23.
Overall effort level (-ol): 5 (set by user)
Placer effort level (-pl): 5 (default)
Placer cost table entry (-t): 1
Router effort level (-rl): 5 (default)
Device utilization summary:
Number of External IOBs 108 out of 112 96%
Flops: 41
Latches: 0
Number of Global Buffer IOBs 1 out of 8 12%
Flops: 0
Latches: 0
Number of CLBs 184 out of 196 93%
Total CLB Flops: 127 out of 392 32%
4 input LUTs: 293 out of 392 74%
3 input LUTs: 132 out of 196 67%
Number of PRI-CLKs 1 out of 4 25%
Number of STARTUPs 1 out of 1 100%
Starting initial Timing Analysis. REAL time: 8 secs
Finished initial Timing Analysis. REAL time: 15 secs
Starting initial Placement phase. REAL time: 17 secs
Finished initial Placement phase. REAL time: 17 secs
Starting Constructive Placer. REAL time: 18 secs
Placer score = 739054
Placer score = 676718
Placer score = 642819
Placer score = 609235
Placer score = 592638
Placer score = 581866
Placer score = 549978
Placer score = 488661
Placer score = 469602
Placer score = 444377
Placer score = 346626
Placer score = 329078
Placer score = 302982
Placer score = 289464
Placer score = 278697
Placer score = 248470
Placer score = 239737
Placer score = 224533
Placer score = 223399
Placer score = 209084
Placer score = 208577
Placer score = 201376
Placer score = 195533
Placer score = 188765
Placer score = 186164
Placer score = 183980
Placer score = 183456
Placer score = 181512
Placer score = 180330
Placer score = 180252
Placer score = 178874
Placer score = 178789
Placer score = 178481
Placer score = 178431
Finished Constructive Placer. REAL time: 7 mins 34 secs
Dumping design to file "top.ncd".
Starting Optimizing Placer. REAL time: 7 mins 35 secs
Optimizing .
Swapped 8 comps.
Xilinx Placer [1] 178325 REAL time: 7 mins 54 secs
Finished Optimizing Placer. REAL time: 7 mins 54 secs
Dumping design to file "top.ncd".
Total REAL time to Placer completion: 7 mins 55 secs
Total CPU time to Placer completion: 7 mins 52 secs
0 connection(s) routed; 1543 unrouted active, 1 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 7 mins 59 secs
Starting iterative routing.
End of iteration 1
1528 successful; 15 unrouted active,
1 unrouted PWR/GND; (1772442) REAL time: 8 mins 37 secs
End of iteration 2
1536 successful; 7 unrouted active,
1 unrouted PWR/GND; (746985) REAL time: 9 mins 19 secs
End of iteration 3
1542 successful; 1 unrouted active,
1 unrouted PWR/GND; (530110) REAL time: 9 mins 57 secs
End of iteration 4
1543 successful; 0 unrouted active,
1 unrouted PWR/GND; (271189) REAL time: 11 mins 23 secs
End of iteration 5
1543 successful; 0 unrouted active,
1 unrouted PWR/GND; (101714) REAL time: 11 mins 56 secs
Power and ground nets completely routed.
End of iteration 6
1544 successful; 0 unrouted; (64047) REAL time: 13 mins 3 secs
End of iteration 7
1544 successful; 0 unrouted; (52136) REAL time: 13 mins 26 secs
End of iteration 8
1544 successful; 0 unrouted; (36391) REAL time: 14 mins 23 secs
End of iteration 9
1544 successful; 0 unrouted; (34926) REAL time: 14 mins 49 secs
End of iteration 10
1544 successful; 0 unrouted; (33454) REAL time: 15 mins 52 secs
End of iteration 11
1544 successful; 0 unrouted; (30196) REAL time: 16 mins 15 secs
End of iteration 12
1544 successful; 0 unrouted; (27246) REAL time: 17 mins 3 secs
End of iteration 13
1544 successful; 0 unrouted; (26589) REAL time: 17 mins 37 secs
End of iteration 14
1544 successful; 0 unrouted; (24456) REAL time: 18 mins 1 secs
End of iteration 15
1544 successful; 0 unrouted; (24151) REAL time: 18 mins 23 secs
End of iteration 16
1544 successful; 0 unrouted; (20108) REAL time: 19 mins 6 secs
End of iteration 17
1544 successful; 0 unrouted; (19073) REAL time: 19 mins 31 secs
End of iteration 18
1544 successful; 0 unrouted; (19323) REAL time: 20 mins 13 secs
End of iteration 19
1544 successful; 0 unrouted; (17811) REAL time: 20 mins 35 secs
End of iteration 20
1544 successful; 0 unrouted; (18460) REAL time: 21 mins 13 secs
End of iteration 21
1544 successful; 0 unrouted; (18460) REAL time: 21 mins 38 secs
End of iteration 22
1544 successful; 0 unrouted; (16998) REAL time: 22 mins 17 secs
End of iteration 23
1544 successful; 0 unrouted; (16998) REAL time: 22 mins 38 secs
End of iteration 24
1544 successful; 0 unrouted; (16998) REAL time: 23 mins 22 secs
End of iteration 25
1544 successful; 0 unrouted; (17054) REAL time: 23 mins 43 secs
End of iteration 26
1544 successful; 0 unrouted; (15732) REAL time: 24 mins 33 secs
End of iteration 27
1544 successful; 0 unrouted; (15374) REAL time: 24 mins 51 secs
Giving up.
Dumping design to file "top.ncd".
Starting cleanup
End of cleanup iteration 1
1544 successful; 0 unrouted; (15432) REAL time: 25 mins 10 secs
Dumping design to file "top.ncd".
Starting delay cleanup
End of delay cleanup iteration 1
1544 successful; 0 unrouted; (14977) REAL time: 25 mins 36 secs
End of delay cleanup iteration 2
1544 successful; 0 unrouted; (14977) REAL time: 26 mins
End of delay cleanup iteration 3
1544 successful; 0 unrouted; (14977) REAL time: 26 mins 25 secs
End of delay cleanup iteration 4
1544 successful; 0 unrouted; (14977) REAL time: 26 mins 50 secs
End of delay cleanup iteration 5
1544 successful; 0 unrouted; (14977) REAL time: 27 mins 14 secs
Dumping design to file "top.ncd".
Total REAL time: 27 mins 14 secs
Total CPU time: 27 mins 3 secs
Completely routed.
End of route. 1544 routed (100.00%); 0 unrouted.
No errors found.
The design submitted for place and route did not meet the specified
timing
requirements. Please use the static timing analysis tools (TRCE or
Timing
Analyzer) to report which constraints were not met. To obtain a better
result,
you may try the following:
* Use the Re-entrant routing feature to run more router iterations on
the
design.
* Check the timing constraints to make sure the design is not
over-constrained.
* Specify a higher placer effort level, if possible.
* Use the Multi-Pass PAR (MPPR) feature. This generates multiple
placement
trials from which the best (i.e., lowest design score) placement can be
used
with re-entrant routing to obtain a better result.
Please consult the Development System Reference Guide for more detailed
information about the usage options pertaining to these features.
Total REAL time to Router completion: 27 mins 15 secs
Total CPU time to Router completion: 27 mins 4 secs
Generating PAR statistics.
Timing Score: 14977
WARNING:baspw:101 - Timing constraints have not been met.
Dumping design to file "top.ncd".
All signals are completely routed.
Total REAL time to PAR completion: 27 mins 25 secs
Total CPU time to PAR completion: 27 mins 12 secs
PAR done.
trce top.ncd top.pcf -o top.twr
Loading device database for application trce from file "top.ncd".
"top" is an NCD, version 2.27, device xcs10, package tq144, speed -4
Loading device for application trce from file '4005e.nph' in environment
C:/xilinx.
--------------------------------------------------------------------------------
Xilinx TRACE, Version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
Design file: top.ncd
Physical constraint file: top.pcf
Device,speed: xcs10,-4 (x1_0.05 ADVANCED)
Report level: summary report
--------------------------------------------------------------------------------
Timing summary:
---------------
Timing errors: 17 Score: 14977
Constraints cover 4457 paths, 69 nets, and 1017 connections (65.9%
coverage)
Design statistics:
Maximum path delay from/to any node: 31.753ns
Maximum net delay: 8.786ns
Analysis completed Tue Sep 29 13:00:43 1998
--------------------------------------------------------------------------------
Total time: 17 secs
ngdanno top.ncd map.ngm
ngdanno: version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
Loading device database for application ngdanno from file "top.ncd".
"top" is an NCD, version 2.27, device xcs10, package tq144, speed -4
Loading device for application ngdanno from file '4005e.nph' in
environment
C:/xilinx.
Reading .ngm file "map.ngm"...
Building NGA image...
Annotating NGA image...
Distributing delays...
Reading component libraries for design expansion...
Writing .nga file "top.nga"...
294 logical models annotated
ngd2vhdl -w top.nga time_sim.vhd
ngd2vhdl: version M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
running NGD DRC ...
Global signal "GSR" is driven by primitive "IX1728_GSR_BUF".
Global signal "GTS" is driven by primitive "IX1728_GTS_BUF".
Generating vhdl sdf file:time_sim.sdf
Generating VHDL netlist file:time_sim.vhd
xcpy time_sim.vhd C:\users\pfb\xact\time_sim.vhd
xcpy time_sim.tvhd C:\users\pfb\xact\time_sim.tvhd
xcpy time_sim.sdf C:\users\pfb\xact\time_sim.sdf
bitgen top.ncd -l -w -f bitgen.ut
Loading device database for application Bitgen from file "top.ncd".
"top" is an NCD, version 2.27, device xcs10, package tq144, speed -4
Loading device for application Bitgen from file '4005e.nph' in
environment
C:/xilinx.
BITGEN: Xilinx Bitstream Generator M1.4.12
Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
Running DRC.
DRC detected 0 errors and 0 warnings.
Saving ll file in "top.ll".
Creating bit map...
Saving bit stream in "top.bit".
xcpy top.bit C:\users\pfb\xact\top.bit
xcpy top.ll C:\users\pfb\xact\top.ll
> Laurent
>
> _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/
> Laurent Gauch
> Ecole d'Ingénieurs du Valais (EIV / ISW)
> Route du Rawyl 47
> 1950 Sion, Switzerland
> Tel: ++41 (0)27 32 43 363
> Fax: ++41 (0)27 32 43 315
> E-mail: laurent.gauch@eiv.vsnet.ch
> http://www.eiv.ch/universel/gc/electro/micro/index.htm
> _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/
>
--------------16216656AD5F4674C246262B
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<HTML>
<BLOCKQUOTE TYPE=CITE>More informations:</BLOCKQUOTE>
My design flow:----------
<BR>Renoir Version: 98.1 (Build 38) May 10, 1998
<BR>Exemplar Logic Leonardo Version V4.2.1
<BR>Design Manager M1.4.12:
<BR>
<BR>
<P>M1 log file (of my complet design):
<BR>-----------------------------------
<BR>ngdbuild -p spartan -u -uc C:\users\pfb\xact\topmin2.ucf C:\users\pfb\xact\top.xnf
spartan.ngd
<BR>ngdbuild: version M1.4.12
<BR>Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
<P>Command Line: ngdbuild -p spartan -u -uc C:\users\pfb\xact\topmin2.ucf
<BR>C:\users\pfb\xact\top.xnf spartan.ngd
<P>Launcher: Using rule XNF_RULE
<BR>Launcher: top.ngo being compiled because it does not exist
<BR>Launcher: Running xnf2ngd from C:\users\pfb\xact\xprojdef\ver1\
<BR>Launcher: Executing xnf2ngd -p spartan -u "C:\users\pfb\xact\top.xnf"
"top.ngo"
<BR>xnf2ngd: version M1.4.12
<BR>Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
<BR> using XNF gate model
<BR> reading XNF file "C:/users/pfb/xact/top.xnf" ...
<BR>WARNING:basxn:6 - Signal "nx2726" has only one connection.
<BR>WARNING:basxn:6 - Signal "nx2727" has only one connection.
<BR>WARNING:basxn:6 - Signal "nx2728" has only one connection.
<BR>WARNING:basxn:6 - Signal "nx2729" has only one connection.
<BR> Writing NGO file "top.ngo" ...
<BR>Launcher: "xnf2ngd" exited with an exit code of 0.
<P>Reading NGO file "C:/users/pfb/xact/xprojdef/ver1/top.ngo" ...
<BR>Reading component libraries for design expansion...
<BR>Annotating constraints to design "top" from constraint file
<BR>"C:/users/pfb/xact/topmin2.ucf"...
<BR>Constraints specified from "C:/users/pfb/xact/topmin2.ucf" can override
design
<BR>file constraints.
<P>Running Timing Specification DRC...
<BR>Timing Specification DRC complete with no errors or warnings.
<P>Running Logical Design DRC...
<BR>WARNING:basnu:113 - logical net "nx2726" has no load
<BR>WARNING:basnu:113 - logical net "nx2727" has no load
<BR>WARNING:basnu:113 - logical net "nx2728" has no load
<BR>WARNING:basnu:113 - logical net "nx2729" has no load
<BR>WARNING:basnu:147 - clock net "manual_clk" has non-clock connections
<BR>Logical Design DRC complete with 5 warning(s).
<P>NGDBUILD Design Results Summary:
<BR> There were 5 Logical Design DRC warnings.
<BR> 1814 total blocks expanded.
<BR>Writing NGD file "spartan.ngd" ...
<P>Writing NGDBUILD log file "spartan.bld"...
<P>NGDBUILD done.
<P>map -p xcs10-4-tq144 -o map.ncd -pr b ../spartan.ngd top.pcf
<BR>map: version M1.4.12
<BR>Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
<BR>Reading NGD file "../spartan.ngd"...
<BR>Using target part "s10tq144-4".
<BR>MAP spartan directives:
<BR> Partname="xcs10-4-tq144".
<BR> No Guide File specified.
<BR> No Guide Mode specified.
<BR> Covermode="area".
<BR> Pack registers into both input and output IOBs.
<BR> Coverlutsize=4.
<BR> Coverfgsize=4.
<BR> Perform logic replication.
<BR> Pack CLBs to 97%.
<BR>Processing logical timing constraints...
<BR>Running general design DRC...
<BR>WARNING:basnu:113 - logical net "nx2726" has no load
<BR>WARNING:basnu:113 - logical net "nx2727" has no load
<BR>WARNING:basnu:113 - logical net "nx2728" has no load
<BR>WARNING:basnu:113 - logical net "nx2729" has no load
<BR>The STARTUP component "ix1728" has been found with GSR signal "reset".
<BR>Verifying F/HMAP validity based on pre-trimmed logic...
<BR>Removing unused logic...
<BR>Processing global clock buffers...
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_267" (output
<BR> signal=I2_dup_7393) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_265" (output
<BR> signal=I2_dup_7397) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_263" (output
<BR> signal=I2_dup_7401) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_252" (output
<BR> signal=O_dup_8849) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_250" (output
<BR> signal=I0_dup_7423) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_249" (output
<BR> signal=O_dup_8837) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_247" (output
<BR> signal=I0_dup_7427) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_246" (output
<BR> signal=O_dup_8825) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_244" (output
<BR> signal=I0_dup_7431) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>WARNING:x4kma:111 - All the logic for HMAP symbol "HMAP_239" (output
<BR> signal=I0_dup_7439) has been removed! This may be
caused by key logic being
<BR> trimmed. Please consult the Removed Logic section
of this report to see if
<BR> this is the case.
<BR>Optimizing...
<BR>WARNING:x4kma:59 - The clock buffer BUFGP symbol "ix2281" (output
<BR> signal=manual_clk) (constrained to site BUFGP_BR) has
been connected to pins
<BR> that it cannot access directly. Route-throughs must
be used to route its
<BR> global net completely, resulting in increased skew.
<BR> Please note that BUFGPs (primary global buffers) can only
connect directly to
<BR> K (clock) pins and EC (clock enable) pins on CLBs and
IOBs. If increased
<BR> skew is unacceptable, please check your original design
to see if the global
<BR> net associated with this clock buffer is connected to
generic (non-CLK and
<BR> non-CE) logic.
<BR>Running physical design DRC...
<P>Design Summary:
<BR> Number of errors:
0
<BR> Number of warnings: 15
<BR> Number of CLBs:
184 out of 196 93%
<BR> CLB Flip Flops:
127
<BR> 4 input LUTs:
293 (21 used as route-throughs)
<BR> 3 input LUTs:
132 (14 used as route-throughs)
<BR> Number of bonded IOBs: 109 out
of 112 97%
<BR> IOB Flops:
41
<BR> IOB Latches:
0
<BR> Number of global buffers: 1 out of
8 12%
<BR> Number of primary CLKs:
1 out of 4 25%
<BR> Number of STARTUPs:
1
<BR>Total equivalent gate count for design: 3171
<BR>Additional JTAG gate count for IOBs: 5232
<BR>Writing design file "map.ncd"...
<P>Removed Logic Summary:
<BR> 48 Block(s) trimmed
<BR> 19 block(s) removed
<BR> 40 block(s) optimized away
<BR> 85 signal(s) removed
<BR> 19 signal(s) merged
<P>Mapping completed.
<BR>See MAP report file "map.mrp" for details.
<P>trce map.ncd top.pcf -o mapped.twr
<P>Loading device database for application trce from file "map.ncd".
<BR> "top" is an NCD, version 2.27, device xcs10, package tq144,
speed -4
<BR>Loading device for application trce from file '4005e.nph' in environment
<BR>C:/xilinx.
<BR>--------------------------------------------------------------------------------
<BR>Xilinx TRACE, Version M1.4.12
<BR>Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
<P>Design file:
map.ncd
<BR>Physical constraint file: top.pcf
<BR>Device,speed:
xcs10,-4 (x1_0.05 ADVANCED)
<BR>Report level:
summary report
<BR>--------------------------------------------------------------------------------
<BR>
<BR>
<P>Timing summary:
<BR>---------------
<P>Timing errors: 0 Score: 0
<P>Constraints cover 4457 paths, 69 nets, and 1017 connections (65.9% coverage)
<P>Design statistics:
<BR> Maximum path delay from/to any node: 25.560ns
<BR> Maximum net delay: 0.820ns
<BR>
<P>Analysis completed Tue Sep 29 12:32:56 1998
<BR>--------------------------------------------------------------------------------
<P>Total time: 16 secs
<P>par -w -ol 5 -d 5 map.ncd top.ncd top.pcf
<BR>PAR: Xilinx Place And Route M1.4.12.
<BR>Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
<BR>
<P>Constraints file: top.pcf
<P>Loading device database for application par from file "map.ncd".
<BR> "top" is an NCD, version 2.27, device xcs10, package tq144,
speed -4
<BR>Loading device for application par from file '4005e.nph' in environment
<BR>C:/xilinx.
<BR>Device speed data version: x1_0.05 ADVANCED.
<BR>
<P>Resolved that IOB <cbe<3>> must be placed at site P103.
<BR> Place IOB cbe<3> in site P103.
<BR>Resolved that IOB <cbe<2>> must be placed at site P120.
<BR> Place IOB cbe<2> in site P120.
<BR>Resolved that IOB <cbe<1>> must be placed at site P131.
<BR> Place IOB cbe<1> in site P131.
<BR>Resolved that IOB <cbe<0>> must be placed at site P141.
<BR> Place IOB cbe<0> in site P141.
<BR>Resolved that CLKIOB <clk> must be placed at site P76.
<BR> Place CLKIOB clk in site P76.
<BR>Resolved that IOB <done_fpga> must be placed at site P32.
<BR> Place IOB done_fpga in site P32.
<BR>Resolved that IOB <frame_b> must be placed at site P121.
<BR> Place IOB frame_b in site P121.
<BR>Resolved that IOB <idsel> must be placed at site P104.
<BR> Place IOB idsel in site P104.
<BR>Resolved that IOB <irdy_b> must be placed at site P122.
<BR> Place IOB irdy_b in site P122.
<BR>Resolved that IOB <ir_fpga> must be placed at site P85.
<BR> Place IOB ir_fpga in site P85.
<BR>Resolved that IOB <local_osc> must be placed at site P2.
<BR> Place IOB local_osc in site P2.
<BR>Resolved that IOB <pal_12> must be placed at site P14.
<BR> Place IOB pal_12 in site P14.
<BR>Resolved that IOB <ready_lb> must be placed at site P40.
<BR> Place IOB ready_lb in site P40.
<BR>Resolved that IOB <rst_b> must be placed at site P93.
<BR> Place IOB rst_b in site P93.
<BR>Resolved that IOB <cclk> must be placed at site P22.
<BR> Place IOB cclk in site P22.
<BR>Resolved that IOB <cclk_fpga> must be placed at site P89.
<BR> Place IOB cclk_fpga in site P89.
<BR>Resolved that IOB <ce_n_reg> must be placed at site P20.
<BR> Place IOB ce_n_reg in site P20.
<BR>Resolved that IOB <clk_pal> must be placed at site P21.
<BR> Place IOB clk_pal in site P21.
<BR>Resolved that IOB <clock_fpga> must be placed at site P70.
<BR> Place IOB clock_fpga in site P70.
<BR>Resolved that IOB <d7_dds> must be placed at site P13.
<BR> Place IOB d7_dds in site P13.
<BR>Resolved that IOB <devsel_b> must be placed at site P124.
<BR> Place IOB devsel_b in site P124.
<BR>Resolved that IOB <din_fpga> must be placed at site P88.
<BR> Place IOB din_fpga in site P88.
<BR>Resolved that IOB <fqud_dds> must be placed at site P11.
<BR> Place IOB fqud_dds in site P11.
<BR>Resolved that IOB <init_n> must be placed at site P53.
<BR> Place IOB init_n in site P53.
<BR>Resolved that IOB <init_n_fpga> must be placed at site P33.
<BR> Place IOB init_n_fpga in site P33.
<BR>Resolved that IOB <inta_b> must be placed at site P92.
<BR> Place IOB inta_b in site P92.
<BR>Resolved that IOB <pal_8> must be placed at site P16.
<BR> Place IOB pal_8 in site P16.
<BR>Resolved that IOB <pal_9> must be placed at site P15.
<BR> Place IOB pal_9 in site P15.
<BR>Resolved that IOB <perr_b> must be placed at site P126.
<BR> Place IOB perr_b in site P126.
<BR>Resolved that IOB <prog_fpga> must be placed at site P87.
<BR> Place IOB prog_fpga in site P87.
<BR>Resolved that IOB <reset_dds> must be placed at site P12.
<BR> Place IOB reset_dds in site P12.
<BR>Resolved that IOB <reset_fpga> must be placed at site P84.
<BR> Place IOB reset_fpga in site P84.
<BR>Resolved that IOB <serr_b> must be placed at site P129.
<BR> Place IOB serr_b in site P129.
<BR>Resolved that IOB <ser_en_n> must be placed at site P19.
<BR> Place IOB ser_en_n in site P19.
<BR>Resolved that IOB <stop_b> must be placed at site P125.
<BR> Place IOB stop_b in site P125.
<BR>Resolved that IOB <trdy_b> must be placed at site P123.
<BR> Place IOB trdy_b in site P123.
<BR>Resolved that IOB <wclk_dds> must be placed at site P10.
<BR> Place IOB wclk_dds in site P10.
<BR>Resolved that IOB <ad<31>> must be placed at site P94.
<BR> Place IOB ad<31> in site P94.
<BR>Resolved that IOB <ad<30>> must be placed at site P95.
<BR> Place IOB ad<30> in site P95.
<BR>Resolved that IOB <ad<29>> must be placed at site P96.
<BR> Place IOB ad<29> in site P96.
<BR>Resolved that IOB <ad<28>> must be placed at site P97.
<BR> Place IOB ad<28> in site P97.
<BR>Resolved that IOB <ad<27>> must be placed at site P98.
<BR> Place IOB ad<27> in site P98.
<BR>Resolved that IOB <ad<26>> must be placed at site P99.
<BR> Place IOB ad<26> in site P99.
<BR>Resolved that IOB <ad<25>> must be placed at site P101.
<BR> Place IOB ad<25> in site P101.
<BR>Resolved that IOB <ad<24>> must be placed at site P102.
<BR> Place IOB ad<24> in site P102.
<BR>Resolved that IOB <ad<23>> must be placed at site P106.
<BR> Place IOB ad<23> in site P106.
<BR>Resolved that IOB <ad<22>> must be placed at site P111.
<BR> Place IOB ad<22> in site P111.
<BR>Resolved that IOB <ad<21>> must be placed at site P112.
<BR> Place IOB ad<21> in site P112.
<BR>Resolved that IOB <ad<20>> must be placed at site P113.
<BR> Place IOB ad<20> in site P113.
<BR>Resolved that IOB <ad<19>> must be placed at site P114.
<BR> Place IOB ad<19> in site P114.
<BR>Resolved that IOB <ad<18>> must be placed at site P115.
<BR> Place IOB ad<18> in site P115.
<BR>Resolved that IOB <ad<17>> must be placed at site P116.
<BR> Place IOB ad<17> in site P116.
<BR>Resolved that IOB <ad<16>> must be placed at site P119.
<BR> Place IOB ad<16> in site P119.
<BR>Resolved that IOB <ad<15>> must be placed at site P132.
<BR> Place IOB ad<15> in site P132.
<BR>Resolved that IOB <ad<14>> must be placed at site P133.
<BR> Place IOB ad<14> in site P133.
<BR>Resolved that IOB <ad<13>> must be placed at site P134.
<BR> Place IOB ad<13> in site P134.
<BR>Resolved that IOB <ad<12>> must be placed at site P135.
<BR> Place IOB ad<12> in site P135.
<BR>Resolved that IOB <ad<11>> must be placed at site P136.
<BR> Place IOB ad<11> in site P136.
<BR>Resolved that IOB <ad<10>> must be placed at site P138.
<BR> Place IOB ad<10> in site P138.
<BR>Resolved that IOB <ad<9>> must be placed at site P139.
<BR> Place IOB ad<9> in site P139.
<BR>Resolved that IOB <ad<8>> must be placed at site P140.
<BR> Place IOB ad<8> in site P140.
<BR>Resolved that IOB <ad<7>> must be placed at site P142.
<BR> Place IOB ad<7> in site P142.
<BR>Resolved that IOB <ad<6>> must be placed at site P143.
<BR> Place IOB ad<6> in site P143.
<BR>Resolved that IOB <ad<5>> must be placed at site P3.
<BR> Place IOB ad<5> in site P3.
<BR>Resolved that IOB <ad<4>> must be placed at site P4.
<BR> Place IOB ad<4> in site P4.
<BR>Resolved that IOB <ad<3>> must be placed at site P5.
<BR> Place IOB ad<3> in site P5.
<BR>Resolved that IOB <ad<2>> must be placed at site P6.
<BR> Place IOB ad<2> in site P6.
<BR>Resolved that IOB <ad<1>> must be placed at site P7.
<BR> Place IOB ad<1> in site P7.
<BR>Resolved that IOB <ad<0>> must be placed at site P9.
<BR> Place IOB ad<0> in site P9.
<BR>Resolved that IOB <din> must be placed at site P105.
<BR> Place IOB din in site P105.
<BR>Resolved that IOB <m_fpga> must be placed at site P86.
<BR> Place IOB m_fpga in site P86.
<BR>Resolved that IOB <par> must be placed at site P130.
<BR> Place IOB par in site P130.
<BR>Resolved that IOB <pio<7>> must be placed at site P31.
<BR> Place IOB pio<7> in site P31.
<BR>Resolved that IOB <pio<6>> must be placed at site P30.
<BR> Place IOB pio<6> in site P30.
<BR>Resolved that IOB <pio<5>> must be placed at site P29.
<BR> Place IOB pio<5> in site P29.
<BR>Resolved that IOB <pio<4>> must be placed at site P28.
<BR> Place IOB pio<4> in site P28.
<BR>Resolved that IOB <pio<3>> must be placed at site P26.
<BR> Place IOB pio<3> in site P26.
<BR>Resolved that IOB <pio<2>> must be placed at site P25.
<BR> Place IOB pio<2> in site P25.
<BR>Resolved that IOB <pio<1>> must be placed at site P24.
<BR> Place IOB pio<1> in site P24.
<BR>Resolved that IOB <pio<0>> must be placed at site P23.
<BR> Place IOB pio<0> in site P23.
<BR>
<BR>
<P>Overall effort level (-ol): 5 (set by user)
<BR>Placer effort level (-pl): 5 (default)
<BR>Placer cost table entry (-t): 1
<BR>Router effort level (-rl): 5 (default)
<P>Device utilization summary:
<P> Number of External IOBs
108 out of 112 96%
<BR> Flops:
41
<BR> Latches:
0
<BR> Number of Global Buffer IOBs
1 out of 8 12%
<BR> Flops:
0
<BR> Latches:
0
<P> Number of CLBs
184 out of 196 93%
<BR> Total CLB Flops:
127 out of 392 32%
<BR> 4 input LUTs:
293 out of 392 74%
<BR> 3 input LUTs:
132 out of 196 67%
<P> Number of PRI-CLKs
1 out of 4 25%
<BR> Number of STARTUPs
1 out of 1 100%
<BR>
<P>Starting initial Timing Analysis. REAL time: 8 secs
<BR>Finished initial Timing Analysis. REAL time: 15 secs
<P>Starting initial Placement phase. REAL time: 17 secs
<BR>Finished initial Placement phase. REAL time: 17 secs
<P>Starting Constructive Placer. REAL time: 18 secs
<BR>Placer score = 739054
<BR>Placer score = 676718
<BR>Placer score = 642819
<BR>Placer score = 609235
<BR>Placer score = 592638
<BR>Placer score = 581866
<BR>Placer score = 549978
<BR>Placer score = 488661
<BR>Placer score = 469602
<BR>Placer score = 444377
<BR>Placer score = 346626
<BR>Placer score = 329078
<BR>Placer score = 302982
<BR>Placer score = 289464
<BR>Placer score = 278697
<BR>Placer score = 248470
<BR>Placer score = 239737
<BR>Placer score = 224533
<BR>Placer score = 223399
<BR>Placer score = 209084
<BR>Placer score = 208577
<BR>Placer score = 201376
<BR>Placer score = 195533
<BR>Placer score = 188765
<BR>Placer score = 186164
<BR>Placer score = 183980
<BR>Placer score = 183456
<BR>Placer score = 181512
<BR>Placer score = 180330
<BR>Placer score = 180252
<BR>Placer score = 178874
<BR>Placer score = 178789
<BR>Placer score = 178481
<BR>Placer score = 178431
<BR>Finished Constructive Placer. REAL time: 7 mins 34 secs
<P>Dumping design to file "top.ncd".
<P>Starting Optimizing Placer. REAL time: 7 mins 35 secs
<BR>Optimizing .
<BR>Swapped 8 comps.
<BR>Xilinx Placer [1] 178325 REAL time: 7 mins
54 secs
<P>Finished Optimizing Placer. REAL time: 7 mins 54 secs
<P>Dumping design to file "top.ncd".
<P>Total REAL time to Placer completion: 7 mins 55 secs
<BR>Total CPU time to Placer completion: 7 mins 52 secs
<P>0 connection(s) routed; 1543 unrouted active, 1 unrouted PWR/GND.
<BR>Starting router resource preassignment
<BR>Completed router resource preassignment. REAL time: 7 mins 59 secs
<BR>Starting iterative routing.
<BR>End of iteration 1
<BR>1528 successful; 15 unrouted active,
<BR> 1 unrouted PWR/GND; (1772442) REAL time: 8 mins 37 secs
<BR>End of iteration 2
<BR>1536 successful; 7 unrouted active,
<BR> 1 unrouted PWR/GND; (746985) REAL time: 9 mins 19 secs
<BR>End of iteration 3
<BR>1542 successful; 1 unrouted active,
<BR> 1 unrouted PWR/GND; (530110) REAL time: 9 mins 57 secs
<BR>End of iteration 4
<BR>1543 successful; 0 unrouted active,
<BR> 1 unrouted PWR/GND; (271189) REAL time: 11 mins 23 secs
<BR>End of iteration 5
<BR>1543 successful; 0 unrouted active,
<BR> 1 unrouted PWR/GND; (101714) REAL time: 11 mins 56 secs
<BR>Power and ground nets completely routed.
<BR>End of iteration 6
<BR>1544 successful; 0 unrouted; (64047) REAL time: 13 mins 3 secs
<BR>End of iteration 7
<BR>1544 successful; 0 unrouted; (52136) REAL time: 13 mins 26 secs
<BR>End of iteration 8
<BR>1544 successful; 0 unrouted; (36391) REAL time: 14 mins 23 secs
<BR>End of iteration 9
<BR>1544 successful; 0 unrouted; (34926) REAL time: 14 mins 49 secs
<BR>End of iteration 10
<BR>1544 successful; 0 unrouted; (33454) REAL time: 15 mins 52 secs
<BR>End of iteration 11
<BR>1544 successful; 0 unrouted; (30196) REAL time: 16 mins 15 secs
<BR>End of iteration 12
<BR>1544 successful; 0 unrouted; (27246) REAL time: 17 mins 3 secs
<BR>End of iteration 13
<BR>1544 successful; 0 unrouted; (26589) REAL time: 17 mins 37 secs
<BR>End of iteration 14
<BR>1544 successful; 0 unrouted; (24456) REAL time: 18 mins 1 secs
<BR>End of iteration 15
<BR>1544 successful; 0 unrouted; (24151) REAL time: 18 mins 23 secs
<BR>End of iteration 16
<BR>1544 successful; 0 unrouted; (20108) REAL time: 19 mins 6 secs
<BR>End of iteration 17
<BR>1544 successful; 0 unrouted; (19073) REAL time: 19 mins 31 secs
<BR>End of iteration 18
<BR>1544 successful; 0 unrouted; (19323) REAL time: 20 mins 13 secs
<BR>End of iteration 19
<BR>1544 successful; 0 unrouted; (17811) REAL time: 20 mins 35 secs
<BR>End of iteration 20
<BR>1544 successful; 0 unrouted; (18460) REAL time: 21 mins 13 secs
<BR>End of iteration 21
<BR>1544 successful; 0 unrouted; (18460) REAL time: 21 mins 38 secs
<BR>End of iteration 22
<BR>1544 successful; 0 unrouted; (16998) REAL time: 22 mins 17 secs
<BR>End of iteration 23
<BR>1544 successful; 0 unrouted; (16998) REAL time: 22 mins 38 secs
<BR>End of iteration 24
<BR>1544 successful; 0 unrouted; (16998) REAL time: 23 mins 22 secs
<BR>End of iteration 25
<BR>1544 successful; 0 unrouted; (17054) REAL time: 23 mins 43 secs
<BR>End of iteration 26
<BR>1544 successful; 0 unrouted; (15732) REAL time: 24 mins 33 secs
<BR>End of iteration 27
<BR>1544 successful; 0 unrouted; (15374) REAL time: 24 mins 51 secs
<BR>Giving up.
<BR>Dumping design to file "top.ncd".
<BR>Starting cleanup
<BR>End of cleanup iteration 1
<BR>1544 successful; 0 unrouted; (15432) REAL time: 25 mins 10 secs
<BR>Dumping design to file "top.ncd".
<BR>Starting delay cleanup
<BR>End of delay cleanup iteration 1
<BR>1544 successful; 0 unrouted; (14977) REAL time: 25 mins 36 secs
<BR>End of delay cleanup iteration 2
<BR>1544 successful; 0 unrouted; (14977) REAL time: 26 mins
<BR>End of delay cleanup iteration 3
<BR>1544 successful; 0 unrouted; (14977) REAL time: 26 mins 25 secs
<BR>End of delay cleanup iteration 4
<BR>1544 successful; 0 unrouted; (14977) REAL time: 26 mins 50 secs
<BR>End of delay cleanup iteration 5
<BR>1544 successful; 0 unrouted; (14977) REAL time: 27 mins 14 secs
<BR>Dumping design to file "top.ncd".
<BR>Total REAL time: 27 mins 14 secs
<BR>Total CPU time: 27 mins 3 secs
<BR>Completely routed.
<BR>End of route. 1544 routed (100.00%); 0 unrouted.
<BR>No errors found.
<P>The design submitted for place and route did not meet the specified
timing
<BR>requirements. Please use the static timing analysis tools (TRCE
or Timing
<BR>Analyzer) to report which constraints were not met. To obtain
a better result,
<BR>you may try the following:
<BR> * Use the Re-entrant routing feature to run more router iterations
on the
<BR>design.
<BR> * Check the timing constraints to make sure the design is not
<BR>over-constrained.
<BR> * Specify a higher placer effort level, if possible.
<BR> * Use the Multi-Pass PAR (MPPR) feature. This generates
multiple placement
<BR>trials from which the best (i.e., lowest design score) placement can
be used
<BR>with re-entrant routing to obtain a better result.
<P>Please consult the Development System Reference Guide for more detailed
<BR>information about the usage options pertaining to these features.
<P>Total REAL time to Router completion: 27 mins 15 secs
<BR>Total CPU time to Router completion: 27 mins 4 secs
<P>Generating PAR statistics.
<BR>Timing Score: 14977
<P>WARNING:baspw:101 - Timing constraints have not been met.
<P>Dumping design to file "top.ncd".
<BR>
<P>All signals are completely routed.
<P>Total REAL time to PAR completion: 27 mins 25 secs
<BR>Total CPU time to PAR completion: 27 mins 12 secs
<P>PAR done.
<P>trce top.ncd top.pcf -o top.twr
<P>Loading device database for application trce from file "top.ncd".
<BR> "top" is an NCD, version 2.27, device xcs10, package tq144,
speed -4
<BR>Loading device for application trce from file '4005e.nph' in environment
<BR>C:/xilinx.
<BR>--------------------------------------------------------------------------------
<BR>Xilinx TRACE, Version M1.4.12
<BR>Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
<P>Design file:
top.ncd
<BR>Physical constraint file: top.pcf
<BR>Device,speed:
xcs10,-4 (x1_0.05 ADVANCED)
<BR>Report level:
summary report
<BR>--------------------------------------------------------------------------------
<BR>
<BR>
<P>Timing summary:
<BR>---------------
<P>Timing errors: 17 Score: 14977
<P>Constraints cover 4457 paths, 69 nets, and 1017 connections (65.9% coverage)
<P>Design statistics:
<BR> Maximum path delay from/to any node: 31.753ns
<BR> Maximum net delay: 8.786ns
<BR>
<P>Analysis completed Tue Sep 29 13:00:43 1998
<BR>--------------------------------------------------------------------------------
<P>Total time: 17 secs
<P>ngdanno top.ncd map.ngm
<BR>ngdanno: version M1.4.12
<BR>Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
<P>Loading device database for application ngdanno from file "top.ncd".
<BR> "top" is an NCD, version 2.27, device xcs10, package tq144,
speed -4
<BR>Loading device for application ngdanno from file '4005e.nph' in environment
<BR>C:/xilinx.
<BR>Reading .ngm file "map.ngm"...
<BR>Building NGA image...
<BR>Annotating NGA image...
<BR>Distributing delays...
<BR>Reading component libraries for design expansion...
<BR>Writing .nga file "top.nga"...
<BR> 294 logical models annotated
<P>ngd2vhdl -w top.nga time_sim.vhd
<BR>ngd2vhdl: version M1.4.12
<BR>Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
<BR> running NGD DRC ...
<BR>Global signal "GSR" is driven by primitive "IX1728_GSR_BUF".
<BR>Global signal "GTS" is driven by primitive "IX1728_GTS_BUF".
<BR>Generating vhdl sdf <A HREF="file:time_sim.sdf">file:time_sim.sdf</A>
<BR>Generating VHDL netlist <A HREF="file:time_sim.vhd">file:time_sim.vhd</A>
<P>xcpy time_sim.vhd C:\users\pfb\xact\time_sim.vhd
<P>xcpy time_sim.tvhd C:\users\pfb\xact\time_sim.tvhd
<P>xcpy time_sim.sdf C:\users\pfb\xact\time_sim.sdf
<P>bitgen top.ncd -l -w -f bitgen.ut
<P>Loading device database for application Bitgen from file "top.ncd".
<BR> "top" is an NCD, version 2.27, device xcs10, package tq144,
speed -4
<BR>Loading device for application Bitgen from file '4005e.nph' in environment
<BR>C:/xilinx.
<BR>
<P>BITGEN: Xilinx Bitstream Generator M1.4.12
<BR>Copyright (c) 1995-1997 Xilinx, Inc. All rights reserved.
<P>Running DRC.
<BR>DRC detected 0 errors and 0 warnings.
<BR>Saving ll file in "top.ll".
<BR>Creating bit map...
<BR>Saving bit stream in "top.bit".
<P>xcpy top.bit C:\users\pfb\xact\top.bit
<P>xcpy top.ll C:\users\pfb\xact\top.ll
<BLOCKQUOTE TYPE=CITE>
<P><TT>Laurent</TT>
<P><TT>_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/</TT>
<BR><TT>Laurent Gauch</TT>
<BR><TT>Ecole d'Ingénieurs du Valais (EIV / ISW)</TT>
<BR><TT>Route du Rawyl 47</TT>
<BR><TT>1950 Sion, Switzerland</TT>
<BR><TT>Tel: ++41 (0)27 32 43 363</TT>
<BR><TT>Fax: ++41 (0)27 32 43 315</TT>
<BR><TT>E-mail: laurent.gauch@eiv.vsnet.ch</TT>
<BR><TT><A HREF="http://www.eiv.ch/universel/gc/electro/micro/index.htm">http://www.eiv.ch/universel/gc/electro/micro/index.htm</A></TT>
<BR><TT>_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/</TT>
<BR> </BLOCKQUOTE>
</HTML>
--------------16216656AD5F4674C246262B--
Article: 12218Which FPGA: With care, you can implement a pipelined DLX-like 32-bit RISC processor, memory controller, 32-bit on-chip bus, peripherals like UARTs, DRAM controller, boot ROM, and so forth in a XC4010 (XCS20). I did so in 1995, see my PowerPoints at http://www3.sympatico.ca/jsgray/homebrew.htm. I am now working on a new web site which shows how to successfully design custom processors and integrated systems on chip using FPGAs; please write me if you would like more information. It is also possible to build a 32-bit ISA processor and integrated system in smaller parts: * XC4005 (XCS10): pipelined16-bit datapath and 16-bit external bus; takes two cycles to process the lower and upper half-words of each 32-bit operation. * XC4003 (XCS05): non-pipelined (perhaps variable latency)16-bit datapath and 16-bit external bus; requires about 11 cycles to fetch and increment PC, fetch each half-word operand, operate on each half-word operand, and write back the results. I-cache: A 256 byte (16 lines with 16 bytes/line) I-cache is approximately 6x16 CLBs: 4x16 CLBs data, 1x16 CLBs tags, 1x16 CLBs tag comparator and misc logic. In my XC4010 design, there is room for this at the expense of the boot ROM. In fact, the I-cache can be preinitialized with the boot ROM contents... Advice: I appreciate your desire to teach and use an HDL and an existing model. But to best fit a 32-bit pipelined RISC into an modest FPGA I think you will need * time to teach/master the FPGA device architecture and idiom * explicit instantiation of datapath device primitives via schematics or netlist generator * floorplanning * willingness to streamline the ISA to fit into the FPGA I doubt that an off-the-shelf HDL CPU model written without concern for FPGA targeting will easily synthesize to any FPGA you choose. You will probably have to write a new model. You may wish to iteratively codesign your instruction set architecture and implementation in order to achieve a small/feasible datapath. In particular, Xilinx programmable interconnect does not permit a great plurality of word-wide horizontal buses. You should design and floor plan with that in mind, and let that drive your design, whether it be schematics, netlist, or HDL. I definitely feel that use of schematics or netlist generator is your best bet to instance the primitives you need where you need them. For instance, you could specify your entire design in HDL and then do a second implementation of the datapath using schematics to achieve a good/feasible datapath. In the latter you control instantiation and technology mapping using FMAPs, and placement using RLOCs. See http://www.fliptronics.com/floorplanning1.html for a tutorial on FPGA floorplanning. See slides 20 and 21 of http://www3.sympatico.ca/jsgray/j32.ppt, or the GIFs at http://www3.sympatico.ca/jsgray/sld020.htm and http://www3.sympatico.ca/jsgray/sld021.htm for one successful RISC processor datapath and floorplan. Of course, if you design a new ISA or subset an existing ISA you are faced with the problem of compiling to it. Options include a new lcc or gcc back end, or, post-link translation of a MIPS or DLX image to your ISA. Boards: If pedagogical value, not performance, is what you seek, then you can succeed with almost any of the available prototyping boards, including the Xilinx proto board, the XESS board, the various APS boards. If you just want to boot and print hello world, on chip memory will suffice. For something more extenstive, you can add a 16- or 32-bit memory, as little as 2 x8 SRAMs, to the Xilinx proto board. You can use the 8-bit memory on the XESS board, or the 32-bit memory of the APS X240 or the PCI Pamette (http://www.research.digital.com/SRC/pamette/). Just as some examples. As for PC interface, my designs were downloaded and tested using a serial port and the Xilinx xchecker pod, nice because I could slowly clock the prototype and read back all internal state each clock. Also, I don't think a PCI board will be much of an advantage over a ISA board for your application -- just be sure to get something that can download designs, readback configurations and internal state, step the clock, and perhaps read and write to the RAM. There are other institutions teaching similar material. For instance, Cornell: http://www2.cs.cornell.edu/hot314. You should also contact the Xilinx University Program for ideas. Jan GrayArticle: 12219
Hello, To make it more clear, you can get the delay from any signal to any other signal using the DELAY MATRIX.. After invoking the TIming Analyzer(Delay_Matrix), go to Assign menu.. And, select the Source and Destination.. You can also use the wild characters like * to select the signals in your design.. This really helps in large designs.. You can select any signals like D i/p, Q o/p..etc usign this approach.. Then, press on Start button.. For each delay, you can "List Paths" to see the detailed path in the florrplanner and can assign all of them to a clique if that is timing-critical.. regards, Srikanth// Giang Thach Nguyen wrote: > Does anyone know how to report delay of internal signals with Altera's Maxplus2 Timing Analyzer? I can only get the delay from one I/O pin to another I/O pin. Any input would be appreciated.Article: 12220
In article <6v096f$tnt$1@nnrp1.dejanews.com>, <pipjockey@my-dejanews.com> wrote: >Whatever happened to the Viewlogic synthesis tool called Aurora? I understand >that it produced superior results for FPGAs than FPGA-Express. Now that >Synopsys bought Viewlogic, is Aurora dead? I heard exactly the same thing. It's funny, suddenly viewlogic comes up with a decent synthesis tool (after years of sucking with viewsynthesis) and ..... surprize!!! But hey... you can't complain. FPGA express is faster (about 4 times slower than synplicity providing you have 128megs of RAM in your PC for a 10K PLD gate design or less) with average results. > >Rob Weinstein >Memec Design Services >rob_weinstein@memecdesignDOTcom > > > >-- >Rob Weinstein >Memec Design Services - Phoenix >rob_weinstein@memecdesignDOTcom > >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12221
Hans Lindkvist wrote in message <3614BD09.E32A0E14@ldecs.ericsson.se>...
Rickman wrote:
Jake Janovetz wrote:
One possibly big difference, depending on whether you have existing
code, is that Synopsys does not support VHDL-93. They seem to be
pretty
stuck in VHDL-87.
Otherwise, I can only stay that Synopsys is what comes with Xilinx
Foundation, so a lot of Xilinx users have it! ;)
I've heard from a Synopsys representative that vhdl-93 support is close.
I just got the Xilinx Foundation 1.5 tools w/Synopsys FPGA Express, and
there's support for *some* VHDL'93 things, like rising_edge() and
falling_edge() and myprocess : process (yadda) IS.
A start.
-andy
Article: 12222yves@px.uk.com (Yves Tchapda) wrote: :On Mon, 31 Aug 1998 10:15:52 +0200, "Reza Bohrani" :<Reza.Bohrani@timespace.se> wrote: : :>I was wondering, if anyone could tell me what a divide-by-six Jonson counter :>is and to what it is used? :> :A Johnson counter also known as twisted-tail ring counter is a shift :register with the the inverted output of the last stage connected to :the input of the first stage. : A divide-by-six Johnson counter has three registers. A Johson counter :with n-bits (n flip-flops) is a divide-by-2n counter. So the count sequence for a 6-bit Johnson counter would be: 000000 000001 000011 000111 001111 011111 111111 111110 111100 111000 110000 100000 This has of course, used 12 of the 64 states possible in 6 bits. All the other states are illegal. If inadvertently entered, the counter will usually continue cycling through illegal states. A clean reset will start it off right, but if your application must be sure to recover from faults, you'll need to trap those illegal states. -- Dave Brooks <http://www.iinet.net.au/~daveb> PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or serversArticle: 12223
Rickman wrote: > > > Sarbjit, > > I would suggest that you not use Orcad for FPGA design. > > I don't want to get a reputation for Orcad bashing, but I started a > project with Orcad working in a Xilinx FPGA and had to abandon Orcad > before I was done. This was primarily because of many problems with VHDL > synthesis, but there were many other problems such as the one you have > found. Orcad seems to deal with these problems by expecting the customer > to work around them. Many times Orcad did not consider the problem to be > significant enough to fix in the next release. I know this not by > assumption, but because I had many conversations with tech support where > they told me this. > > I can't begin to tell you how many times Orcad crashed on my machines (I > worked on two different ones during the course of my project). I even > was able to send them a schematic which if you deleted a couple of parts > at once, would crash. Their response was that this was expected given > the "invalid state" this would put the schematic in since the parts were > heiarchical port symbols. > > Orcad's response to the problem of losing data when the program crashed > so often was to tell you to save your work often. This is a practice > that I learned in the 70's programming on a mainframe. But most people > no longer consider this an adequate solution in the 90's. (But then > again I get ticked off at my ISP for not being as reliable as my > telephone service). > > So I just gave up on Orcad and started using Xilinx Foundation. It is > certainly not bug free. But I am able to move ahead and get my work > done. With Orcad, I was stuck for as long as a day at a time trying to > find a solution to each problem. > > I really don't want to be an Orcad basher. If anyone has any positive > comments about Orcad I would love to hear them. Sorry I don't have anything positive to say but I can back you up on the negative side. The Capture part of Express has many bugs and inconsistencies. It even has advertised features which are completely missing. I personally have found two separate bugs in Capture (submitted to Orcad) which caused Capture to exit after trying to access memory which did not belong to it (ie probably dereferencing a dangling pointer). In my experience with programming this is the EASIEST kind of bug to track down and fix. Orcad says it will fix these bugs in the next release. The VHDL synthesis part of Express is far worse than the Capture part. Many bugs and much crashing. The Simulate part of the Express package was almost useable but also had some problems. Orcad Layout is probably the most useable part of the whole suite but again is nowhere near being as bug-free and useable as it should be. As it stands I am rather surprised that Orcad seems to have the low price end of the EDA market sown up. I am REALLY looking forward to seeing things like gEDA and freeHDL get to useable state. Erik -- ------------------------------- Erik de Castro Lopo Fairlight ESP Pty Ltd e.de.castro AT fairlightesp.com.auArticle: 12224
I agree that a DSP is easier to use. The DSP's flexibility is in the software: the hardware is fixed. My point is that with an FPGA, the hardware is also flexible which gives you more considerably more freedom to tackle a design problem. It also gives you considerably more freedom to hang yourself, especially if you are not an experienced FPGA designer familiar with hardware implementation of algorithms. So if you meant to say a DSP is easier to use, I agree 100%. I don't, however, equate easy to use with flexible. (how easy it is to change a programmed algorithm is an ease of use issue to me). As tools mature, I think we will see it become easier to create and modify algorithms implemented in FPGA hardware. Rickman wrote: > Perhaps I should let Walt speak for himself, but I think most people > mean flexibility to mean the ability to easily modify or implement > algorithms rather than the raw capability of a medium to implement > algorithms. > > In this case I don't think many people will argue that it is easier to > design an FPGA than it is to program a DSP for a given algorithm. And > certainly it is much easier to change that 32 tap FIR to a 5 biquad IIR > on a DSP than an FPGA. I suppose this is a matter of opinion based on > what you are familiar with. But I am much more familiar with FPGAs than > DSPs and given the choice, I would choose the DSP! > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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