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On Fri, 17 Jul 1998, Ray Andraka wrote: > [snip] The xilinx 6200 is a weird chip. [snip] > Another nice feature is that there are no illegal bit streams, so you > don't have to worry about what you feed it (this feature makes this > device the only one acceptable for evolutionary reconfiguration such as > genetic programming). [snip fried chips] I've seen this comment several times here. While safety is a desirable feature, lack of it does not mean you can't use evolutionary strategies to program the chip. Some approaches work at a high level and can thus use software techniques to eliminate the possibility of writing a bit stream that will result in damage. Other approaches use such mechanisms as non-uniform cellular automata to insulate themselves from the hardware of the chips, so that no combination of different cells can cause a short. > Pawel E. Tomaszewicz wrote: > > Hello, > > I'm looking for information about FPGA devices with partial > > reprograming. [snip] > > I heard about programme/family chip called "Raphael" from Xilinx. Where > > can I find any info about it? Not from me - I've not heard of it - Xilinx's search engine hasn't either. Reconfigurability is supposed to be on the list of features of the Xilinx 'Virtex' series due in the not-too-distant. It is not clear to me whether these chips will supercede the 6200 immediately, or whether the 6200 will remain the preferred Xilinx chip for applications which require partial reconfiguration for some time. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.comArticle: 11126
Does anyone have a useful reference design for an Asynchronous FIFO suitable for a Xilinx 4000E/X/XL device they can send me ? Regards, Neil C.Article: 11127
Edward Pickering wrote: > > Does anyone happen to know what has happened to either Crosspoint > Solutions or Concurrent Logic? > > I'm currently doing some research, and can't seem to find anything out > about them. Chances are that they went bust or got taken over, but a > definate confirmation would be useful. > > My thanks in advance... > > Edward Pickering > UMIST As Ray said, the Concurrent stuff is now the Atmel 6K product family. Crosspoint went the way of the dodo bird if I remember correctly. Not enough venture capital is what I heard. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11128
Hi, I was trying to do a VHDL Functional simulation with Maxplus2. I have an entity A, which has an entity B underneath it, and B has an entity C underneath it. After compilation, I brought up the waveform editor to add signals. I was trying to use Menu Node -> "Enter Nodes from SDF". I wanted to trace down the hierachy to see all the ports and signals in entity B and C. However, not all the ports/ signals were there when I listed all the nodes/groups. Does anyone know how to trace the ports/signals down the hierachy? Thanks for your help in advance. ----------------------- Louis Zhang lzhang@eecg.toronto.eduArticle: 11129
In article <35B36DC1.D49003B@yahoo.com> Rickman <spamgoeshere4@yahoo.com> writes: >Edward Pickering wrote: >> Does anyone happen to know what has happened to either Crosspoint >> Solutions or Concurrent Logic? >> I'm currently doing some research, and can't seem to find anything out >> about them. Chances are that they went bust or got taken over, but a >> definate confirmation would be useful. >> Edward Pickering >> UMIST >As Ray said, the Concurrent stuff is now the Atmel 6K product family. >Crosspoint went the way of the dodo bird if I remember correctly. Not >enough venture capital is what I heard. Hardly. Way too much VC money. Among the things I'm fairly un-enthusiastic about, fine grained FPGAs and anti-fuse are nowhere near the bottom of my list. Crosspoint was both. In FPGAs, die size tends to be far better correlated to routing/connection resources (scaled by implementation technology), rather than logic, because the real-estate for routing/switching/programming/prog-verify out-weighs the "delivered to the user gates" by from 5-to-1 to 10-to-1. Switchable/programmable interconnect is also slower that direct metal interconnect. The problem with fine grained architectures is that a significant protion of your interconnect ends up being used just to build basic functions. In some silly FPGA architectures, you actually use programmable interconnect just to get a flip flop. Since you are basically paying for interconnect :-) , do you really want to be paying to create the basic gates, or do you want to pay to connect them together. Not that I am one to speak ill of the dead, but another excellent case study in FPGA architecture designed by those that never have used them it the Pilkington design: So far, three companies (Plessey, Toshiba, Motorola) have wasted big bucks down this alley. The big attraction is that these companies wanted to get into the FPGA business, and the fast track is to license technology rather than develop it. Maybe it is also important to check if the technology is worth licensing. Among the features usually promoted by fine-grained enthusiasts, the most common is that the technology "looks just like an ASIC", so "there wont be any tools issues", and "it will be easy to migrate to an ASIC". It would be interesting to see if ANY fine-grained architecture has EVER lived up to any of these three claims. But put aside your need for instant gratification, and the advantage of converting to an ASIC with zero effort, and take the long term strategic view from the FPGA vendor's view (i.e. a 6 month view rather than a 3 month view) : If the main selling point is that you can convert to an alternative technology that is cheaper, and available from multiple other vendors, then there will be little medium to high volume usage, and the company will not have the revenue to stay in business. Do you really want to invest time in learning how to use a company's product, when their business model pretty much guarantees they wont be around for very long. My issues with anti-fuse are: Cant be on a leading technology because it adds processing steps to what ever is the leading geometry/metalization capability May not be able to be run on the leading geometry because of the voltages needed to program the anti-fuses Cant be fully tested from the factory. Cant be programmed after board assembly Does not get at-speed timing and parametric test, post programming Tend to be fine grained. In an environment where incomming parts are expected to have dead-on-arrival rates below 100 parts per million, a post programming failure rate of .1% represents a quality level 10 times worse than acceptable. Now go try finding an anti-fuse part that can do 50000 gates, and will yield 99.9%, post programming. Philip FreidinArticle: 11130
Here's the most useful document I've come across about CRC's. It explains everything and tells you how to do serial, Parallel and Parallel lookup CRC. [excerpt from document] A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS ================================================== "Everything you wanted to know about CRC algorithms, but were afraid to ask for fear that errors in your understanding might be detected." Version : 3. Date : 19 August 1993. Author : Ross N. Williams. Net : ross@guest.adelaide.edu.au. FTP : ftp.adelaide.edu.au/pub/rocksoft/crc_v3.txt [end excerpt] ems wrote in message <35b32585.13098417@news.dial.pipex.com>... >On Sun, 19 Jul 1998 10:42:35 -0400, APS <resp@associatedpro.com> >wrote: > >>Has anyone done any CRC-16 implementations in an FPGA? I am looking for >>the CRC-CCITT implementaton in particular. Any help or pointers to >>information at all would be appretiated? > >The first problem here is the phrase 'CRC-CCITT'. I don't know who >invented this term (it doesn't seem to have been the CCITT), and >what specifically they meant, but I take it to mean some subset of V41 >and V42 (CCITT Blue Book, Volume VIII, Fascicle VIII.I, >recommendations V41 and V42, ISBN 92-61-03661-9). V41 and V42 agree >on a polynomial, but recommend different preset values for the >shift register. I think the most common implementation is to preset >the transmitter to all 1's, to invert the output, and for the receiver >to check for 0x1D0F (the V42 'typical implementation'). If you don't >want to do a parallel version, then the diagrams in the spec are all >you'll need. > >If you want a parallel version, you'll have to decompose the >polynomial into a parallel form. This is pretty straightforward. One >very useful reference is one of AMD's TAXI app notes, which I've >unfortunately lost. You could also look up an EDN article by Krishna >Rallapalli (EDN, Sept.5/1978). I think this describes an old Fairchild >chip (74F401?). I've also got an old article by Jack Ganssle (1991) - >I don't know what the source is; probably EDN or Byte. > >The next problem is that the CCITT describes a bit-serial algorithm, >and so there's an implicit endianism problem when you convert to >parallel. The articles I've seen generally ignore this (Ganssle's is >particularly bad, and wrong), and so they result in different >implementations (for instance, the receiver has to check for 0xF0B8 >instead of 0x1D0F). A related problem is whether to transmit the high >byte of the result first, or second. The answer's easy if you've >actually got a bit- serial transmission medium - everything has to be >bit-big-endian (X25, for example, normally sends its data fields >little-endian, but sends the checksum big-endian). > >However, if you're not responsible for the complete system, the >important thing is to check that everyone agrees on the transmission >format and check value - there's a good chance that the other guy will >have got it wrong. > >The actual parallel hardware's pretty trivial. You can trade off the >number of delay levels against the logic complexity but, IIRC, you'll >end up with a total of 20-25 two, three, and four-in xor's. > >Evan (ems@nospam.riverside-machines.com) >Article: 11131
Is there _any_ way at all of doing behavioral synthesis for the Xilinx 6200 FPGA? Any help will be greatly appreciated. Reetinder Sidhu Dept. of EE University of Southern CaliforniaArticle: 11132
On Mon, 20 Jul 1998 07:54:15 GMT, leslie.yip@asmpt.com wrote: > elsif UP='1' and UP'event and ENABLE = '1' then > <snip> > elsif DN='1' and DN'event and ENABLE = '1' then you can't do this - you can't have two clocks in the same process. however, this isn't a language issue. how would you design this with a pencil and paper? can you guarantee that the two clocks don't arrive at the 'same' time? and if you really want to create a register element with two clock inputs, what sort of device could you implement it in? the only general solution, if you actually have two clocks, is to sync them both up to a higher rate clock, and to generate a delayed register clock with an appropriate up/down enable. evan (ems@nospam.riverside-machines.com)Article: 11133
"Gareth Baron" <Gareth.Baron@eng.efi.com> wrote: :Here's the most useful document I've come across about CRC's. It explains :everything and tells you how to do serial, Parallel and Parallel lookup CRC. : :[excerpt from document] : :A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS :================================================== :"Everything you wanted to know about CRC algorithms, but were afraid :to ask for fear that errors in your understanding might be detected." : :Version : 3. :Date : 19 August 1993. :Author : Ross N. Williams. :Net : ross@guest.adelaide.edu.au. :FTP : ftp.adelaide.edu.au/pub/rocksoft/crc_v3.txt : :[end excerpt] That URL should read: ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt -- Dave Brooks <http://www.iinet.net.au/~daveb> PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or serversArticle: 11134
ems wrote: > > On Mon, 20 Jul 1998 07:54:15 GMT, leslie.yip@asmpt.com wrote: > > > elsif UP='1' and UP'event and ENABLE = '1' then > > <snip> > > elsif DN='1' and DN'event and ENABLE = '1' then > > you can't do this - you can't have two clocks in the same process. > > however, this isn't a language issue. how would you design this with a > pencil and paper? can you guarantee that the two clocks don't arrive > at the 'same' time? and if you really want to create a register > element with two clock inputs, what sort of device could you implement > it in? > > the only general solution, if you actually have two clocks, is to sync > them both up to a higher rate clock, and to generate a delayed > register clock with an appropriate up/down enable. > > evan (ems@nospam.riverside-machines.com) The "how would you design this in hardware" argument doesn't apply this time. This is exactly how a standard TTL device works, the 74LS193. It has an up clock and a down clock. Of course it is up to the user to actuate only one at a time. But then all logic has the caveat of proper usage. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11135
Try using the "Preserve All Node Name Synonyms" option, found under the Processing menu when the Compiler window is active. The naming generated by the compiler (I use AHDL) is my single biggest problem with Altera. Finding the nodes in the timing simulators and floorplans can be a pain. At least in the timing simulator you can search using wildcards for node names. On the floorplanner, unless you know the exact name (which can be ridiculously long for even a moderately heirarchical design), you can't find it. Then when it optimises it away, its a hair-tearer. FWIW, I prefer HDLs over schematics just for the portability and universality (?) of the design file format (ASCII text), if nothing else. Choose your favourite editor & revision control system.... And AHDL over VHDL. As someone posted here a while ago, AHDL is to VHDL what assembler is to C. You can get so close to the architecture (which lots of newcomers think is a bad thing), and use it very efficiently. regards, Paul Teagle Systems Engineer CAE MRadArticle: 11136
Announcing the updated version of Bournemouth University's Dynamically Reconfigurable Hardware WWW Library http://dec.bournemouth.ac.uk/drhw_lib/ The DRHW WWW Library has now replaced the old BU's page of Dynamically Reconfigurable Hardware originally located at http://dec.bournemouth.ac.uk/dec_ind/decind6/drhw_page.html. The information provided at the new site has been largely updated, and also some new contents categories (such as list of DRHW-related conferences) have been created. The interface now includes frame-based navigation and search capabilities. DRHW WWW Library Table of Contents: - Welcome ! - Terminology - Devices & Technology - Custom Computing - Embedded Systems - Evolvable HW & Embryonics - CAD & Compilers - Conferences & Journals - Other FPGA Links Please update your links ! I would welcome your comments/suggestions/corrections or other requests regarding the new DRHW WWW Library. Thank you, Milan Vasilko -- M.Vasilko@computer.org Dept of Electronics Bournemouth University -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11137
Hello Everybody
I don't know how to implement my previous ASIC-design counter with 2 edge
triggers -- up and down (up => increment the counter by 1; down [i.e. dn] =>
decrement the counter by 1) I used logic gates to implement this function but
it seems difficult to describe this with VHDL. I know that another writing of
up-down counter is to use a pin to control up/down and another is just a
clock for incrementing / decrementing the counter.
My 4-bit counter, however, uses four 4-bit counter to connect together by:
Carry => UP
('Carry' of lower-bit counter connected to 'UP' of another counter)
Borrow => DN
Below is a correct but unsynthesizable (by ViewLogic) code of 16-bit counter.
Could anyone tell me any idea?
Thanks a lot in advance.
-- Leslie Yip, ASM; July, 17
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity COUNTER is
port( NRST: in std_logic;
LOAD: in std_logic;
ENABLE: in std_logic;
UP,DN: in std_logic;
BUSIN: in std_logic_vector(15 downto 0);
CARRY,BORROW: out std_logic;
CNTOUT: out std_logic_vector(15 downto 0)
);
end COUNTER;
architecture COUNTER_ARCH of COUNTER is
signal CNT: std_logic_vector(15 downto 0);
begin
process(NRST,LOAD,UP,DN)
begin
if NRST = '0' then
CNT <= (others=>'0');
CARRY <= '0';
BORROW <= '0';
elsif LOAD='1' then
CNT <= BUSIN;
elsif UP='1' and UP'event and ENABLE = '1' then
if CNT = "1111111111111111" then
CARRY <= UP;
else
CARRY <= '0';
end if;
CNT <= CNT + 1;
elsif DN='1' and DN'event and ENABLE = '1' then
if CNT = "0000000000000000" then
BORROW <= DN;
else
BORROW <= '0';
end if;
CNT <= CNT - 1;
end if;
end process;
CNTOUT <= CNT;
end COUNTER_ARCH;
-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
Article: 11138
leslie.yip@asmpt.com wrote:
>
> Hello Everybody
>
> I don't know how to implement my previous ASIC-design counter with 2 edge
> triggers -- up and down (up => increment the counter by 1; down [i.e. dn] =>
> decrement the counter by 1) I used logic gates to implement this function but
> it seems difficult to describe this with VHDL. I know that another writing of
> up-down counter is to use a pin to control up/down and another is just a
> clock for incrementing / decrementing the counter.
>
> My 4-bit counter, however, uses four 4-bit counter to connect together by:
> Carry => UP
> ('Carry' of lower-bit counter connected to 'UP' of another counter)
> Borrow => DN
>
> Below is a correct but unsynthesizable (by ViewLogic) code of 16-bit counter.
> Could anyone tell me any idea?
> Thanks a lot in advance.
>
> -- Leslie Yip, ASM; July, 17
You might try this design, but it will require very careful timing
control of the clock path. The clock must be slower than the logic. Or
if you trailing edge clock the register, the clock must be faster than
the logic:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity COUNTER is
port( NRST: in std_logic;
LOAD: in std_logic;
ENABLE: in std_logic;
UP,DN: in std_logic;
BUSIN: in std_logic_vector(15 downto 0);
CARRY,BORROW: out std_logic;
CNTOUT: out std_logic_vector(15 downto 0)
);
end COUNTER;
architecture COUNTER_ARCH of COUNTER is
signal CNT: std_logic_vector(15 downto 0);
signal clk: std_logic;
begin
-- You can only have one signal active at a time.
clk <= UP or DN;
-- This makes the Carry and Borrow directly follow UP and DN
-- rather than be clocked. Otherwise keep them within the if clk.
CARRY <= UP when CNT = "1111111111111111" else
'0';
BORROW <= DN when CNT = "0000000000000000" else
'0';
process(NRST,LOAD,clk)
begin
if NRST = '0' then
CNT <= (others=>'0');
CARRY <= '0';
BORROW <= '0';
elsif LOAD='1' then
CNT <= BUSIN;
elsif clk='1' and clk'event and ENABLE = '1' then
if (UP = '1') then
CNT <= CNT + 1;
elsif DN='1' and DN'event and ENABLE = '1' then
CNT <= CNT - 1;
end if;
end if;
end process;
CNTOUT <= CNT;
end COUNTER_ARCH;
If you want to see how they did it in the 74LS193TTL part, I can fax you
the page from the data book (or scan it in and email it).
--
Rick Collins
rickman@XYwriteme.com
remove the XY to email me.
Article: 11139I am trying to use Foundation 1.4 to generate a sdf file, so I can back annotate final placed and routed delay info back into my verilog simulation. In several counters the low order bit uses local feedback and the timing information does not seem to be correctly entered into the sdf file for the local feedback loops. This causes hold violations at every clock edge. Has anyone seen this? P.S. The device is a 95108, the software is stock off the CD. I have downloaded the recommended xilinx update for 95xx series, but not tried it yet. -- | Andrew Dyer <adyer@midway.com> or <adyer@mcs.net> | | Sr. Design Engineer (773) 961-1751 | | Midway Games, Inc. (773) 961-1890 (fax) | | 2727 W. Roscoe Ave., Chicago, IL 60618 |Article: 11140
In comp.arch.fpga ems <ems@see_sig.com> wrote: > On Mon, 20 Jul 1998 07:54:15 GMT, leslie.yip@asmpt.com wrote: > > elsif UP='1' and UP'event and ENABLE = '1' then > > <snip> > > elsif DN='1' and DN'event and ENABLE = '1' then > you can't do this - you can't have two clocks in the same process. > however, this isn't a language issue. how would you design this with a > pencil and paper? can you guarantee that the two clocks don't arrive > at the 'same' time? and if you really want to create a register > element with two clock inputs, what sort of device could you implement > it in? > the only general solution, if you actually have two clocks, is to sync > them both up to a higher rate clock, and to generate a delayed > register clock with an appropriate up/down enable. edge detectors, join them to one signal, use that as clock and use the UP and DN as selects for a multiplexer to select CNT+1 or CNT-1? The edge detector needs some delaying to get the multiplexer ready but... it might work i think Max > evan (ems@nospam.riverside-machines.com)Article: 11141
Having recently posted and item this news group with respect to the interest there would be in a contract VHDL/FPGA startup company, I assume I am partly responsible for all this thread. I never intended any upset and apologise for any caused. My belief was that this newsgroup covered all aspects of FPGA technology and development and that my post was not inappropriate Thomas A. Coonan wrote in message <35b293f2.567303815@news.mindspring.com>... >I too, am concerned. When the traffic on comp.lang.verilog escalates >to the noise of alt.tv.x-files - I know I'll be outta here. > >I've always thought it fair that independents or small firms may >include a 4-5 line email signature trailer (with WWW site, phone #, >etc.), but for us to see it, they simply have to contribute to our >group with some good insightful replies. Give and Take. > >tom coonan >tcoonan@mindspring.com >Scientific Atlanta >>I noticed the amount of personal, corporate and head hunter advertising in >>this news group has increased dramatically. >> >>Personally, I find all this advertising in VERY poor taste. I do not >>believe it is in this groups charter to make this an advertising group, it >>IS a discussion group. >> >>Though people talking about new products, or web sites is great, >>advertising you offer some consulting service, or are a head hunter looking >>for names, I believe, is inappropriate. >> >>Any body else tired of all this advertising? >> >>Austin Franklin >>darkroom@ix.netcom.com >> >Article: 11142
On Mon, 20 Jul 1998 23:26:30 -0400, Rickman <spamgoeshere4@yahoo.com> wrote: > <snip> interesting point about the '193 - i haven't looked at this part before. it looks like it would need some careful layout control to delay the combined clock (it's significantly slower than the equivalent '74, which would support this). my first point was that the code had two clocks in a single process. i don't know for a fact that viewlogic won't synthesise this, but it seems very unlikely (quite apart from the fact that both clocks are updating the same signal - it would be a pretty extraordinary synthesiser that could do this). 1076.6 also specifically excludes multiple clocks in a single process. your code also does the same thing: > elsif clk='1' and clk'event and ENABLE = '1' then > if (UP = '1') then > CNT <= CNT + 1; > elsif DN='1' and DN'event and ENABLE = '1' then > CNT <= CNT - 1; > end if; > end if; but presumably this isn't what you meant? if you can control the delay correctly then you can just substitute s/elsif DN='1' and DN'event and ENABLE = '1' then/elsif (DN = '1') then/ but, practically speaking, my money's on starting again with some hardware that's guaranteed to work, particularly if it's going to be in an fpga. evanArticle: 11143
On 21 Jul 1998 00:35:27 -0500, adyer@MCS.COM (Andrew Dyer) wrote: >I am trying to use Foundation 1.4 to generate a sdf file, so I can >back annotate final placed and routed delay info back into my verilog >simulation. In several counters the low order bit uses local feedback >and the timing information does not seem to be correctly entered into >the sdf file for the local feedback loops. This causes hold >violations at every clock edge. Has anyone seen this? can you post the sdf data for the low bit, and the next bit up, for comparison? evanArticle: 11144
I'm jumping in with both feet and my eyes closed... Any primer/newbie links to CPLD and/or programmable logic in general needed please. It's been years since I "mapped" a PAL. Now I need a PLD interface for our micro and external circuits. Using Lattice isp-Synario. Looking it over, I see I have a lot of catching up to do. Tutorials, app notes and general technique primers needed. I don't think we're in Kansas anymore, Toto. Thanks for replying to email: john@mi-systems.com -- Senior Technologist Magneto-Inductive Systems Ltd. (anti-spamming measures may be in effect)Article: 11145
Hello, does anybody know a EEPROM device that can be used instead of the Xilinx Serial Configuration PROMs XC1700 ? The Problem is, that the standard serial EEPROMs (like 24C08) donīt have identical timing and the same easy-to-use internal adress counter... Thanx for every hint WolfgangArticle: 11146
ATT made a set of compatible devices for the Xilinx family of XC1700 parts. They had an added advantage of being reprogrammable. Erich Wagner Freiberger Wolfgang wrote in message <35B489E0.71FA863@mail.fgb.mw.tu-muenchen.de>... >Hello, > >does anybody know a EEPROM device that can be used instead of the Xilinx >Serial Configuration PROMs XC1700 ? The Problem is, that the standard >serial EEPROMs (like 24C08) donīt have identical timing and the same >easy-to-use internal adress counter... > >Thanx for every hint > >Wolfgang >Article: 11147
On Tue, 21 Jul 1998 14:30:24 +0200, Freiberger Wolfgang <freiberg@mail.fgb.mw.tu-muenchen.de> wrote: >Hello, > >does anybody know a EEPROM device that can be used instead of the Xilinx >Serial Configuration PROMs XC1700 ? The Problem is, that the standard >serial EEPROMs (like 24C08) don?t have identical timing and the same >easy-to-use internal adress counter... > >Thanx for every hint > >Wolfgang AT17C... family from ATMEL. Look at www.atmel.com and search for FPGA configuration E2PROMs. -- Christopher Rozniak Gdansk, Poland, Europe, Earth E-mail: k.rozniak@XXX.ien.gda.pl remove anty-spam XXX. to emailArticle: 11148
Rickman wrote: > The "how would you design this in hardware" argument doesn't apply this > time. This is exactly how a standard TTL device works, the 74LS193. It > has an up clock and a down clock. Of course it is up to the user to > actuate only one at a time. But then all logic has the caveat of proper > usage. > Just because this was done in a device designed a quarter century ago doesn't make it good design practice. Many of the early TTL counters are also ripple counters (each stage clocked by the output of the previous stage). Yes you can do this in VHDL (you need to combine and decode the clocks, look at the schematic given in an old TTL databook for the '193), but it is not synchronous design. Asynchronous logic should be avoided in FPGA designs, especially in those that will later be ported to an ASIC. Asynchronous design is possible in an FPGA, but it is loaded with pitfalls, is difficult to verify over the range of operating conditions and makes for an expensive translation to ASIC. Don't do it where you don't absolutely have to, you'll just make more headaches for everyone involved. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11149
One site you may want to visit is The Programmable Logic Jump Station at http://www.optimagic.com. It contains a fairly comprehensive set of links to most matters related to CPLDs and FPGAs. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- John Nangreaves wrote in message <01bdb49a$faa013c0$9802a8c0@john-misl>... >I'm jumping in with both feet and my eyes closed... > >Any primer/newbie links to CPLD and/or programmable logic in general >needed please. > >It's been years since I "mapped" a PAL. Now I need a PLD interface >for our micro and external circuits. Using Lattice isp-Synario. >Looking it over, I see I have a lot of catching up to do. Tutorials, >app notes and general technique primers needed. > >I don't think we're in Kansas anymore, Toto. > >Thanks for replying to email: >john@mi-systems.com > >-- >Senior Technologist >Magneto-Inductive Systems Ltd. >(anti-spamming measures may be in effect)
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