Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Mark You might find our Dynamically Reconfigurable Hardware WWW Library a useful source of infos on these issues. Look at http://dec.bournemouth.ac.uk/drhw_lib/ Best --Milan In article <37166B04.5DB4@xs4all.nl>, Mark <mkinsley@xs4all.nl> wrote: > I like to possibilities offered by reconfigurable FPGAs, but it seems > most of the devices around are designed to be loaded once on power up, > and maybe reconfigured to do something different if the designer is > being really ingenuitive. > > I've heard talk of some new FPGAs from Xilinx which alow partial > reconfigurability (6000 series?), but i don't see these as being > particularly more useful.... ? Anyone disagree here ? > > What i think would be really interesting, is being able to re-configure > an entire FPGA really quickly (say 1 system clock period ideally). This > translates into the idea of having 'layers' of FPGA config data which > can be latched into the FPGA config area. The inactive 'layers' being > updated or replaced while not in use -> pretty much like a video display > where an image is built up in the off screen buffer before the active > video buffer is toggled. > > The implications of such an architecture are of course ghastly amounts > of configuration data flying around and a squadron of PentiumIV's > working overtime trying to place, route and load all this into our > liquid cooled UltraFPGA. But if applied to a pretty small block of > reconfigurable logic i think the creative designer could do some really > neat things. > > ....any comments ? > > Are there any such devices out there already ? > > Regds, > Mark K. > > -- Life is about wanting what you don't know you don't want. -- > --== Sent via Deja.com http://www.deja.com/ ==-- ---Share what you know. Learn what you don't.---Article: 16251
Hi, I'm currently develope a graphic interface for my 68040 board at home using FPGA and VDRAM. But I got a very fancy problem with it, which I can't get of it. When the CPU is writing to the RAM, sometimes it also overwrite other locations as well. For example when the cpu is writing on the line X pos Y, it overwrites also some other location on the same line. Could it be some kind of reflection problem? Or some other effects, which I don't know about it? I saw in other designs, they use resistors between DRAM and Mux on the address lines. But some other designs don't. Some use thouse on RAS/CAS, some don't. What is the point of thouse resistors? thanks RomanArticle: 16252
Hi Peter, Are your metastability tests performed on a sample size large enough to be able to estimate worst case figures? Even something like a standard deviation would be nice. So far, all we've been getting have been typical values. Of course, a typical value is better than no value at all, but it makes it hard to employ worst case design methodologies. Also, are you performing tests over temperature? I would expect that the resolution time would be longer at higher temperatures (because the FF gain would be lower), but I'm just guessing. Keep up the good work, Allan. On Mon, 10 May 1999 09:21:33 -0700, Peter Alfke <peter@xilinx.com> wrote: >Allan Herriman wrote: > >> the metastability parameters >> aren't published in the data sheet. Nice try, though. >> >> Does anyone know why such important parameters *aren't* listed in a >> datasheet, even as typical values? >> >> Allan. > >I can only speak for Xilinx: > >Because hardly anybody asks for the data. >I published a fairly detailed explanation of metastability, test methodology, >and results in the 1989 Xilinx data book, and repeated and improved it in all >the seven or eight subsequent editions, ( look in the index!) but I have sensed >very little interest. >We are about to start a new series of tests, and I will publish the results >again. >Nice to hear that somebody is interested. > >Peter Alfke, Xilinx ApplicationsArticle: 16253
Other than the Nallatech and VCC Virtual Workbench (which we have on order) boards, does anyone know of any other virtex development boards that are currently available. We have money to spend and want to use it now!!!! Many thanks Daryl Bradley -- Bio-Inspired Architectures Department of Electronics University of York, UK http://www-users.york.ac.uk/~dwb105Article: 16254
I have design a small core in VHDL and I would like to know if I use difference tools to synthesize my VHDL code, will the numbers of CLB from those tools be difference. And if you know any excellent tools for synthesize please recommend. realk@thaimail.comArticle: 16255
I have sent you a UART design demo in Verilog from Exemplar (uart.v) ,hope
it 'll be useful for you.
realk@thaimail.com
Dan Oomkes wrote in message <3738805B.CE920511@avionics.bfg.com>...
>I am looking for a simple UART design (without all of the handshaking
>features) in verilog for use in a Xilinx XCS20 device. Does anybody
>know where I could download a free design?
>
begin 666 uart.v
M+R\-"B\O($-O<'ER:6=H=" H8RD@,3DY,BPQ.3DS+#$Y.30L($5X96UP;&%R
M($QO9VEC($EN8RX@06QL(')I9VAT<R!R97-E<G9E9"X-"B\O#0HO+PT*+R\@
M1&5S8W)I<'1I;VX@.@T*+R\@(" @5&AI<R!697)I;&]G($A$3"!D97-C<FEP
M=&EO;B!I;7!L96UE;G1S(&$@54%25"X-"B\O#0HO+R @(" @5F5R<VEO;B Q
M+C$@.B!/<FEG:6YA;"!#<F5A=&EO;@T*+R\@(" @(" @(" @(" @,BXQ(#H@
M861D960@8V]M;65N=',-"B\O#0H-"@T*;6]D=6QE('5A<G0@*&-L:W@Q-BP@
M<F5A9"P@=W)I=&4L(')X+"!R97-E="P@='@L(')X<F1Y+"!T>')D>2P@#0H@
M(" @(" @(" @(" @<&%R:71Y97)R+"!F<F%M:6YG97)R+"!O=F5R<G5N+"!D
M871A*3L-"@T*:6YP=70@(" @(" @(" @8VQK>#$V.PD)+R\@26YP=70@8VQO
M8VLN(#$V>"!B:70@8VQO8VL-"FEN<'5T(" @(" @(" @(" @<F5A9#L)"2\O
M(%)E8V5I=F5D(&1A=&$@<F5A9"!S=')O8F4-"FEN<'5T(" @(" @(" @("!W
M<FET93L)"2\O(%1R86YS;6ET(&1A=&$@=W)I=&4@<W1R;V)E#0II;G!U= D@
M(" @("!R>#L)"2\O(%)E8V5I=F4@(&1A=&$@;&EN90T*:6YP=70)(" @<F5S
M970["0DO+R!C;&5A<B!D97!E;F1E;F-I97,-"F]U='!U= D@(" @("!T>#L)
M"2\O(%1R86YS;6ET(&1A=&$@;&EN90T*;W5T<'5T(" @(" @(" @("!R>')D
M>3L)"2\O(%)E8V5I=F5D(&1A=&$@<F5A9'D@=&\@8F4@<F5A9 T*;W5T<'5T
M(" @(" @(" @("!T>')D>3L)"2\O(%1R86YS;6ET=&5R(')E861Y(&9O<B!N
M97AT(&)Y=&4-"F]U='!U=" @(" @("!P87)I='EE<G(["0DO+R!296-E:79E
M<B!P87)I='D@97)R;W(-"F]U='!U=" @(" @(&9R86UI;F=E<G(["0DO+R!2
M96-E:79E<B!F<F%M:6YG(&5R<F]R#0IO=71P=70@(" @(" @("!O=F5R<G5N
M.PD)+R\@4F5C96EV97(@;W9E<G)U;B!E<G)O<B -"FEN;W5T(" @(" @(%LP
M.C==(&1A=&$[("\O($)I9&ER96-T:6]N86P@9&%T82!B=7,-"@T*<F5G"2 @
M(" @('1X.PD)+R\@5')A;G-M:70@9&%T82!L:6YE#0IR96<@(" @(" @("!O
M=F5R<G5N.PD)+R\@4F5C96EV97(@;W9E<G)U;B!E<G)O<B -"G)E9R @(" @
M(&9R86UI;F=E<G(["0DO+R!296-E:79E<B!F<F%M:6YG(&5R<F]R#0IR96<@
M(" @(" @<&%R:71Y97)R.PD)+R\@4F5C96EV97(@<&%R:71Y(&5R<F]R#0H-
M"B\O(%1R86YS;6ET(&1A=&$@:&]L9&EN9R!R96=I<W1E<@T*(" @('=I<F4@
M6S Z-UT@='AH;VQD(#L-"@T*+R\@5')A;G-M:70@<VAI9G0@<F5G:7-T97(@
M8FET<PT*(" @(')E9R!;,#HW72!T>')E9SL-"B @("!R96<@(" @("!T>'1A
M9S(@(#L)"2\O('1A9R!B:71S(&9O<B!D971E8W1I;F<@#0H@(" @<F5G(" @
M(" @='AT86<Q(" ["0DO+R @("!E;7!T>2!S:&EF="!R96<-"B @("!R96<@
M(" @='AP87)I='D@(#L)"2\O(%!A<FET>2!G96YE<F%T:6]N(')E9VES=&5R
M#0H-"B\O(%1R86YS;6ET(&-L;V-K(&%N9"!C;VYT<F]L('-I9VYA;',-"B @
M("!R96<@(" @(" @='AC;&L@(#L@(" @(" @"2\O(%1R86YS;6ET(&-L;V-K
M.B Q+S$V=&@@;V8@8VQK>#$V#0H@(" @=VER92 @(" @('1X9&]N92 @.PD)
M+R\@,2=B,2!W:&5N('-H:69T:6YG(&]F(&)Y=&4@:7,@9&]N90T*(" @('=I
M<F4@<&%R:71Y8WEC;&4@(#L)"2\O(#$G8C$@;VX@;F5X="!T;R!L87-T('-H
M:69T(&-Y8VQE#0H@(" @<F5G(" @='AD871A<F1Y(" [(" @(" @( DO+R Q
M)V(Q('=H96X@9&%T82!I<R!R96%D>2!I;B!T>&AO;&0-"@T*+R\@4F5C96EV
M92!S:&EF="!R96=I<W1E<B!B:71S#0H@(" @<F5G(%LP.C==(')X:&]L9#L@
M(" O+R!(;VQD<R!R96-E:79E9"!D871A(&9O<B!R96%D#0H@(" @<F5G(%LP
M.C==(')X<F5G.R @("\O(%)E8V5I=F4@9&%T82!S:&EF="!R96=I<W1E<@T*
M(" @(')E9R @("!R>'!A<FET>2 @.PD)+R\@4&%R:71Y(&)I="!O9B!R96-E
M:79E9"!D871A#0H@(" @<F5G(" @<&%R:71Y9V5N(" ["0DO+R!'96YE<F%T
M960@<&%R:71Y(&]F(')E8V5I=F5D(&1A=&$-"B @("!R96<@(" @("!R>'-T
M;W @(#L)"2\O(%-T;W @8FET(&]F(')E8V5I=F5D(&1A=&$-"@T*+R\@4F5C
M96EV92!C;&]C:R!A;F0@8V]N=')O;"!S:6=N86QS#0H@(" @<F5G(" @(" @
M(')X8VQK(" ["0DO+R!296-E:79E(&1A=&$@<VAI9G0@8VQO8VL-"B @("!R
M96<@(" @("!R>&ED;&4@(#L@(" @(" @"2\O(#$G8C$@=VAE;B!R96-E:79E
M<B!I<R!I9&QI;F<-"B @("!R96<@("!R>&1A=&%R9'D@(#L@(" @(" @"2\O
M(#$G8C$@=VAE;B!D871A(&ES(')E861Y('1O(&)E(')E860-"@T*#0IR96<@
M6S(Z,%T@8VYT.PT*#0H-"B\O(%1O9V=L92!T>&-L:R!E=F5R>2 X(&-O=6YT
M<RP@=VAI8V@@9&EV:61E<R!T:&4@8VQO8VL@8GD@,38-"@T*86QW87ES($ H
M<&]S961G92!C;&MX,38I#0H@("!B96=I;@T*"6EF("AR97-E="D-"@D@(" @
M='AC;&L@/2 Q)V(P.PT*"65L<V4@:68@*&-N=" ]/2 S)V(P,# I(" -"@D@
M(" @='AC;&L@/2 A='AC;&L[( T*#0H):68@*')E<V5T*0T*"2 @("!C;G0@
M/2 S)V(P,# [#0H)96QS90T*"2 @("!C;G0@/2!C;G0@*R Q.PT*(" @(&5N
M9 T*#0IR96<@6S Z,UT@<GAC;G0[(" @(" @+R\@0V]U;G0@;V8@8VQO8VL@
M8WEC;&5S#0IR96<@<G@Q+"!H=6YT.R @(" @(" @+R]R>"!D96QA>65D(&]N
M92!C>6-L92P@($AU;G1I;F<@9F]R('-T87)T(&)I= T*#0H-"F%L=V%Y<R!
M*'!O<V5D9V4@8VQK>#$V*0T*8F5G:6X-"B\O(')X8VQK(#T@8VQK>#$V(&1I
M=FED960@8GD@,38@#0H@(" @(" @(')X8VQK(#T@<GAC;G1;,%T[#0H-"B\O
M($AU;G0],2!W:&5N('=E(&%R92!L;V]K:6YG(&9O<B!A('-T87)T(&)I=#H-
M"B\O(" @02!S=&%R="!B:70@:7,@96EG:'0@8VQO8VL@=&EM97,@=VET:"!R
M>#TP(&%F=&5R(&$@9F%L;&EN9R!E9&=E( T*#0H):68@*')E<V5T*0T*"2 @
M("!H=6YT(#T@,2=B,#L-"@EE;'-E(&EF("AR>&ED;&4@)B8@(7)X("8F(')X
M,2 I( T*+R\@4W1A<G0@:'5N=&EN9R!W:&5N(&ED;&4@86YD(&9A;&QI;F<@
M961G92!I<R!F;W5N9 T*"2 @("!H=6YT(#T@,2=B,3L-"@EE;'-E(&EF("@A
M<GAI9&QE('Q\(')X("D@#0HO+R!3=&]P(&AU;G1I;F<@=VAE;B!S:&EF=&EN
M9R!I;B!D871A(&]R(&$@,2!I<R!F;W5N9"!O;B!R> T*"2 @("!H=6YT(#T@
M,2=B,#L-"@T*"7)X,2 ](')X.PDO+R!R>"!D96QA>65D(&)Y(&]N92!C;&]C
M:R!F;W(@961G92!D971E8W1I;VX-"@D)"2\O("A-=7-T(&)E(&%S<VEG;F5D
M($%&5$52(')E9F5R96YC92D-"@T*+R\@26YC<F5M96YT(&-O=6YT('=H96X@
M;F]T(&ED;&EN9R!O<B!W:&5N(&AU;G1I;F<-"@EI9B H(7)X:61L92!\?"!H
M=6YT*2 -"@D@(" @+R\@0V]U;G0@8VQO8VMS('=H96X@;F]T(')X:61L92!O
M<B!H=6YT:6YG(&9O<B!S=&%R="!B:70-"@D@(" @<GAC;G0@/2!R>&-N=" K
M(#$[#0H)96QS90T*"2 @(" O+R!H;VQD(&%T(#$@=VAE;B!R>&ED;&4@86YD
M('=A:71I;F<@9F]R(&9A;&QI;F<@961G90T*"2 @("!R>&-N=" ](#0G8C P
M,#$[#0IE;F0-"@T*86QW87ES($ H<&]S961G92!T>&-L:RD-"F)E9VEN#0H)
M:68@*'1X9&]N92 F)B!T>&1A=&%R9'DI#0H)(" @(&)E9VEN#0H)(" @("\O
M($EN:71I86QI>F4@<F5G:7-T97)S(&%N9"!L;V%D(&YE>'0@8GET92!O9B!D
M871A#0H)(" @('1X<F5G(" @(#T@='AH;VQD.PDO+R!,;V%D('1X(')E9VES
M=&5R(&9R;VT@='AH;VQD#0H)(" @('1X=&%G,B @(#T@,2=B,3L)+R\@5&%G
M(&)I=',@9F]R(&1E=&5C=&EN9R -"@D@(" @='AT86<Q(" @/2 Q)V(Q.PDO
M+R @("!W:&5N('-H:69T:6YG(&ES(&1O;F4-"@D@(" @='AP87)I='D@/2 Q
M)V(Q.PDO+R!087)I='D@8FET+B!);FET:6%L:7II;F<@=&\@,2 ](&]D9"!P
M87)I='D-"@D@(" @='@@(" @(" @/2 Q)V(P.PDO+R!3=&%R="!B:70-"B @
M(" @(" @(" @(&5N9 T*"65L<V4-"@D@(" @8F5G:6X-"@D@(" @+R\@4VAI
M9G0@9&%T80T*"2 @(" O+R!B=6<@:6X@87-S:6=N:6YG('1O('-L:6-E<PT*
M"2 @(" O+R!T>')E9R@P(%1/(#8I(#T@='AR96<H,2!43R W*3L-"@D@(" @
M+R\@='AR96<H-RD@(" @(" ]('1X=&%G,3L-"@D@(" @='AR96<@"3T@>W1X
M<F5G6S$@.B W72P@='AT86<Q?3L-"@D@(" @='AT86<Q(" @(" @/2!T>'1A
M9S([#0H)(" @('1X=&%G,@D](#$G8C [#0H-"@D@(" @+R\@1F]R;2!P87)I
M='D@87,@96%C:"!B:70@9V]E<R!B>0T*"2 @("!T>'!A<FET>2 @(" @(#T@
M='AP87)I='D@7B!T>')E9ULP73L-"@T*"2 @(" O+R!3:&EF="!O=70@9&%T
M82!O<B!P87)I='D@8FET(&]R('-T;W O:61L92!B:70-"@D@(" @:68@*'1X
M9&]N92 I#0H)"71X(#T@,2=B,3L)+R\@<W1O<"]I9&QE(&)I= T*"2 @("!E
M;'-E(&EF("AP87)I='EC>6-L92D-"@D)='@@/2!T>'!A<FET>3L)+R\@4&%R
M:71Y(&)I= T*"2 @("!E;'-E#0H)"71X(#T@='AR96=;,%T["2\O4VAI9G0@
M9&%T82!B:70-"@D@(" @96YD#0IE;F0-"@T*+R\@<&%R:71Y8WEC;&4@/2 Q
M(&]N(&YE>'0@=&\@;&%S="!C>6-L92 H5VAE;B!T>'1A9S(@:&%S(')E86-H
M960@='AR96<H,2DI#0HO+R @("A%;F%B;&5S('!U='1I;F<@=&AE('!A<FET
M>2!B:70@;W5T(&]N('1X*0T*87-S:6=N(" @('!A<FET>6-Y8VQE(#T@='AR
M96=;,5T@)B8@(2AT>'1A9S(@?'P@='AT86<Q('Q\( T*"0D)"2 @(" @='AR
M96=;-UT@?'P@='AR96=;-ET@?'P@='AR96=;-5T@?'P@#0H)"0D)(" @("!T
M>')E9ULT72!\?"!T>')E9ULS72!\?"!T>')E9ULR72D[#0H-"B\O('1X9&]N
M92 ](#$@=VAE;B!D;VYE('-H:69T:6YG(%M7:&5N('1X=&%G,B!H87,@<F5A
M8VAE9"!T>%T-"F%S<VEG;B @("!T>&1O;F4@/2 A*'1X=&%G,B!\?"!T>'1A
M9S$@?'P-"@D)("!T>')E9ULW72!\?"!T>')E9ULV72!\?"!T>')E9ULU72!\
M?"!T>')E9ULT72!\?" -"@D)("!T>')E9ULS72!\?"!T>')E9ULR72!\?"!T
M>')E9ULQ72!\?"!T>')E9ULP72D[#0H-"B\O(%-H:69T(&1A=&$@;VX@96%C
M:"!R>&-L:R!W:&5N(&YO="!I9&QI;F<-"F%L=V%Y<R! *'!O<V5D9V4@<GAC
M;&LI#0H@(&)E9VEN( T*"6EF("AR>&ED;&4I#0H)(" @("\O($QO860@86QL
M(&]N97,@=VAE;B!I9&QI;F<-"@D@(" @8F5G:6X-"@D@(" @<GAR96<@/2 X
M)V(Q,3$Q,3$Q,3L-"@D@(" @<GAP87)I='D@/2 Q)V(Q.PT*"2 @("!P87)I
M='EG96X@/2 Q)V(Q.PDO+R!/9&0@<&%R:71Y#0H)(" @(')X<W1O<" ](#$G
M8C [#0H)(" @(&5N9 T*"65L<V4-"@D@(" @+R\@4VAI9G0@9&%T82!W:&5N
M(&YO="!I9&QI;F<-"@D@(" @+R\@8G5G(&EN(&%S<VEG;FEN9R!T;R!S;&EC
M97,-"@D@(" @+R\@<GAR96<@*# @5$\@-BD@/2!R>')E9R H,2!43R W*3L-
M"@D@(" @+R\@<GAR96<H-RD@/2!R>'!A<FET>3L-"@D@(" @8F5G:6X-"@D@
M(" @<GAR96<@/2![<GAR96<@6S$@.B W72P@<GAP87)I='E].PT*"2 @("!R
M>'!A<FET>2 ](')X<W1O<#L-"@D@(" @<&%R:71Y9V5N(#T@<&%R:71Y9V5N
M(%X@<GAS=&]P.PDO+R!&;W)M('!A<FET>2!A<R!D871A('-H:69T<R!B>0T*
M"2 @("!R>'-T;W @/2!R>#L-"B @(" @(" @(" @(&5N9 T*(" @96YD#0H-
M"B @(" -"B\O(')X:61L92!R97%U:7)E<R!A<WEN8R!P<F5S970@<VEN8V4@
M:70@:7,@8VQO8VME9"!B>2!R>&-L:R!A;F0@( T*+R\@:71S('9A;'5E(&1E
M=&5R;6EN97,@=VAE=&AE<B!R>&-L:R!G971S(&=E;F5R871E9" -"F%L=V%Y
M<R! *'!O<V5D9V4@<GAC;&L@;W(@<&]S961G92!R97-E="D-"B @("!B96=I
M;@T*(" @(" @("!I9B H<F5S970I#0H@(" @(" @(" @(')X:61L92 ](#$G
M8C [#0H@(" @(" @(&5L<V4@#0H@(" @(" @(" @(')X:61L92 ]("%R>&ED
M;&4@)B8@(7)X<F5G6S!=.PT*(" @(&5N9 T*#0HO+R!,;V%D('1X:&]L9"!A
M;F0@<V5T('1X9&%T87)D>2!O;B!F86QL:6YG(&5D9V4@;V8@=W)I=&4-"B\O
M($-L96%R('1X9&%T87)D>2!O;B!F86QL:6YG(&5D9V4@;V8@='AD;VYE#0H)
M<F5G('=R,2QW<C(["2\O('=R:71E('-I9VYA;"!D96QA>65D(#$@86YD(#(@
M8WEC;&5S#0H)<F5G('1X9&]N93$[(" @(" @(" O+R!T>&1O;F4@<VEG;F%L
M(&1E;&%Y960@;VYE(&-Y8VQE#0IA;'=A>7,@0"AP;W-E9&=E(&-L:W@Q-BD-
M"B @("!B96=I;@T*"6EF("AR97-E="D-"@D@(" @='AD871A<F1Y(#T@,2=B
M,#L-"@EE;'-E(&EF("@A=W(Q("8F("!W<C(I#0H)(" @("\O($9A;&QI;F<@
M961G92!O;B!W<FET92!S:6=N86PN($YE=R!D871A(&EN('1X:&]L9"!L871C
M:&5S#0H)(" @('1X9&%T87)D>2 @/2 Q)V(Q.PT*"65L<V4@:68@*"%T>&1O
M;F4@)B8@('1X9&]N93$I#0H)(" @("\O($9A;&QI;F<@961G92!O;B!T>&1O
M;F4@<VEG;F%L+B!4>&AO;&0@:&%S(&)E96X@<F5A9"X-"@D@(" @='AD871A
M<F1Y(" ](#$G8C [#0H-"@DO+R!$96QA>65D('9E<G-I;VYS(&]F('=R:71E
M(&%N9"!T>&1O;F4@<VEG;F%L<R!F;W(@961G92!D971E8W1I;VX-"@EW<C(@
M/2!W<C$[#0H)=W(Q(#T@=W)I=&4[#0H)='AD;VYE,2 ]('1X9&]N93L-"B @
M("!E;F0@#0H-"@ER96<@<F0Q+"!R9#(@.PDO+R!296%D(&EN<'5T(&1E;&%Y
M960@,2!A;F0@,B!C>6-L97,-"@ER96<@<GAI9&QE,2 @.PDO+R!R>&ED;&4@
M<VEG;F%L(&1E;&%Y960@,2!C>6-L90T*86QW87ES($ H<&]S961G92!C;&MX
M,38I#0H@(" @8F5G:6X-"@T*"2\O($QO;VL@9F]R(')I<VEN9R!E9&=E(&]N
M(&ED;&4@86YD('5P9&%T92!O=71P=70@<F5G:7-T97)S#0H):68@*')X:61L
M92 F)B A<GAI9&QE,2D-"@EB96=I;@T*"2 @("!I9B H<GAD871A<F1Y*0T*
M"0DO+R!/=F5R<G5N(&5R<F]R(&EF('!R979I;W5S(&1A=&$@:7,@<W1I;&P@
M=&AE<F4-"@D);W9E<G)U;B ](#$G8C$[#0H)(" @(&5L<V4-"@D)8F5G:6X-
M"@D)+R\@3F\@;W9E<G)U;B!E<G)O<B!S:6YC92!H;VQD:6YG(')E9VES=&5R
M(&ES(&5M<'1Y#0H)"6]V97)R=6X@/2 Q)V(P.PT*#0H)"2\O(%5P9&%T92!H
M;VQD:6YG(')E9VES=&5R#0H)"7)X:&]L9" ](')X<F5G.PT*#0H)"2\O('!A
M<FET>6=E;B ](#$@:68@<&%R:71Y(&5R<F]R#0H)"7!A<FET>65R<B ]('!A
M<FET>6=E;CL-"@T*"0DO+R!&<F%M:6YG97)R;W(@:68@<W1O<"!B:70@:7,@
M;F]T(#$-"@D)9G)A;6EN9V5R<B ](" A<GAS=&]P.PT*#0H)"2\O(%-I9VYA
M;"!T:&%T(&1A=&$@:7,@<F5A9'D@9F]R(')E861I;F<-"@D)<GAD871A<F1Y
M(#T@,2=B,3L-"@D@(" @(" @(&5N9 T*"65N9 T*"7)X:61L93$@/2!R>&ED
M;&4["2\O(')X:61L92!D96QA>65D(#$@8WEC;&4@9F]R(&5D9V4@9&5T96-T
M#0H-"@DO+R @0VQE87(@97)R;W(@86YD(&1A=&$@<F5G:7-T97)S('=H96X@
M9&%T82!I<R!R96%D#0H):68@*"%R9#(@)B8@(')D,2D-"@D@(" @8F5G:6X@
M#0H)(" @(')X9&%T87)D>2 @/2 Q)V(P.PT*"2 @("!P87)I='EE<G(@(#T@
M,2=B,#L-"@D@(" @9G)A;6EN9V5R<B ](#$G8C [#0H)(" @(&]V97)R=6X@
M(" @/2 Q)V(P.PT*"2 @("!E;F0@#0H)<F0R(#T@<F0Q.PDO+R!%9&=E(&1E
M=&5C="!F;W(@<F5A9 T*"7)D,2 ](')E860["2\O("A-=7-T(&)E(&%S<VEG
M;F5D($%&5$52(')E9F5R96YC92D-"@EI9B H<F5S970I( T*"2 @("!R>&1A
M=&%R9'D@/2 Q)V(P.PT*(" @(&5N9 T*#0HO+R!$<FEV92!D871A(&)U<R!O
M;FQY(&1U<FEN9R!R96%D#0IA<W-I9VX@(" @9&%T82 ](')E860@/R @<GAH
M;VQD(#H@."=B>GIZ>GIZ>GH[#0H-"B\O($QA=&-H(&1A=&$@8G5S(&1U<FEN
M9R!W<FET90T*87-S:6=N(" @('1X:&]L9" ]('=R:71E(#\@9&%T82 Z('1X
M:&]L9#L-"@T*+R\@4F5C96EV92!D871A(')E861Y(&]U='!U="!S:6=N86P-
M"F%S<VEG;B @("!R>')D>2 ](')X9&%T87)D>3L-"@T*+R\@5')A;G-M:71T
M97(@<F5A9'D@9F]R('=R:71E('=H96X@;F\@9&%T82!I<R!I;B!T>&AO;&0-
M"F%S<VEG;B @("!T>')D>2 ]("%T>&1A=&%R9'D[#0H-"@T*96YD;6]D=6QE
"#0H`
`
end
Article: 16256
Jonas Thor wrote:
>
> Hello,
> I know I can cascade two flip-flops, but are
> there other/better ways?
Adding to all wise things mentioned already I recommend you a
paper by Charles Seitz and others.
"Pipeline synchronizers" or something like that.
You find it somewhere on www.myri.com.
Andreas
--
---------------------------------------------------------------
Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Ratzeburger Allee 160
D-23538 Luebeck Germany
Tel.: +49 451 500-3741, Fax: -3687
Email: doering@iti.mu-luebeck.de
Home: http://www.iti.mu-luebeck.de/~doering
quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------
Article: 16257roman pollak <roman.pollak@Sun.COM> wrote in <37394D92.7080B6C0@Sun.COM>: > Hi, > > > I'm currently develope a graphic interface for my 68040 board at home > using FPGA and VDRAM. > But I got a very fancy problem with it, which I can't get of it. > When the CPU is writing to the RAM, sometimes it also overwrite other > locations as well. > For example when the cpu is writing on the line X pos Y, it overwrites > also some other location on the same line. Could it be some kind of > reflection problem? Or some other effects, which I don't know about it? > I saw in other designs, they use resistors between DRAM and Mux on the > address lines. But some other designs don't. Some use thouse on RAS/CAS, > some don't. What is the point of thouse resistors? > > thanks Roman The point of those resistors is to cut over/undershoot by impedance matching the wires between the mux source and DRAM destination. On the DRAM designs I've done, it's very important to get this right. I don't know that this is what's causing your problem - the problems caused by overshoot on RAS/CAS/Address tend to be very random and non-repeatable. If you have a repeatable problem, there's probably a logic error.Article: 16258
Allan Herriman wrote: > Hi Peter, > Are your metastability tests performed on a sample size large > enough to be able to estimate worst case figures? > > Even something like a standard deviation would be nice. > > So far, all we've been getting have been typical values. Of course, a > typical value is better than no value at all, but it makes it hard to > employ worst case design methodologies. > > Also, are you performing tests over temperature? I would expect that > the resolution time would be longer at higher temperatures (because > the FF gain would be lower), but I'm just guessing. a quick fun fact ... got more data somewhere ... from "metastability of cmos latch/flip-flop" by lee-sup kim, ieee journal of solid-state circuits, august '90, ... "in fig. 14, the measurement results corresponding to t=50, 75, 100, and 125c are shown, respectively. as expected, the higher chip temperature gives rise to higher failure rates. about 75C of temperature difference causes four orders of magnitude degradation in MTBF. ... " have more data, and i know i have some signetics stuff somewhere ... rkArticle: 16259
We have on order a Virtex based PCI board (RC1010-PP) from http://www.embedded-solutions.ltd.uk/ As far as we know, the price will be about $6500 for a board equipped with a XCV1000. Christof Daryl Bradley wrote: > > Other than the Nallatech and VCC Virtual Workbench (which we have on > order) boards, does anyone know of any other virtex development boards > that are currently available. > > We have money to spend and want to use it now!!!! ________________________________________________________________________ Christof Teuscher Tel.: +41 21 693 47 92 Logic Systems Laboratory Fax: +41 21 693 37 05 Swiss Federal Institute of Technology christof.teuscher@epfl.ch EPFL-DI-LSL http://lslwww.epfl.ch/ CH - 1015 Lausanne http://www.teuschers.ch/christof ________________________________________________________________________Article: 16260
Peter, I have to disagree here. Clock rates in today's systems are quite a bit higher than they were 10 years ago. With system clocks near 100 MHz and aynch inputs with even half that rate, metastability is as scary as ever. It would be really nice to have the numbers instead of just guessing. Peter Alfke wrote: > There is no way ( NO WAY ! ) to avoid metastability, but modern circuits resolve > it so fast that metastability is no longer the same scary subject it was ten > years ago. > > Peter Alfke, Xilinx Applications -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16261
Why not just sample at the lower rate then. You get considerably more benefit since the likelyhood of a metastable event lasting a whole clock is smaller. Jamie Sanderson wrote: > More often than not, I use the method you've described. Did you read the > same TI document on metastability I did? If you really want something that > is bullet-proof and have gates to spare, you can add a "majority logic" > circuit. > > Add one or two stages to your flip-flop chain, bring it to three or four. > Then take all of the outputs to two logic functions, one which causes the > output to be high only when all flip-flop outputs are high, and one which > causes the output to be low only when all flip-flop outputs are low. That > output signal can also be run through a final flip-flop. > > It slows your signal down considerably, but acts like a low-pass filter. > > Cheers, > Jamie > > Jonas Thor wrote in message <3737b8af.23247503@news1.tninet.se>... > >Hello, > > > >My digital design books don't cover synchronizers in detail. So I am > >asking here and hoping for feedback. Basically I have an asynchronous > >input signal and I want to synchronize this to the FPGA clock. This > >can of course be done by simply sampling the signal with an input > >flip-flop and depending on the clock rate and the characteristic of > >the flip-flop I can estimate a MTBF. But how do I reduce this MTBF by > >designing synchronizer? I know I can cascade two flip-flops, but are > >there other/better ways? > > > >Btw, this just a general question and there is no specific > >application. > > > >Thanks! > >Jonas Thor -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16262
Different tools (and sometimes even different revisions of the same tool) will yield different results. Exemplar and Synplicity are currently the best ones out there for FPGAs. Tippawan Aranwattananon wrote: > I have design a small core in VHDL and I would like to know if I use > difference tools to synthesize my VHDL code, will the numbers of CLB from > those tools be difference. > And if you know any excellent tools for synthesize please recommend. > > realk@thaimail.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16263
In article <37394D92.7080B6C0@Sun.COM>, roman pollak <roman.pollak@Sun.COM> writes:
|> I'm currently develope a graphic interface for my 68040 board at home
|> using FPGA and VDRAM.
|> But I got a very fancy problem with it, which I can't get of it.
|> When the CPU is writing to the RAM, sometimes it also overwrite other
|> locations as well.
|> For example when the cpu is writing on the line X pos Y, it overwrites
|> also some other location on the same line. Could it be some kind of
|> reflection problem? Or some other effects, which I don't know about it?
|> I saw in other designs, they use resistors between DRAM and Mux on the
|> address lines. But some other designs don't. Some use thouse on RAS/CAS,
|> some don't. What is the point of thouse resistors?
The resistors are some sort of series termination to avoid reflections,
especially useful on RAS/CAS. Modern DRAM can react so fast that they interprete
the RAS ringing as access termination and start. Since the DRAM had no time to
write its line buffer back (precharge), the whole line can be destroyed. The
problem you have is possibly a similar effect: If you violate the RAS-low
access time or the precharge time, you will get everything from one-bit-failures
to 4096bit-failures.
Try to relax the timing a bit...
--
Bye
Georg Acher, acher@in.tum.de
http://www.in.tum.de/~acher/
"Oh no, not again !" The bowl of petunias
Article: 16264roman pollak wrote: > > Hi, > > I'm currently develope a graphic interface for my 68040 board at home > using FPGA and VDRAM. > But I got a very fancy problem with it, which I can't get of it. > When the CPU is writing to the RAM, sometimes it also overwrite other > locations as well. > For example when the cpu is writing on the line X pos Y, it overwrites > also some other location on the same line. Could it be some kind of > reflection problem? Or some other effects, which I don't know about it? > I saw in other designs, they use resistors between DRAM and Mux on the > address lines. But some other designs don't. Some use thouse on RAS/CAS, > some don't. What is the point of thouse resistors? Sounds like the row and column sizes of the controller do not match the DRAM. Unlikely that lack of series terminations would cause this symptom. Mike Treseler, Sr. Staff Engineer Fluke Corporation mailto:tres@tc.fluke.com PO Box 9090 M/S 279F phone:425.356.5409 Everett WA USA 98206-9090 fax:425.356.5043Article: 16265
That's another way of doing it, but equivalent, really. Unless you have an external clock that is synchronous to your desired clock, but slower, you'll have to put in a clock divider anyhow. In other words, you could use up four flip-flops to re-time the signal several times, or four flip-flops to create a clock/4 signal. Either way, I still think that two flip-flops chained together will give you all the protection from metastability that is needed. Of course, I say this from my perspective only, I'm not designing equipment for life support or anything like that. Cheers, Jamie Ray Andraka wrote in message <373985CB.FA9AD40B@ids.net>... >Why not just sample at the lower rate then. You get considerably more benefit >since the likelyhood of a metastable event lasting a whole clock is smaller. > >Jamie Sanderson wrote: > >> More often than not, I use the method you've described. Did you read the >> same TI document on metastability I did? If you really want something that >> is bullet-proof and have gates to spare, you can add a "majority logic" >> circuit. >> >> Add one or two stages to your flip-flop chain, bring it to three or four. >> Then take all of the outputs to two logic functions, one which causes the >> output to be high only when all flip-flop outputs are high, and one which >> causes the output to be low only when all flip-flop outputs are low. That >> output signal can also be run through a final flip-flop. >> >> It slows your signal down considerably, but acts like a low-pass filter. >> >> Cheers, >> JamieArticle: 16266
Allan Herriman wrote: > Hi Peter, > Are your metastability tests performed on a sample size large > enough to be able to estimate worst case figures? > > Even something like a standard deviation would be nice. > > So far, all we've been getting have been typical values. Of course, a > typical value is better than no value at all, but it makes it hard to > employ worst case design methodologies. > > Also, are you performing tests over temperature? I would expect that > the resolution time would be longer at higher temperatures (because > the FF gain would be lower), but I'm just guessing. > > Keep up the good work, > Allan. > Thanks, Allan. We will test fast and slow devices, room temperature and hot. That should cover the spread. These are manually driven and interpreted bench tests, so there is a limit to the data volume. The reason these numbers end up in app notes and not the data sheet proper is that the world expects data sheet information to be 100% tested and guaranteed. And metastability numbers cannot be tested in production. On the other hand, there is no reason to expect wild fluctuations. The delay is determined by the gain-bandwidth product of a tightly-knit design, the master latch only, so it should be worst at high temperature and low supply voltage and slowest processing ( lowest speed grade ). Peter Alfke, Xilinx ApplicationsArticle: 16267
I've just finished the design of a CompactPCI board (6U) with one Virtex1000 and two synchronous SRAM-modules (2Mx72). It mainly uses rear-panel-I/O (more than 100 signals) and is therefore open for various applications. The PCI-IF is a PLX9054, the FPGA is configured by the PCI-master. Pricing is TBD, but we tend to be expensive. Alfred Fuchs Siemens Austria PSE PRO LMS2 +43/1/1707-34113 Atif Zafar schrieb: > Hello: > > Does anyone know of any development boards (PCI) that use the Virtex > FPGA? I am interested in a board with preferably several XV800 or XV1000 > devices along with RAM for prototyping a custom graphics pipeline. I > have heard of the PCI Pamette board, but to my knowledge this does not > have Virtex silicon. Thanks for any info. > > Atif Zafar > Regenstrief Institute > Zafar_A@regenstrief.iupui.eduArticle: 16268
Daryl, You might try Annapolis Microsystems at: http://www.annapmicro.com/PR9126.html - it can be used for development in Reconfigurable Computing applications. It has connectors for add-on boards and various I/O extenders. Plus, they'll help you spend your money! Cheers, Jonathan Daryl Bradley wrote: > > Other than the Nallatech and VCC Virtual Workbench (which we have on > order) boards, does anyone know of any other virtex development boards > that are currently available. > > We have money to spend and want to use it now!!!! -- Jonathan F. Feifarek Consulting and design Programmable logic solutionsArticle: 16269
Hellow Everyone.
I'm T.Koyama
Can use Pullup in XC9500XL when user operation.
XC9500 does not use Pullup, but XC9500XL?
If it can use, Please teuch me how use.
Thank you
T.Koyama (basaro@fa2.so-net.ne.jp)
Article: 16270I did an algorithm in C language and I want to do the implementation on a FPGA. The algorithm is on floating points and I would like to transfert that on fixed points. Any good software that do the conversion AUTOMATICALY ? Do they calculate the quantization error ?Article: 16271
I'm looking for some good books or papers on the conversion floating points to fixed points for a hardware implementation. I know that L.R.Rabiner is a excellent author, any other one ?Article: 16272
Jean-Francois Richard wrote: > I did an algorithm in C language and I want to do > the implementation on a FPGA. The algorithm is on > floating points and I would like to > transfert that on fixed points. > > Any good software that do the conversion AUTOMATICALY ? > Do they calculate the quantization error ? There was a really great paper from the Chinese University of Hong Kong given by M.P. Leong mpleong@cse.cuhk.edu.hk called "Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping" I was very impressed with the results. -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 16273
Peter Alfke wrote: > There is no way ( NO WAY ! ) to avoid metastability... I used to teach a course in digital design in which I covered metastability. I would stand there in class and say "there is no way (NO WAY!) to avoid metastability", and I would refer the students to the same statement and explanation in their textbook, and every year at least one student would come to me with a circuit s/he claimed would be metastable-free. I would patiently explain why it wouldn't work, but there are always a few who won't believe. I'm sure they're the same students who are designing perpetual-motion machines for their thermodynamics lecturers, too! ;-) MarkArticle: 16274
hhk <hhk@wxs.nl> wrote: > On Fri, 30 Apr 1999 19:18:40 -0700, "Iwan Santoso Oei" > <iwanoei@mindspring.com> wrote: >>Hi, i am new guys in this room. Because i will make a thesis in FPGA topic, >>if you don't mind, tell me about FPGA is. If I were you I'd chose a thesis in an area with a little more knowledge, to speak of.... ;-) >>1. What is FPGA? Is the function of FPGA can do the same like >>Microcontrolller? Well, you can program an FPGA to emulate a microcontroller, or its functiuonality, but they are two different things. >>2. I confuse if FPGA programmable from the beginning(using VHDL or Verilog), >>how can we change the design when we already made it? >>3. If the FPGA can do the same function like Microcontroller(such as >>Motorola 68HC11), is that any possibilities that FPGA will replace >>Microcontroller in the future? In general -- NO. They're like apples and oranges. If you have a microcontroller that does something relatively simple you can replace that with a state machine implemented in an FPGA, but for most uses that's not economical. >> >>Thanks for your attention and help >> >> >> > Hi, I am a student in electronics so i don't know too much about it. > But FPGA stands for Field Programmable Gate Array. And is not > something like a microcontroler. So it won't replace it. > A microcontoler is continuisly driven by software. It's driven by the clock signal and it's executing instructions. > An FPGA is some > kind of board filled with and/or/xor etc. ports. Not exactly. > Using these ports a > complete PCB can be programmed into the device. Depending on the used > technology the FPGA can be reprogramed or not. > To change the design you have to change your VHDL design and implement > the desing again. > As i don't know evry thing I just can advise you to visit the internet > site of Xilinx (great site) Actel and altera. These are all > manufacturers of FPGA's and PLD's.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z