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Hello, My digital design books don't cover synchronizers in detail. So I am asking here and hoping for feedback. Basically I have an asynchronous input signal and I want to synchronize this to the FPGA clock. This can of course be done by simply sampling the signal with an input flip-flop and depending on the clock rate and the characteristic of the flip-flop I can estimate a MTBF. But how do I reduce this MTBF by designing synchronizer? I know I can cascade two flip-flops, but are there other/better ways? Btw, this just a general question and there is no specific application. Thanks! Jonas ThorArticle: 16226
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> I want to design USB core, Could anyone help me to get USB data or specification to design. And step to design core using VHDL. <br>Please email me at kvocharo@kmitl.ac.th</html>Article: 16227
With PLDs I have builded years ago the following good working design: Connect the input signal to a transparent latch with Latch-Enable= CLOCK. When the CLOCK is high, the output follows immediatly the input signal. After CLOCK is going low, the output of the latch is freezed and can not change more, so the setup-time of the subsequent D-type register can be satisfied. If you design the transparent latch with gates, switch off the optimizer, because it is essential to use all redundant terms in the feedback path to avoid glitches. This device does not exhibit metastability behavior at the expense of loss of maximal one takt cycle latency, and the input signal must be valid for longer as one takt cycle for secure detection. Jonas Thor schrieb: > Hello, > > My digital design books don't cover synchronizers in detail. So I am > asking here and hoping for feedback. Basically I have an asynchronous > input signal and I want to synchronize this to the FPGA clock. This > can of course be done by simply sampling the signal with an input > flip-flop and depending on the clock rate and the characteristic of > the flip-flop I can estimate a MTBF. But how do I reduce this MTBF by > designing synchronizer? I know I can cascade two flip-flops, but are > there other/better ways? > > Btw, this just a general question and there is no specific > application. > > Thanks! > Jonas ThorArticle: 16228
Jonas Thor wrote: > Hello, > > My digital design books don't cover synchronizers in detail. So I am > asking here and hoping for feedback. Basically I have an asynchronous > input signal and I want to synchronize this to the FPGA clock. This > can of course be done by simply sampling the signal with an input > flip-flop and depending on the clock rate and the characteristic of > the flip-flop I can estimate a MTBF. But how do I reduce this MTBF by > designing synchronizer? I know I can cascade two flip-flops, but are > there other/better ways? > No, not at all! > Btw, this just a general question and there is no specific > application. > > Thanks! > Jonas ThorArticle: 16229
What do you mean by large? In many FPGA's you can relative fast counters by using carry logic chains up to say 32 bits. But you must enable the carry logic in both the synthesis and sometimes also the palce and route tool. If you need very big counters like say 64 bits you need special code as carry chains of this length is not alloved by standard settings and may give too much trouble in routing. Make a small counter of 2-4 bits and use MSB Q output as enable for the remaining bits. I have some old code somewhere if this is not enough send me a mail. Hi Peter "C. Michele Rogers" wrote: > Hi everyone, > > Can Synplicity and Leonardo automatically optimize large binary counters to be > fast? Or do I have to recode them? > > Any help will be highly appreciated. > > Thanks > MicheleArticle: 16230
HELO SIR, The input a single byte(8-bits). Out put should be of 15 bits. Later I will normalize to standard form. The data input rate is in one clock 1 byte has to enter the reciprocator, In the other clock the reciprocal has to come out. Satish Kumar. In article <3730482D.6C7CAD88@ids.net>, Ray Andraka <randraka@ids.net> wrote: > How many bits accuracy do you need?, what is bit width of the input and output?. > What is the required data rate and the available clocks (ie. how many clocks are > allowed to do this). These parameters will greatly affect the implementation. > > satish_me@hotmail.com wrote: > > > Hai, > > I am research fellow from India. For one of my VHDL project I need a > > reciprocator. Like If I give Input 10, The out put should be 1/10 that is 0.1, > > For 3 it should be 0.33. For this I need a VHDL code, or implemented FPGA. > > This should be true for all numbers. > > Any suggestion or code is highly appreciable. Thanks in advance. > > Please communicate to my email:satish_me@hotmail.com > > > > -----------== Posted via Deja News, The Discussion Network ==---------- > > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > --== Sent via Deja.com http://www.deja.com/ ==-- ---Share what you know. Learn what you don't.---Article: 16231
I read lately in business week that there's virtual chip fabs. Anybody know about their web site. I used to work on asic, but the size of my designs are constant. I mean they don't increase in complexity, or don't keep up with the rate of FPGA PLD capacities. Currently I do FPGA's, its a lot more flexible in design, where you can re-program the FPGA. And no NRE charges. But I'm still curious about ASICs and Analog design ? any body knows about the virtual fabs ? can you point me to them ? --== Sent via Deja.com http://www.deja.com/ ==-- ---Share what you know. Learn what you don't.---Article: 16232
What we have done here is to put a via next to each BGA pad (see
drawing). It does need to be tented though.
O O O O
\o \o \o \o
O O O O
\o \o \o \o
etc, etc.
You then don't have to worry about solder wicking and you get your probe
points.
Martin Whitaker wrote:
> When we first came to make a board with a BGA device, the sub-contracter
> who manufactures our boards suggested that we put a via under every pad.
> Apparently, providing the via has a very small diameter (I think < 25
> thou was specified), there is no problem with solder being sucked into
> the via.
<snip>
> Admittedly we haven't manufactured many of these boards, but we haven't
> seen any other problems with the BGA devices. I would be inclined to
> keep the holes for production unless there was any evidence that they
> were reducing reliability - the ability to rework the occasional bad
> joint is well worth having.
>
> Martin
--
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>
Article: 16233You can find a list of available FPGA boards on the Programmable Logic Jump Station at http://www.optimagic.com/boards.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Carl Martin wrote in message <926356074.143.100@news.remarQ.com>... >Looking for a 10k Altera prototype board with a >pc104 or PC-isa or PC-pci interface on one side >and maximum number of io pins on the other side. > >Found one from Nova engineering www.nova-eng.com >are there others > > >Thanks >Carl R. Martin >cmart@hypercon.com > > >Article: 16234
That would be very interested! I have used the Xilinx metasability numbers on several communication applications in the past. While the majority of people may not need the metastability time constant and other information about a specific part or process, for those of us who need it, it is absolutely critical. Try building a tap-delay-line based clock recovery or beating two clocks against each other (with a 4KHz frequency difference) without knowing the metastability parameters of the FPGA you are using and one will not sleep well at night. Peter Alfke wrote: > Nice to hear that somebody is interested. > > Peter Alfke, Xilinx Applications >Article: 16235
The only SDF based problem I have had with Modelsim was with Verilog models. Verilog-XL has extended features which are not supported in Modelsim. I have never had a problem with VHDL models. Since you are not sure about you SDF file generation, are you using the -c VHDL and -f sdf-v2.1 switches? You could also try the ESNUG mailing list. Mail a request to be added to the mailing list to jcooley@world.std.com.Article: 16236
I've actually seen some criticism about multi-level synchronizers not providing the benefit predicted by the math, but until somebody comes up with something better or ASIC and FPGA vendors start implementing metastable hardened FF's, I'm keeping this particular hammer in my toolbox.Article: 16237
More often than not, I use the method you've described. Did you read the same TI document on metastability I did? If you really want something that is bullet-proof and have gates to spare, you can add a "majority logic" circuit. Add one or two stages to your flip-flop chain, bring it to three or four. Then take all of the outputs to two logic functions, one which causes the output to be high only when all flip-flop outputs are high, and one which causes the output to be low only when all flip-flop outputs are low. That output signal can also be run through a final flip-flop. It slows your signal down considerably, but acts like a low-pass filter. Cheers, Jamie Jonas Thor wrote in message <3737b8af.23247503@news1.tninet.se>... >Hello, > >My digital design books don't cover synchronizers in detail. So I am >asking here and hoping for feedback. Basically I have an asynchronous >input signal and I want to synchronize this to the FPGA clock. This >can of course be done by simply sampling the signal with an input >flip-flop and depending on the clock rate and the characteristic of >the flip-flop I can estimate a MTBF. But how do I reduce this MTBF by >designing synchronizer? I know I can cascade two flip-flops, but are >there other/better ways? > >Btw, this just a general question and there is no specific >application. > >Thanks! >Jonas ThorArticle: 16238
Roland Fröhlich wrote: > With PLDs I have builded years ago the following good working design: > > Connect the input signal to a transparent latch with Latch-Enable= CLOCK. > > When the CLOCK is high, the output follows immediatly the input signal. > After CLOCK is going low, the output of the latch is freezed and can not > change more, so the setup-time of the subsequent D-type register can be > satisfied. > If you design the transparent latch with gates, switch off the optimizer, > because > it is essential to use all redundant terms in the feedback path to avoid > glitches. > This device does not exhibit metastability behavior at the expense of > loss of > maximal one takt cycle latency, and the input signal must be valid for > longer as > one takt cycle for secure detection. > Sorry Roland, but you are wrong. A latch is equally as vulnerable to metastable delays as a flip-flop. Actually, it is the master latch in the flip-flop that goes metastable. When the data input changes right at the moment when you stop the latch from being transparent, you get the same unpredictable metastable delay as you get in a flip-flop. There is no way ( NO WAY ! ) to avoid metastability, but modern circuits resolve it so fast that metastability is no longer the same scary subject it was ten years ago. Peter Alfke, Xilinx ApplicationsArticle: 16239
Mentor Graphics is pleased to offer Top Down Hands On workshops in several cities in the Southeast United States. These workshops allow the attendee to spend some hands on time with Renoir, ModelSim, and LeonardoSpectrum, Mentor Graphics integrated FPGA design flow. Workshops are being offered in Deerfield (Ft. Lauderdale are), Florida on May 12th and in Raleigh, NC on May 18th. If you would like more information, check out the detailed information on Mentor's web site at: http://www.mentor.com/region/SE/Workshops/index.html -- ...Mike No Guts, No Glory. +--------------------------------------------------------------+ | Michael P. Walsh mike@rtp-nc.mentorg.com | | mike_walsh@mentorg.com | | Applications Engineering Manager | | Mentor Graphics Corporation V:(919) 484-2505 | | 2525 Meridian Parkway, Suite 260 F:(919) 544-0701 | | Research Triangle Park, North Carolina 27713 | +--------------------------------------------------------------+Article: 16240
You can always have one made with your exact specifications... there are many companies that would do this for you for around 1500.00 to 2000.00 range... me for instance :) Carl Martin <cmart@concom.com> wrote in message news:926356074.143.100@news.remarQ.com... > Looking for a 10k Altera prototype board with a > pc104 or PC-isa or PC-pci interface on one side > and maximum number of io pins on the other side. > > Found one from Nova engineering www.nova-eng.com > are there others > > > Thanks > Carl R. Martin > cmart@hypercon.com > > >Article: 16241
Peter Alfke wrote: > There is no way ( NO WAY ! ) to avoid metastability, but modern circuits resolve > it so fast that metastability is no longer the same scary subject it was ten > years ago. > > Peter Alfke, Xilinx Applications I haven't looked at metastability time constants in a couple years, but it used to be that every generation of technology had better and better numbers but this was offset by the higher and higher operating speeds. Sure, if you take a 10-year old design and run it at the 10-year old clock rate on a state-of-the-art process, you'll [almost] never need to worry about metastability but with today's 0.25um processes at 200+ MHz, 5ns isn't much time for metastability to resolve. For Xilinx, do you know if the metastability constants have surpassed the peak operating speeds in the last few generations? Bob Sugar SiTera Inc. P.S. Peter, are you the app's engineer who wrote the awesome video capture app. note for MMI many years ago?Article: 16242
--------------FFE655841CCD2659E17A4FDF Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Jamie Sanderson wrote: > More often than not, I use the method you've described. Did you read the > same TI document on metastability I did? If you really want something that > is bullet-proof and have gates to spare, you can add a "majority logic" > circuit. > > Add one or two stages to your flip-flop chain, bring it to three or four. > Then take all of the outputs to two logic functions, one which causes the > output to be high only when all flip-flop outputs are high, and one which > causes the output to be low only when all flip-flop outputs are low. That > output signal can also be run through a final flip-flop. > > It slows your signal down considerably, but acts like a low-pass filter. Before everybody cascades three or four flip-flops, and degrades system performance, it might be wiser to look at the statistical data, as published by various manufacturers. For normal designs using modern circuits, clock rates below 50 MHz and asynchronous input rates below 10 MHz a single-stage synchronizer is fully sufficient. For more aggressive clock and data rates, calculate the MTBF. You might be pleasantly surprised how fast the metastable uncertainty resolves itself. For Xilinx FPGAs click on http://www.xilinx.com/xapp/xapp094.pdf Peter Alfke, Xilinx Applications --------------FFE655841CCD2659E17A4FDF Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <BODY BGCOLOR="#FFFFFF"> Jamie Sanderson wrote: <BLOCKQUOTE TYPE=CITE>More often than not, I use the method you've described. Did you read the <BR>same TI document on metastability I did? If you really want something that <BR>is bullet-proof and have gates to spare, you can add a "majority logic" <BR>circuit. <P>Add one or two stages to your flip-flop chain, bring it to three or four. <BR>Then take all of the outputs to two logic functions, one which causes the <BR>output to be high only when all flip-flop outputs are high, and one which <BR>causes the output to be low only when all flip-flop outputs are low. That <BR>output signal can also be run through a final flip-flop. <P>It slows your signal down considerably, but acts like a low-pass filter.</BLOCKQUOTE> Before everybody cascades three or four flip-flops, and degrades system performance, it might be wiser to look at the statistical data, as published by various manufacturers. <BR>For normal designs using modern circuits, clock rates below 50 MHz and asynchronous input rates below 10 MHz a single-stage synchronizer is fully sufficient. For more aggressive clock and data rates, calculate the MTBF. You might be pleasantly surprised how fast the metastable uncertainty resolves itself. <P>For Xilinx FPGAs click on<U></U> <P><U><A HREF="http://www.xilinx.com/xapp/xapp094.pdf">http://www.xilinx.com/xapp/xapp094.pdf</A></U> <P>Peter Alfke, Xilinx Applications </BODY> </HTML> --------------FFE655841CCD2659E17A4FDF--Article: 16243
Formal Solutions for Static Verification: An ASIC and IC Design
Verification
Seminar
Register at http://www.chrysalis.com/seminars.html
Verification is the critical path for complex ASICs and ICs. Formal
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solution.
This seminar will cover:
Static Verification Methodology
What it is and how it is evolving
Formal Design Rule Checks
How they automate functional verification of logic design
rules
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How it addresses block-level functional verification to reduce
simulation costs
Formal Equivalence Checking
How it replaces gate-level simulation to ensure accurate
implementation from synthesis and schematics to tapeout.
Chrysalis Technology
How it integrates formal tools to support static functional
verification
Dates and Locations:
Tuesday, May 18th at the Westin Hotel
Santa Clara, CA
Wensday, May 19th at the Best Western Gateway Hotel
Rockville, MD
Tuesday, May 25th at the Radisson Heritage Hotel
Chelmsford, MA
Thursday, June 3rd at the Radisson Governors Inn
Research Triangle Park, NC
Times:
8:30 AM
Continental Breakfest
9:00 AM
Welcome
9:15 AM
Formal Solutions for Static Verification
11:00 AM
Demonstration of Formal Solutions
Register at http://www.chrysalis.com/seminars.html
or call 978/436-9909.
--
-------------------------------------------------------
Tom Jackson
Director of Corporate Marketing
Chrysalis Symbolic Design, Inc.
101 Billerica Avenue, Bldg. 5
N. Billerica, Massachusetts 01862
ph: 978.436.9909
fax: 978.436.9697
email: tjackson@chrysalis.com
Article: 16244I am looking for a simple UART design (without all of the handshaking features) in verilog for use in a Xilinx XCS20 device. Does anybody know where I could download a free design?Article: 16245
Dan Oomkes wrote: > I am looking for a simple UART design (without all of the handshaking > features) in verilog for use in a Xilinx XCS20 device. Does anybody > know where I could download a free design? look at http://www.memecdesign.com/cdrom.htm they have a 8250 macro plus 4 or 5 other pieces of IP for $99.00 US -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 16246
Bob Sugar wrote: > Sure, if you take a 10-year old design and run > it at the 10-year old clock rate on a state-of-the-art process, you'll > [almost] never need to worry about metastability but with today's > 0.25um processes at 200+ MHz, 5ns isn't much time for metastability > to resolve. > > For Xilinx, do you know if the metastability constants have surpassed > the peak operating speeds in the last few generations? I think the answer is yes, and the reason is that - same as in ASICs - overall performance is more and more determind by interconnect delays ( which do not contribute to metastability problems), and the flip-flop performance has improved faster than the system performance.We will have new sets of metastability numbers in a few weeks, and I will post them here. Luckily, most asynchronous interfaces do not run at a 200 MHz clock rate. Whenever they do, watch out! Asynchronous interfaces are often between slower peripherals running at inherently more modest rates, where metastability has become less of an issue. > > > Bob Sugar > SiTera Inc. > > P.S. Peter, are you the app's engineer who wrote the awesome video > capture app. note for MMI many years ago? No, I spent ten years at AMD, but was never at MMI. Peter Alfke, Xilinx ApplicationsArticle: 16247
Peter Alfke wrote: > I can only speak for Xilinx: > > Because hardly anybody asks for the data. count me as one who asks for the data and has tested some stuff on his own. all manufacturers should publish this stuff ... some used to but have stopped. and, in my itty bitty opinion, it should be in the data sheet, not an application note (although the app notes you published are appreciated, i just feel that specifications and behavior of the device should be in the data sheet, recommendations on how to use the device should be in the application notes). so, i guess i'm a nobody. --------------------------- > I published a fairly detailed explanation of metastability, test methodology, > and results in the 1989 Xilinx data book, and repeated and improved it in all > the seven or eight subsequent editions, ( look in the index!) but I have sensed > very little interest. > We are about to start a new series of tests, and I will publish the results > again. > Nice to hear that somebody is interested. yeah, interested. and perhaps those that aren't should be. <rk goes back to his keyboard, wondering why he has a job that requires a lot of writing when he can't write at all> :-)Article: 16248
asap wrote:
>
> Hi all,
>
> I'm trying to do a post-synthesis
> simulation with Modelsim EE 5.2,
> using the VITAL lib of my ASIC vendor.
> I keep getting errors that some instances
> do not have one or two generics (e.g.: tpd_c_q_posedge).
> (I do not have errors of missing instances...)
> I don't think there is any error on the top instance
> I apply the sdf file, nor similar things...
> However, I don't know if i produce wrongly the sdf/vhdl files
> from Synopsys DC v1999.05 (I use the SDF v2.1 format).
> Is there any chance that the vendor ASIC VITAL models
> are not 100% VITAL compatible, as mentioned on the
> Modelsim user manual?
>
> Thanks,
I confronted similar problem.
I used Synopsys's DesignPower to estimate of power of the chip.
When I compiled the VITAL intenal memory libary of STM by VSS, such as lines
made errors.
==> VITAL Entity 'FIFO_94X16' has VITAL conformance error(s):
TPD_OE_Q : VitalDealyArrayType01z(7 downto 0) := (others =>
^
**Error: vhdlan,2148 FIFO_94x16_ent.vhd(20):
The type of a scalar timing generic parameter 'TPD_OE_Q' does not match
the
type of the associated ports.
......
Other man who compiled by Leapfrog said he didn't have such error.
I could escape the error by changing the name TPD_CK_Q => aTPD_CK_Q.
I don't kwow why such error, but after changing it compiled well.
Maybe the name was a reserved word of VSS?
So, in my opinion, you may avoid error by changing names...
Is there a person who knows the reason of my case? please let me know!!!
-- ***************************************
-- Kyungjin Jang
-- DIT 2R, Daewoo Electronics CO., LTD.
-- ***************************************
Article: 16249Peter Alfke schrieb: > Roland Fröhlich wrote: > > > With PLDs I have builded years ago the following good working design: > > > > Connect the input signal to a transparent latch with Latch-Enable= CLOCK. > > > > When the CLOCK is high, the output follows immediatly the input signal. > > After CLOCK is going low, the output of the latch is freezed and can not > > change more, so the setup-time of the subsequent D-type register can be > > satisfied. > > If you design the transparent latch with gates, switch off the optimizer, > > because > > it is essential to use all redundant terms in the feedback path to avoid > > glitches. > > This device does not exhibit metastability behavior at the expense of > > loss of > > maximal one takt cycle latency, and the input signal must be valid for > > longer as > > one takt cycle for secure detection. > > > > Sorry Roland, but you are wrong. > > A latch is equally as vulnerable to metastable delays as a flip-flop. Actually, > it is the master latch in the flip-flop that goes metastable. > When the data input changes right at the moment when you stop the latch from > being transparent, you get the same unpredictable metastable delay as you get in > a flip-flop. > > There is no way ( NO WAY ! ) to avoid metastability, but modern circuits resolve > it so fast that metastability is no longer the same scary subject it was ten > years ago. > > Peter Alfke, Xilinx Applications Peter, you are right with this statement. I remember the problem I have solved with the mentioned design was not metastability but setup-time violation. This is very serious if the sampled input signal is parallel feeded to different synchronous blocks and the underlying logic concept assumes these signals to be equal, but the actual hardware sees this not. This inconsistency let the design work completly wrong and useless. Roland Froehlich.
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