Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I subscribe to "Embedded Systems" and read this article before I saw this thread. Normally, I don't finish magazine articles but this article was exceptional! This was the kind of introduction I was thinking about on programmable logic. Now, all that's needed is some examples & schematics, including the procedures for programming the chips. Michael's article was a credit to our profession. I recommend everyone read this and pass it along to their peers. Gary ----- Michael Barr <mbarr@netrino.com> wrote in message news:3757EE96.6CB79AF2@netrino.com... > I agree with all of these recommendations. With respect to simpler > issues like "the difference between a CPLD and an FPGA" and a brief > overview of typical applications, take a look at this article from > the latest issue of Embedded Systems Programming. > > http://www.netrino.com/Articles/ProgrammableLogic/ > > It's written primarily for the software engineer who's new to FPGAs > in general. So it doesn't get into more detailed topics. But it > might be worth a look and/or a link before you write your own stuff. > > Cheers, > Michael BarrArticle: 16751
Thierry Garrel wrote: > > Hi all > > Why buy a Memec 8250 core ? > > Look at ftp://ftp.xilinx.com/pub/applications/misc, you'll find a file > named rs-232.zip. > This is an old app note from Xilinx which describes a 8250 core designed > in schematics. > The schematics are included in Viewlogic format. The app note in > postcript format is also > included in the zip file. We have implemented it in a lot of design with > success, > at speed up to 155k bauds. ...snip... > ------------------------------------------------------------------------------ > Thierry GARREL - tga@magic.fr > > +----------------------------------------------+ > | MATRA Défense Equipements et Systèmes (MDES) | > | 6 avenue des tropiques - BP 80 | > | 91943 COURTABOEUF CEDEX / FRANCE | > | Tel : (33) 1 69 86 85 00 | > | Fax : (33) 1 68 07 03 70 | > | Mail : ceo@matra-des.mgn.fr | > +----------------------------------------------+ I am very interested in this design. Have you used it in a system where it had to work with existing drivers written for a standard 8250 UART? My intention is to use the interface to the bus, but to not serialize the data. Instead I will modify the design to provide another parallel interface for a DSP processor. The intention is to link a DSP chip to a machine running any standard operating system without the need for special drivers. Have you used this design with standard drivers from any of the established operating systems? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16752
Lasse Langwadt Christensen wrote: > I don't know if you can change priority from the command line, but > you can start a task with priority like this: > > start /priority program.exe > > where priority is: low, high, idle etc. > and program.exe what ever program you want to start Hi Lasse, This is close but not quite right. Using start as you show above spawns a new MS-DOS shell which runs the program and returns. I'm running par as part of a makefile so this solution doesn't quite work. What does work is: start /low /wait program It still spawns another MS-DOS window but now waits until program finishes before continuing with the makefile. I'm reasonably happy with this soluion. Thanks, Erik -- ------------------------------- Erik de Castro Lopo Fairlight ESP Pty Ltd e.de.castro AT fairlightesp.com.auArticle: 16753
In article <7j578h$7m4$1@nnrp1.deja.com>, Swapnajit Mittra <mittra@my-deja.com> wrote: > In article <7j0hrd$3jl$1@nnrp1.deja.com>, > andi_carmon@my-deja.com wrote: > > > Swapnajit, > > > > I finally got the book above. Congratulations. > > The section about inter-process communications was very helpful. > > Regarding this issue, I need an advice on the following : > > The 'accept' call of the server is blocking by default. It will not > > return until a connection is available. I know that it is possible to > > define the socket as non-blocking. Can you advise me how? Actually I > > want to achieve the effect of the server 'visiting' the socket and if > > there is no connection of the client to let it continue. > > Thank you, > > Andi Carmon > > andi@orckit.com > > > Andi, > > I am glad that the example in the book > has encouraged you to do further research > on the topic; after all, that is one of the > main objective of the book. > > Regarding your question, you can create a > non-blocking socket (by default, all sockets > are blocking) by using fcntl() system call. > An example of this is : > > fcntl(s, F_SETFL, FNONBLK); > > where s is the socket created by socket(). > The names of the integer constants may be > slightly different depending on your version of > UNIX. For example, when FNONBLK is POSIX > compliant, IRIX uses a native FNONBLOCK. > > Also, there are other ways to do the same. Some > flavors of UNIX (and BeOS) does this using > setsockopt(), but it is not implemented > in all OS'. > > Thanks, > - Swapnajit Mittra > -- > =-=-=-=-=-= 100% pure Verilog PLI - go, get it ! =-=-=-=-=-= > Principles of Verilog PLI -By- Swapnajit Mittra > Kluwer Academic Publishers. ISBN: 0-7923-8477-6 > http://www.angelfire.com/ca/verilog/ > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. > Swapnajit, Thank you for the tip. I think I need only one small additional push. I defined the server socket as non-blocking (but not the client). The accept() call is now part of the read_server routine and to check for availability of new data from client I use poll() as Bob Beckwith also suggested. The problem is that the ping-pong works only once! It seems that I need some means to "re-arm" the mechanism. The sequence I get is as follows: (As I mentioned the server is triggered in verilog and checks for availability of new data from client). client_write; client_read (now waits for server_write). Later, the server check and successfully detects the pending data. server_write; client successfully detects server_write and performs again client_write; client_read (now waits for server_write). Now, here is hangs up. The server, triggered later again, checks but does not detect any more pending data. Can you see what the problem is ? Thank you again, and if you attend DAC I would like to thank you personally. Andi Carmon Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16754
Erik de Castro Lopo wrote: > > Lasse Langwadt Christensen wrote: > > I don't know if you can change priority from the command line, but > > you can start a task with priority like this: > > > > start /priority program.exe > > > > where priority is: low, high, idle etc. > > and program.exe what ever program you want to start > > Hi Lasse, > > This is close but not quite right. Using start as you show above > spawns a new MS-DOS shell which runs the program and returns. I'm > running par as part of a makefile so this solution doesn't quite > work. > > What does work is: > > start /low /wait program > > It still spawns another MS-DOS window but now waits until program > finishes before continuing with the makefile. > > I'm reasonably happy with this soluion. > > Thanks, > Erik I've found a way of doing it, download http://spot.fho-emden.de/ftp/NT/unix95_7.zip (you can probably get it several differetn places) just extract it and you've got all the nice :) command prompt unix stuff missing in NT such as nice,ps, kill .. --L2C --___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_---- Lasse Langwadt Christensen, MSEE (to be, june 30th 1999) Aalborg University, Department of communication tech. Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.orgArticle: 16755
***WaveFormer Pro & TestBencher Pro V6.0 Released*** Version 6.0 of the popular timing diagram analysis and HDL test bench development tools, WaveFormer Pro & TestBencher Pro from SynaptiCAD Inc., are now available. The release of the new version coincides with the appointment of EuroEDA Limited as UK distributor for SynaptiCAD's full product range consisting of TimingDiagrammer Pro, WaveFormer Pro, TestBencher Pro & VeriLogger Pro. Brief product details can be found on the EuroEDA web site at http://www.euro-eda.com, from where additional information and evaluation copies of the software may be requested. -- EuroEDA Limited Phone: +44 (0)1933 676373 Fax: +44 (0)1933 676372 Email: info@euro-eda.com Web: http://www.euro-eda.comArticle: 16756
What Xilinx device are you wanting to use. If its an XC9500 CPLD then try
the Xilinx 'Web-Fitter'
at www.xilinx.com - this will take an Altera .tdf file.
Regards, Neil Carrington
Vitolo wrote in message <7j0s18$h9b29@SGI3651ef0>...
>Hi, all:
>
>I need convert a ALTERA design(MAX+PLUSII) into a XILINX design (Foundation
>F1.3). I try export a Edif 200 file from MAX+PLUS and import netlist into
>Schematic Editor of Foundation. I complet the design with the new
component
>(IBUF, OBUF, pads) and save. When i try export the netlist in a XNF file,
>ihave a error message ("Missing AND1 model or library error") then i export
>in a VHD file and have ("Cannot read pin descriptors for AND1") error.
>
>I want to generate a VHDL file (XILINX Foundation compatible) from a EDIF
>,or other, ALTERA file. How i can to do?
>
>
>
Article: 16757Altera came out with an EEPROM device that is pin-compatible with EPC1. It is called EPC2 and can be in-circuit programmed through JTAG (a lot faster than Data I/O with EPC1). You might (didn't check thoroughly) not have to modify your board if you don't want the in-circuit programmability feature, and may consider making a board with a PLCC socket and a 5x2 straight-pin header to program the EPC2 and place them on your board instead of EPC1. Again, I'm not sure about this, but it might be worth the time to check it out. Just my $.02. Victor Carlhermann Schlehaus wrote: > > Hi, > > just kidding, we have switched to the EPF6K and so we had the need to > programm an EPC1. We decided to buy an Optima Light, manufactured by SMS > (now a part of the Data I/O universe). > First of all, I had some telephone call with SMS support to ensure the > programmer could be used with a notebook running with WIN NT. Okay, this > should work, so we bought the programmer. > > When the device arrived, the documentation told me, that the NT software > would be in 'BETA' and that either the programmer driver or the printer > driver could be installed (ridiculous, every time you'd like to programm an > EPC1, you have to deinstall your printer)... > > Okay, called the support, got a link to the SMS ftp-Server to download a > newer version. This version could co-exist with the printer drivers. But the > programming times are incredible. > We need about 5 min to programm a EPC1. The *.pof is very quick read, but > then the blank check lasts just as long as the programming cycle and then > the verification, it's a horror. Series production is not possible with 10 > devices / hour :-( > > On the other hand I tried to program a normal 256KB (PLCC32 device). The > result is that every time I start the programming I could reset my PC as the > software causes NT (!) to crash completely ... > > Cu,CSArticle: 16758
Jan Vermaete wrote: > Hello, > > Where can I find a symbol (Xilinx FPGA XC4013E) in Viewlogic? > I use Powerview 6.1 but we have also the workview office CD's (for > windows NT) > > Many thanks Now I can anser my question. On the second CDROM of Powerview Office (version 7.5) there is a directory <cdrom>/vendor/lmg . When you install this directory and make the searchpath correct you will find a lot of common FPGAs. get. JanArticle: 16759
Hmm, That doesn't agree with my experience. If you look at the EDIF output from the coregen you will see the INIT= attributes in the EDIF file, assuming that you provided a .COE file as input to the coregen. To see this, run the COREGEN on an example RAM using a .coe file, then open the edif output file with a text editor such as wordpad, and do a search on "INIT". Hobson Frater wrote: > Tom and Ray, > > The EDIF file coming out of Coregen just contains the design itself (no initial > values or the initial values are set to zero). That's why the COE file exists. > When you run through NGDBUILD (Translate), all of your EDIF files get merged > together. NGDBUILD also pulls in other files like the COE file. There is no need > to specify this file in a UCF or NCF file. It gets pulled in if it's present in > the design directory. After NGDBUILD, you have an NGD file, so run NGD2EDIF, > NGD2VHDL, or NGD2VER to get the appropriate structural netlist that you need for > functional simulation. This netlist should have all of the initial values for > your memories b/c all of your input design files have been merged. Hope this > helps... > > Regards, > Hobson Frater > Xilinx Applications > > Tom McLaughlin wrote: > > > Ray, > > Thanks for the help. I did find the INIT property in the edif file, but they > > were all set to zero! I have a .coe file with initial values and Coregen > > generated the .mif file for simulation with the correct initial values, but > > they are not in the edif file generated at the same time. Any suggestions??? > > By the way, I am generating a single port RAM for Virtex using Coregen v1.5.2. > > Any help would be appreciated. > > > > Regards, > > Tom > > > > Ray Andraka wrote: > > > > > The initial values do indeed get passed through the edif file using the INIT > > > property. If the initial values are all zero for a particular LUT, then the > > > INIT property is not placed on that LUT. If it is missing, then the default > > > of all zeros is used. You can see the initial values if you generate a RAM > > > component using a COE initial values file. After generating it, go into the > > > edif file with a text editor and do a search on the string "INIT". You will > > > find lines similar to " (property INIT (string "0f03c0f0"))" which > > > correspond to the initial values in the COE file. > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16760
Exemplar Leonardo, a synthesis tool.
Wenwei Qiao wrote in message ...
>What and where is Leonardo?
>
>David Hawke <dhawke@globalnet.co.uk> wrote in message
>news:7j703e$aga$1@gxsn.com...
>> You could always use Leonardo to read in the Altera EDIF and then
retarget
>> towards Xilinx.
>> I use this quite a lot when I need a quick (but slightly dirty
conversion)
>>
>> Regards,
>>
>> David Hawke.
>> Xilinx.
>>
>> Bill Gates wrote in message <7j69in$9nf$1@tourist.gnt.net>...
>> >Unfortunately the EDIF that Max+plus gave you uses parts available for
>the
>> >particular
>> >chip family that was selected by the Max tools and the Xilinx part you
>want
>> >to use
>> >does not have the same parts (i.e. AND1 for instance). If you get this
>to
>> >actually work
>> >I would be amazed.
>> >
>> >If you have the original VHDL code (that is if you didnt use Max's AHDL
>or
>> >some
>> >schematic entry) then I would use that instead by either compiling it in
>> >Xilinx or some
>> >"better" tool like leonardo or synplicity.
>> >
>> >Good luck... maybe someone else has a suggestion as to how to edit the
>edif
>> >file
>> >or something to that nature.
>> >
>> >
>> >Vitolo <setel@mx3.redestb.es> wrote in message
>> >news:7j0s18$h9b29@SGI3651ef0...
>> >> Hi, all:
>> >>
>> >> I need convert a ALTERA design(MAX+PLUSII) into a XILINX design
>> >(Foundation
>> >> F1.3). I try export a Edif 200 file from MAX+PLUS and import netlist
>into
>> >> Schematic Editor of Foundation. I complet the design with the new
>> >component
>> >> (IBUF, OBUF, pads) and save. When i try export the netlist in a XNF
>file,
>> >> ihave a error message ("Missing AND1 model or library error") then i
>> >export
>> >> in a VHD file and have ("Cannot read pin descriptors for AND1") error.
>> >>
>> >> I want to generate a VHDL file (XILINX Foundation compatible) from a
>EDIF
>> >> ,or other, ALTERA file. How i can to do?
>> >>
>> >>
>> >>
>> >
>> >
>>
>>
>
>
Article: 16761Does anyone know of any free or reasonably cheap tools that can be used specifically for generating timing diagrams for documentation etc. It doesn't need to support any database of parts with timing etc. just a good drafting tool that understands electronic signal diagrams. Something speedier and faster than using Visio or PowerPoint etc. Thanks.Article: 16762
--------------34545814E50554023DBAC238
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Hi,
i am trying implement a design for the XCS30XL-FPGA (Xilinx Spartan
series). The FPGA will be connected to the system-bus between the
microcontroller and the sdram-modul.
|--------|
| |
| FPGA |
|--------|
| | |
| | |
|----|_______________|_|_|_______|-------|
| MC |_________________|_|_______| SDRAM |
| |___________________|_______| |
|----| / |-------|
/
Bus
The FPGA should translate the bus-signals for the sdram in a more simple
form.
I am only interested in the read and write accesses.
The datas and the whole address should be at the same time on the
outputs.
(The outputs are similar the signals for a sram.)
--------
| |
CLK_IN - - CLK_OUT
| |
BA[1:0] - - Addr_out[21:0]
| |
Addr_in[11:0] - - Addr_out_valid
| |
CS - - read/write
| |
RAS - - Data_out[31:0]
| |
CAS - - Data_out_valid
| |
WE - |
| |
Data_in[31:0] - |
| |
--------
A single write-access is not the problem. The things become more
difficult with a read-access because the cas-latency of two clocks or
burst-access (burst-length=4).
Perhaps can anybody give me some hints what is the best way to solve
this problem?
Thanks
Frank
--------------34545814E50554023DBAC238
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<font face="Courier New,Courier"><font size=-1>Hi,</font></font><font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>i am trying implement
a design for the XCS30XL-FPGA (Xilinx Spartan series). The FPGA will be
connected to the system-bus between the microcontroller and the sdram-modul.</font></font><font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>
|--------|</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| FPGA |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
|--------|</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| | |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| | |</font></font>
<br><font face="Courier New,Courier"><font size=-1>|----|_______________|_|_|_______|-------|</font></font>
<br><font face="Courier New,Courier"><font size=-1>| MC |_________________|_|_______|
SDRAM |</font></font>
<br><font face="Courier New,Courier"><font size=-1>|
|___________________|_______| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>|----|
/
|-------|</font></font>
<br><font face="Courier New,Courier"><font size=-1>
/</font></font>
<br><font face="Courier New,Courier"><font size=-1>
Bus</font></font><font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>The FPGA should translate
the bus-signals for the sdram in a more simple form.</font></font>
<br><font face="Courier New,Courier"><font size=-1>I am only interested
in the read and write accesses.</font></font>
<br><font face="Courier New,Courier"><font size=-1>The datas and the whole
address should be at the same time on the outputs.</font></font>
<br><font face="Courier New,Courier"><font size=-1>(The outputs are similar
the signals for a sram.)</font></font>
<br><font face="Courier New,Courier"><font size=-1></font></font> <font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>
--------</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
CLK_IN -
- CLK_OUT</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
BA[1:0] -
- Addr_out[21:0]</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
Addr_in[11:0] - -
Addr_out_valid</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
CS
- - read/write</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
RAS
- - Data_out[31:0]</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
CAS
- - Data_out_valid</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
WE
- |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
Data_in[31:0] - |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
| |</font></font>
<br><font face="Courier New,Courier"><font size=-1>
--------</font></font><font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>A single write-access
is not the problem. The things become more difficult with a read-access
because the cas-latency of two clocks or burst-access (burst-length=4).</font></font><font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>Perhaps can anybody give
me some hints what is the best way to solve this problem?</font></font><font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>Thanks</font></font>
<br><font face="Courier New,Courier"><font size=-1>Frank</font></font></html>
--------------34545814E50554023DBAC238--
Article: 16763Hi, Victor Snesarev (EXCHANGE:BNRTP:3H18) <hw4@americasm01.nt.com> schrieb in im Newsbeitrag: 375BCF0A.4DDBF86B@americasm01.nt.com... > Altera came out with an EEPROM device that is pin-compatible with EPC1. > It is called EPC2 and can be in-circuit programmed through JTAG (a lot > faster than Data I/O with EPC1). That's right, but when I asked my local distributor, I got a horrendous price. It was nearly five times higher than the EPC1 :-( That was the knockout criteria to use this device. How much does this devices costs in america ? CU, CS > You might (didn't check thoroughly) not have to modify your board if you > don't want the in-circuit programmability feature, and may consider > making a board with a PLCC socket and a 5x2 straight-pin header to > program the EPC2 and place them on your board instead of EPC1. Again, > I'm not sure about this, but it might be worth the time to check it out. Well AFAIK it is possible to programm the EPC2 with the BitBlaster from ALTERA In Circuit, but the Device shouldn't costs that much to use it not even in prototypes... >Article: 16764
Ha Young Youl wrote: > I prepare a communication chip design project. > the communication chip functions SDLC, Bus interfacing, queuing. > I anticipate it will need about 40,000 ~ 50,000 gate. > FPGA design will be preceded. > > but final product should be low cost. > I am thinking Custum IC is one of them > > What can I do in order to convert FPGA design to Custum IC design I looked at an FPGA to ASIC approach several years ago. At the time, one vendor, United Technologies Microelectronics said they had software which would convert a Xilinx 4K FPGA design to their process, which we chose because it was radiation hardened. They might be able to help with your (presumably commercial) application - try calling Bob Bauer at U.S. telephone number (719) 594-8379 (this is in the state of Colorado). Jonathan -- Jonathan F. Feifarek Consulting and design Programmable logic solutionsArticle: 16765
I have a 10K20 design compiled into a 144-pin TQFP package at about 60% device utilization. Part of this design is a 16-bit data bus onto my PC board which is running at 7.5MHz (no big deal, chip register index is 40MHz). The problem I'm experiencing is when any output of the bus is driving logic high, it is influenced by neighboring data lines allowing 1.5V switching for that entire signal level. When the output drives low, there is no switching noise or other influence. It behaves like a week open collector. If a termination resistor (pull-up or pull-down) is applied, (anywhere from 200 ohms to 50K) the output is stable. I have checked the PC board for trace resistance and shorts (the trace lengths are about 6 inches). Also tried several configurations with the output assignments, and the only one that didn't give me this problem is when configured as open drain (shouldn't have to do this). It's as if the outputs are unable to drive logic high without a load. I have used this device in the 240-pin RQFP package with an earlier version of Max+Plus and no problems like this. Anyone experience any similar problems with this device? John Heslip john_heslip@avionics.bfg.comArticle: 16766
> On Fri, 4 Jun 1999, Ha Young Youl wrote: > > > Hello. > > > > I prepare a communication chip design project. > > the communication chip functions SDLC, Bus interfacing, queuing. > > I anticipate it will need about 40,000 ~ 50,000 gate. > > FPGA design will be preceded. > > > > but final product should be low cost. > > I am thinking Custum IC is one of them > > > > What can I do in order to convert FPGA design to Custum IC design > > What do I need .. > > or is there another method to be low cost > > > > help me! > > Xilinx has a progrram called the Hardwire program http://www.xilinx.com/products/hardwire/hardwirehome.htm what is great about this program is that they just need your bit file that configures your part and from that they make a low cost ASIC. -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 16767
Frank Papendorf wrote: > > Hi, > > i am trying implement a design for the XCS30XL-FPGA (Xilinx Spartan > series). The FPGA will be connected to the system-bus between the > microcontroller and the sdram-modul. > > |--------| > | | > | FPGA | > |--------| > | | | > | | | > |----|_______________|_|_|_______|-------| > | MC |_________________|_|_______| SDRAM | > | |___________________|_______| | > |----| / |-------| > / > Bus > > The FPGA should translate the bus-signals for the sdram in a more > simple form. > I am only interested in the read and write accesses. > The datas and the whole address should be at the same time on the > outputs. > (The outputs are similar the signals for a sram.) > > > -------- > | | > CLK_IN - - CLK_OUT > | | > BA[1:0] - - Addr_out[21:0] > | | > Addr_in[11:0] - - Addr_out_valid > | | > CS - - read/write > | | > RAS - - Data_out[31:0] > | | > CAS - - Data_out_valid > | | > WE - | > | | > Data_in[31:0] - | > | | > -------- > > A single write-access is not the problem. The things become more > difficult with a read-access because the cas-latency of two clocks or > burst-access (burst-length=4). This is not so hard if you are trying to interface an SRAM or something similar to make it appear to be an SDRAM. You do need to "decode" the CS, RAS, CAS and WE to only respond to the READ and WRITE commands. You load the Bank and Row address into the upper bits of a register on Active command. Load the Column address into the lower bits of the register on Read or Write commands. On a Write command you also latch the data. This address and data are presented to the other interface. I can't tell you how to generate the control signals out to the other device since I don't know what that device is. A simple state machine will help you produce a data on a Read which is delayed by the CAS latency. With a burst length of 4, the low two bits of the address will increment on every clock. If the burst was not started at an address that is a multiple of 4, the two bit counter should not carry into the next bit, but should wrap around. Of course you also need to handle a burst being terminated by a Precharge, Burst Terminate, Read or Write command. Basically, you will need to read an SDRAM data sheet in enough detail that you can emulate the interface and command responses while driving a compatible set of signals to the other interface. This will be a little tricky on writes since you will have to perform a write on each clock cycle. It can be very hard to generate a write strobe unless you have a 2x clock. I know this from experience. Good luck. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16768
Hi. I have a question about the weak pull-up resistors in 3.3V Spartan XL parts. The datasheet only specifies one point on the V-I characteristic, 20 to 250uA at Vin = 0V. 1. I'm interested in knowing whether they pull-up all the way to VCC. 2. I'm also interested in knowing what happens to the V-I characteristic when the voltage gets above VCC. Does the current drop to (near) zero? Or is there some significant leakage current? The datasheet says that the pull-ups are p-channel fets. It also says that they are 5V tolerant. XAPP 088 shows that something has been done to bias the fet well (to avoid the problems due to the parasitic diode in the fet) but it doesn't give any details of the well bias circuit. Could someone help me please? Thanks, Allan.Article: 16769
Call for Participation
THE FIRST NASA/DoD WORKSHOP ON EVOLVABLE HARDWARE
July 19 - 21, 1999
Jet Propulsion Laboratory
California Institute of Technology
Pasadena, California, USA
NEW: Those wishing to attend please consult the workshop website
(http://cism.jpl.nasa.gov/events/nasa_eh) to register online.
Payment can be made at the door or anytime before the workshop, but
please use the website to register as early in advance as possible.
NEW: The conference program is now available on the workshop website.
THE FIRST NASA/DoD WORKSHOP ON EVOLVABLE HARDWARE
Sponsored by:
National Aeronautics and Space Administration (NASA)
Defense Advanced Research Projects Agency (DARPA)
Ballistic Missile Defense Organization (BMDO)
Hosted by:
Center for Integrated Space Microsystems (CISM), JPL
Center for Space Microelectronics Technology (CSMT), JPL
NASA Technology Program (NTP), JPL
The First NASA/DoD Workshop on Evolvable Hardware (EH'99) will be held at
the Jet Propulsion Laboratory in Pasadena, California. The purpose of this
workshop is to bring together leading researchers from the evolvable
hardware community, representatives of the programmable/reconfigurable
hardware community, technology developers, and end-users from the aerospace
community.
The emerging field of Evolvable Hardware is expected to have major impact
on deployable systems for space missions and defense applications that need
to survive and perform at optimal functionality during long duration in
unknown, harsh and/or changing environments. Examples of such applications
include outer solar system exploration, missions to comets and planets with
severe environmental conditions, long lasting space-borne surveillance
platforms, defensive counter-measures, long-term nuclear waste and other
hazardous environment monitoring and control. Evolvable hardware is also
expected to greatly enrich the area of commercial applications in which
adaptive information processing is needed; such applications range from
human-oriented hardware interfaces and internet adaptive hardware to
automotive applications.
The purpose of the workshop is to provide a forum for discussion on the
potential role of evolvable hardware in real-world applications, in
particular those related to space. The Workshop attendees will have the
opportunity to discuss the fundamental issues and state-of-the art of
evolvable hardware technology, plans for development of future devices and
hardware systems suitable for evolution, and needs related to space
applications. The outcome of this meeting is expected to be a technology
development roadmap that would lead to deployable evolvable hardware.
Honorary Chair: John R. Koza, Stanford University
Chair: Adrian Stoica, Jet Propulsion Laboratory
Co-Chairs: Didier Keymeulen, Jet Propulsion Laboratory
Electrotechnical Laboratory
Jason Lohn, NASA Ames Research Center
Program Committee:
Leon Alkalai, Jet Propulsion Laboratory (USA)
Forrest H. Bennett III, Genetic Programming, Inc. (USA)
Gregory Cain, Victoria University (Australia)
Silvano P. Colombano, NASA Ames Research Center (USA)
Hugo de Garis, Advanced Telecommunication Research Lab (Japan)
Stuart J. Flockton, University of London (UK)
Terry Fogarty, Napier University (UK)
David B. Fogel, Natural Selection, Inc. (USA)
Inman Harvey, University of Sussex (UK)
Hitoshi Hemmi, NTT Communication Science Labs (Japan)
Tetsuya Higuchi, Electrotechnical Laboratory (Japan)
Lorenz Huelsbergen, Bell Labs, Lucent Technologies (USA)
Alan Hunsberger, National Security Agency (USA)
Rich Katz, NASA Goddard Space Fligth Center (USA)
Daniel Mange, Swiss Federal Institute of Technology (Switzerland)
Pierre Marchal, Centre Suisse d'Electronique et de Microtechnique SA
(Switzerland)
Julian Miller, Napier University (UK)
Eric Mjolsness, Jet Propulsion Laboratory (USA)
Jose Munoz, Defense Advanced Research Projects Agency (USA)
Masahiro Murakawa, University of Tokyo (Japan)
Edward Rietman, Bell Labs, Lucent Technologies (USA)
Justinian Rosca, Siemens Corporate Research (USA)
Mehrdad Salami, Victoria University (Australia)
Eduardo Sanchez, Swiss Federal Institute of Technology (Switzerland)
Moshe Sipper, Swiss Federal Institute of Technology (Switzerland)
Stephen Smith, Altera (USA),
Stephen Trimberger, Xilinx (USA)
Adrian Thompson, University of Sussex (UK)
Anil Thakoor, Jet Propulsion Laboratory (USA)
Benny Toomarian, Jet Propulsion Laboratory (USA)
R. S. Zebulum, University of Sussex (UK)
For further information please check the workshop web site or contact:
Adrian Stoica
Jet Propulsion Laboratory, MS 303-300
4800 Oak Grove Drive
Pasadena, CA 91109, USA
adrian.stoica@jpl.nasa.gov
Tel: +1 (818) 354-2190
Fax: +1 (818) 393-1545
Web: http://cism.jpl.nasa.gov/events/nasa_eh
Article: 16770Does any one out there have any info on the likely configuration and performance of the LVDS IO planned for the Altera 20KE. I have had a look at the 20K data sheet but it contains very little info. What I would like to know is: 1) the number of LVDS inputs that will be offered. (I am interested in 8-16;) 2) the maximum operating frequency/data rate; (I am interested in 500+ MHz operation;) 3) what sort of demux will be offered on chip to reduce the data rate to acceptable FPGA rates, (i.e. approx. 100 MHz.). My interest stems from attempting to hook high speed ADCs to FPGAs rather than a line communications application! Regards SteveArticle: 16771
On topic Flame Bait thread initiator:
In article <928349344.434604@BITS.bris.ac.uk> tt@cryogen.com writes:
>
>When Xilinx sais they were going to fold the family, they didn't have
>any real reconfigurable alternative and pledged that they would continue
>to manufacture the chip and make samples of it available to academics
>and researchers for as long as there was demand for it. Now that Xilinx
>presumably want to channel people towards their Virtex part, which appears
>to have at least some of the functionality of the 6200 series, I don't
>know what their position is any more. By all accounts the 6200 was
>a pretty weird beast, and was without some of the software support it
>really needed.
The 6200 offered some interesting capabilities, in particular, being
mostly able to be configured with random data without contention (not the
I/O), register type access, partial reconfiguration at a very fine grain
level, and total exposure of the config stream format (not an architectural
feature, a marketting decission).
On the other hand, it suffered in its own way from the same problems of
all the fine grain architectures (anything from Pilkington (Plessy,
Toshiba, Motorola), Concurrent/CLay/Atmel/IBM, Crosspoint Solutions)
which is that they end up burning significant amount of the available
interconnect just building up basic macro functions, like an add with
carry, or a 4 to 1 mux, or even something real basic like an 8 input AND
gate.
If you look at the short history of (re)configurable computing (the
procedings of the FCCM conferences would be a good start), you will find
that almost ALL of the significant papers that present RESULTS that show
a speed up over traditional computers, or even over purpose built ASICs,
have used traditional FPGAs like the XC3000 and XC4000 (and derivatives).
As I wrote about 6 years ago, one of the biggest advantages of FPGA based
computing surfaces versus ASICs (assumes you understand how these both can
out perform traditional CPUs in selected applications) is that you can
explore the algorithm space. You can try multiple algorithms, run them at
millions of cycles a second, detect bottlenecks/pathological problems,
fix it and try again. This may be impossible with simulation due to the
amount of computing needed to get to the problem points. With ASICs, you
only get one shot at it. None of this has anything to do with fine grain
architecture. And except for evolutionary approaches to HW design, config
without contention is (or should be) irrelevant. The other thing that you
will note is that the success stories did not depend on rapid
reconfiguration.
Fine grain is the wrong direction.
Random bitstream tolerance is only needed for what is currently a very
small part of the possible research areas, and I contend that this is
not even needed with appropriate care in how evolutionary HW permutes the
bitstream.
Rapid reconfiguration is not even worthy of attention yet. What's needed
is robust ways to get one configuration right, preferably for people who
don't/won't want to learn about the internals of an FPGA.
This type of stuff:
Linpack.ftn -> {magic} -> FPGA configuration stream
DhryStone.c -> {magic} -> FPGA configuration stream
Word97.bas -> {MAGIC} -> FPGA configuration stream
DES.C -> {magic} -> FPAG configuration stream
I dont think we will see this in the near future, but this MAGIC is
what I think is what will make this field of endeavor more relevant.
And it should use standard, traditional FPGAs, because otherwise you wont
be able to buy them in a few years. You NEED the devices to be main
stream, so that more traditional uses will keep the volumes high.
>Most other Xilinx chips are "island style" FPGAs (as opposed to "cellular
>style") and have a less uniform structure, with patches of processing
>surrounded by interconnect.
This is not true. What you are looking at is the data sheet representation
of the FPGA tile. The actual implementation in terms of silicon topology
may look nothing like it. Both are irrelevant. What matters is that the
logic have sufficient routing resources to get from sources to
destinations. This is a function of the amount of routing resorces, the
connectivity (Xilinx PIPS for example), and how good the place and route
software is at putting things together given those resources.
For a well designed FPGA architecture, only in the extreme does the
details of the routing topology matter. For all other cases, in the
current state of the art of FPGAs (I believe that is the XC4000XL/XV and
Virtex), there is sufficient routing for any well placed design. (I have
100,000 gate designs that route to completion without problems, and quite
rapidly).
> Such components appear less useful than they might be to those looking
> at cellular automata approaches.
I disagree. Just because you look at an architecture and the diagram
shows you that there is (for instance) nearest neighbor conectivity in
all directions, does not mean that something like Virtex that shows a
logic cluster and a routing cluster can't implement the same design just
as easilly, and maybe significantly faster.
>Most FPGAs have too much space devoted to look-up tables, and not enough
>space devoted to flip-flops, as well - for my taste.
My preference is 1 FF with CE per LUT, with carry logic, RAM capability,
a TBUF.
>This is partly because they are used to prototype VLSI chips, which are
>generally designed to be used in conjunction with external RAM.
Not at all. Any FPGA vendor that optimized their architecture for
prototyping ASICs (or VLSI chips as you say) would be out of business.
The FPGA vendors that are successful, are so because they build parts that
are worthy of going into production designs, and do go into production
designs. Xilinx and Altera do not each do about $620,000,000 revenue per
year building chips for one-off prototypes.
The architectures that they both use are both about 1 LUT per FF. What may
not be apparent is that in the details of the TILE (logic + FF + routing +
connectivity + configuration + test structures + other) the LUT + FF is
probably less than 20%.
>The whole legacy VN-architecture idea of having RAM physically
>separated from the processor seems like a real problem to me.
And I totally agree. But look at the XC4000, Virtex, FLEX, 40K and even
the most recent stuff from Cypress. They all are putting RAM on chip, to
allow very high bandwidth access, without going off chip.
> /All/ my applications seem to require that the RAM be physically
> situated right next to the logic elements, and distributed uniformly
> among the processing elements.
Sounds like the XC4000 and Virtex. So the real problem is that you are
using (or assuming that you will be using) the 6200 which has no RAM :-)
>There are some other ways in which I'd like to see the FPGA market
>develop. Currently the LUTs in FPGAs are too large and take up too much
>space.
Totally disagree. This is the path to the Dark Side (tm). Down this path
is the fine grain stuff that I detest so much. The LUT is less than 10% of
the tile. Reducing it further (a 3-LUT) for instance changes the tile by
less than 5%, yet a whole lot of usefull functions are no longer possible,
i.e 1 bit add/sub (needs An, Bn, CARRYn, Add/Sub control), which is also
needed to build up/down counters.
> I would like to see simpler components more closely packed.
Shrinking the LUT wont help packing at all.
>Then there's reversibility. Current FPGAs can eat power and run hot.
>In the next ten years this will become a significant limiting factor,
>and it is /largely/ an unnecessary one.
>I would like to see *reversible* FPGAs, composed of large numbers of
>Fredkin gates - or equivalent reversible logic.
If a company came out with such a product tomorrow, they would go bust,
guaranteed!
The only customers would be a handfull of academic researchers.
For this to make sense, there needs to be the infrastructure to do design
with this type of technology, including synthesys, simulation,
verification, ATPG, BIST, etc, etc, etc. This infrastructure would need to
be main stream (i.e. ASIC and full custom design) before it makes any
sense for an FPGA vendor to touch it. FPGA vendors are incapable of
driving such a change in design tools.
> I think this is a completely fundamental step, one which is inevitable,
> and consequently one which FPGA manufacturers should be looking at
> today.
While I would feel uncomfortable taking a shot at this, I feel that there
are many other issues that require FPGA vendors attention before going
down this path with any resources.
>__________
> |im |yler The
>Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com
Philip Freidin.
Guy that uses FPGAs.
Article: 16772salve C'è qualche italiano che (dietro pagamento) puo' programmarmi una mach210????? 73Article: 16773
news.pcnet.com wrote in message ... >I was thinking about putting up a page devoted to new engineers entering the >FPGA market. > I'm new to the scene and find fpga technology extremely attractive. I would be very interested in implementing any java applets that could help illustrate design methodology on such a site. SimonArticle: 16774
Hi, i describe a design with a process with only the CLK and RESET in the sensitivity list in the goal to have only one clocked register at end. The synthesizer (Synplify) generate naturally a Warning "Incomplete sensitivity list" but with the remark "assuming completeness" !!! What's the meaning of "assuming completeness"? Did the synthesizer generate a process with a complete sensivity list ? Thanks for the time. kerim el imem.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z