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This is a multi-part message in MIME format. --------------9966CE9F98DDCDB17E66E923 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit i would suggest xilinx foundation series( new version supports virtex family too) rather than altera because it has very good placement and routing ( floorplanner) than altera max plus all the best kamal Shawki Areibi wrote: > We are introducing a new course on Digital Design at the School of > Engineering > at the University of Guelph. We would like to choose between the Altera > MAXII-Plus and the Xilinx Foundation Series Software. > Anyone with the experience of using the two systems? Which is better to > use > by the students (i.e simpler to use e.t.c) > Thanks, > Shawki Areibi > > -- > Shawki Areibi > Assistant Professor > School of Engineering > University of Guelph > Guelph, Ont, Canada N1G 2W1 > Tel: (519) 824-4120 > Fax: (519) 836-0227 --------------9966CE9F98DDCDB17E66E923 Content-Type: text/x-vcard; charset=us-ascii; name="raja.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for raja Content-Disposition: attachment; filename="raja.vcf" begin:vcard n:kamalanathan;Raja tel;home:07 38761962 tel;work:07 33658849 x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:raja@elec.uq.edu.au fn:Raja kamalanathan end:vcard --------------9966CE9F98DDCDB17E66E923--Article: 20176
Ray, Peter Alfke kindly informed me via private email that my assertion was totally wrong, and that the Virtex/Spartan2 DLLs have a completely digital implementation. Peter expressed some doubt that it was possible to implement a VCO using a ring oscillator. ISTR from my VLSI classes taken many moons ago that such a VCO could be made by adjusting the supply voltage to the delay elements in the ring oscillator. This would still require some analog elements (opamp + capacitor to make the loop filter), and so would be more expensive than the DLL. I'd be interested to know how Altera actually do it. On a slightly different topic: *any* DLL or PLL will have some sensitivity to noise on the supply votlage. I haven't seen any specifications for this. (Recently I've built a few boards using Motorolla microprocessors with onboard PLLs. They recommended using separately filtered supplies for the PLLs (which had separate supply pins for this purpose).) Thanks, Allan. On Fri, 28 Jan 2000 17:41:52 GMT, Ray Andraka <randraka@ids.net> wrote: >I hadn't considered a VCO made as a ring oscillator. I'll have to noodle on that. >I'm pretty sure the DLL's loop filter function can be done digitally pretty easily >(require more than one phase miss before moving to a new delay tap). > >Allan Herriman wrote: > >> On Thu, 27 Jan 2000 15:26:31 GMT, Ray Andraka <randraka@ids.net> >> wrote: >> >> >Oh, one more thing, The DLL is implemented basically as delay gates with >> >feedback, which allows it to be done in the same process as the SRAM >> >technology for the rest of the chip, with virtually nothing extra added to the >> >process or yield testing. It's a totally digital circuit. That means the >> >incremental cost of adding the DLL is virtually nothing after the NRE. >> > >> >Contrast that with a PLL, which by nature is an analog animal. That means >> >extra care is required in the fab, as there are parameters that have to be met >> >which would not have to be met for a strictly digital circuit. >> >> Ray, I disagree with your statements about DLLs and PLLs. Both are >> implemented with delay lines made from gates. Both use feedback to >> adjust the gate delay. Both have an analog loop filter (but the DLL >> loop filter is simpler). >> >> About the only difference is that the PLL has the output of its delay >> line fed back to the input to make a ring oscillator. The DLL has its >> input connected to the input clock signal. This should give the DLL >> better jitter performance, but the quoted specs (A vs X) are >> identical. >> >> (BTW, I'm making some guesses about the implementations. It is >> possible that they have been implemented in other ways.) >> >> Regards, >> Allan. >> >> >Magnus Homann wrote: >> > >> >> Steve Dewey <steve@s-dewey123.demon.co.uk> writes: >> >> >> >> > One point in this debate is that Xylinx seem to put the DLLs into ALL >> >> > the Virtex and Spartan parts. Altera definitely only puts them into >> >> > certain speed grades/packages/device sizes. So you have to pay extra and >> >> > probably not use the speed grade, package, or device size that you >> >> > thought. >> >> >> >> Well, wont you have to pay extra for the Xilinx DLLs all the time too? >> >> >> >> Homann >> >> -- >> >> Magnus Homann, M.Sc. CS & E >> >> d0asta@dtek.chalmers.se >> > >> >-- >> >-Ray Andraka, P.E. >> >President, the Andraka Consulting Group, Inc. >> >401/884-7930 Fax 401/884-7950 >> >email randraka@ids.net >> >http://users.ids.net/~randraka >> > >> > > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > >Article: 20177
Mike Horwath <mikeh@merge.com> wrote in message news:3891ADB2.D28DAA9C@merge.com... > Has anyone used TI serail McBSP to program Spartan XL. If so how did > you accomplish this? We use the regular (unbuffered) mode of a 320VC549 to program an XC4005E. The DSP is far faster than the maximum configuration rate of the 4005 anyway, so we didn't bother with the auto-buffering abilities of the DSP and just sit in a tight loop waiting for each byte to be sent. To do this, the only tricky signals are Init and CClk. We used a couple of CLBs off of an address decoder CPLD that we already had on the board to gate CClk. We use XIO off of the DSP for Init; the CPLD then stops providing CClk to the FPGA until it sees the first frame signal from the DSP's serial port, at which point it starts simply passing it through (again note that timing is slow enough that you can get away with slightly crude methods such as this). To build the bitstream, Xilinx has a tool that takes the configuration bitstream file and dumps it as ASCII hex. It's configurable enough that you can get it to generate a compilable file in just about any language you'd care to, and also get it to produce output as bytes, words, long words, with big endian or little endian bit ordering. I think this program is called "makesrc," but I could be completely mis-remembering that detail (it's all magically done in a makefile in our environment). Our current task is getting a PLX9054 to program a Virtex... ---Joel KolstadArticle: 20178
it's a RISC microprocessor core - see the ARm website http://www.arm.com ¹Ú±¸¿ë <hereim@maru.comtec.re.kr> wrote in message news:86rlav$ovu$1@news.nuri.net... > hi, friends. > what is the ARM core? Is there any site or Book for this question? > thanks, good day!! > >Article: 20179
also try Stefan Doll's verification course at : http://www.i2.i-2000.com/~stefan/vcourse/html/ Madison <madisonfj@uswest.net> wrote in message news:38927C20.36CA5CB9@uswest.net... > I am seeking a source of comprehensive information on building > testbenches for programmable logic simulations. The reference material > I presently have (both instructional texts and software documentation) > give this matter very light treatment. Are there books which cover > testbenches exclusively or at least have thorough coverage of the topic? > > Thanks and Best Regards, > > Frank Madison >Article: 20180
I think that Xilinx foundation is better, because they are less parameters to fix to obtain a executable design with students, altough all these parameters can be manipulated. regards. Daniel BERQUET In article <3891C2B3.9FB4614E@uoguelph.ca>, Shawki Areibi <sareibi@uoguelph.ca> wrote: > We are introducing a new course on Digital Design at the School of > Engineering > at the University of Guelph. We would like to choose between the Altera > MAXII-Plus and the Xilinx Foundation Series Software. > Anyone with the experience of using the two systems? Which is better to > use > by the students (i.e simpler to use e.t.c) > Thanks, > Shawki Areibi > > -- > Shawki Areibi > Assistant Professor > School of Engineering > University of Guelph > Guelph, Ont, Canada N1G 2W1 > Tel: (519) 824-4120 > Fax: (519) 836-0227 > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20181
I have tried out the new Foundry 9.4 with 2 different designs for a or3t30 (98% full) and a or3t80 (84% full) (both running at 62.5 MHz). Well, plain-spoken it was a DESASTER!!! Compilation times increased, score was 10 times worse, timing slack was 2 times worse..... (then with 9.35). This version is for me useless.. Did anybody make the same experiences like me? Patrick Muller * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 20182
This is a multi-part message in MIME format. --------------CE98D6D901F9B0D5FE8F47DA Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit As always, I will recommend our XSK-40 product which combines an XS40 FPGA Board with the Xilinx Student Edition for around $200. The Foundation 1.5 software in the Student Edition is very similar to the WebPACK software (which is based on Foundation 2.1). Go to http://www.xess.com/prod009.html for info on the XSK-40 or go to http://www.xess.com to examine the other boards we offer. As always, I recommend a look at http://www.optimagic.com for a list of other sources for free/low-cost software and hardware. Ralph Mason wrote: > I have been using the Xilinx webpack to experiment with VHDL using a couple > of XL95108's and would now like move to a FPGA for larger designs. > > So far my designs have included an AVR so I am quite interested in the Atmel > FPSLIC but I don't think they're readily available yet, and I'm not sure of > what tools are available for them. > > So which I am looking for is a beginner friendly FPGA with a free or low > cost VHDL compiler and programmer. Preferably a low cost part that is easy > to obtain one or two at a time. > > Thanks for any help. --------------CE98D6D901F9B0D5FE8F47DA Content-Type: text/x-vcard; charset=us-ascii; name="devb.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dave Vanden Bout Content-Disposition: attachment; filename="devb.vcf" begin:vcard n:Vanden Bout;David tel;fax:(919) 387-1302 tel;work:(919) 387-0076 x-mozilla-html:FALSE url:http://www.xess.com org:XESS Corp. adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA version:2.1 email;internet:devb@xess.com title:FPGA Product Manager x-mozilla-cpt:;28560 fn:Dave Vanden Bout end:vcard --------------CE98D6D901F9B0D5FE8F47DA--Article: 20183
>EDN mag, Jan 6th issue, p. 24 had some unattributed Spartan-2 price projections: >XC2S15 3.95, XC2S30 4.95, XC2S50 7.95, XC2S100 9.95, XC2S150 12.95 >The fine print states that this pricing is for 250,000 units, lowest >speed and cheapest package, end of 2000. They'll be throwing in a free >pizza and beverage with every million-dollar order, too :) > >regards, >Tom Burgess You forgot about the free Ginsu knife set ;-) Sorry, Tom, I can only print the prices they're willing to give me. My mind-reading abilities haven't been sufficiently fine-tuned yet to allow me extract additional price/quantity combinations from the brains of Xilinx's marketing folks, especially when I get briefed on the product over the telephone instead of face-to-face.....(long-distance, don'tchaknow) Brian Dipert Technical Editor: Memory, Multimedia and Programmable Logic EDN Magazine: The Design Magazine Of The Electronics Industry http://www.ednmag.com Contributing Editor; CommVerge Magazine http://www.commvergemag.com 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (voice), (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** mailto:bdipert@NOSPAM.pacbell.net Visit me at http://members.aol.com/bdipertArticle: 20184
I have been using the Xilinx webpack to experiment with VHDL using a couple of XL95108's and would now like move to a FPGA for larger designs. So far my designs have included an AVR so I am quite interested in the Atmel FPSLIC but I don't think they're readily available yet, and I'm not sure of what tools are available for them. So which I am looking for is a beginner friendly FPGA with a free or low cost VHDL compiler and programmer. Preferably a low cost part that is easy to obtain one or two at a time. Thanks for any help.Article: 20185
Hi, Thanks RC, i'll add lucent to my green book (red book: try again, black book: don't bother). Rickman wrote: > > Russell, > > I am not trying to push the Lucent stuff, but they do give away their > toolset which includes the front end (Viewlogic) and the back end tools > as well as VHDL support (or so I hear, I have not tried to use it). You > just have to ask your FAE to provide you with a copy. My FAE (Rick > Golabowski of Impact) has been very supportive (especially on snow days > ;). Try your distributor based FAEs. > > I like the Xilinx tools which work well if they are a bit hard to learn. > But I have found the Lucent tools to be very useful as well and I am > getting decent support from my local FAE as well as some advice from Bob > Wagner via postings here. > > One common point to all of the FPGA tools I have looked at; they all > seem to be going in the direction of HDL support. Every time I ask > questions the responder seems to assume that I am using an HDL ignoring > the possibility of my entry method being schematic. I am using schematic > entry because I often have pieces of my design that need to be very > highly optimized which I just don't have enough control via VHDL to make > work. So rather than do a mixed design, I just use schematic capture. I > also have tight schedules which I have found fit better with predictable > schematic capture. > > My concern is that I may end up like the dodo bird when it comes to > support. A lot of the support engineers already don't use schematic > tools and so can't answer questions about them. So if you do any serious > design in FPGAs, you may want to go for the HDL tools and keep schematic > as an adjunct for the tough pieces. > > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- ******************************************* * Russell Shaw, B.Eng, M.Eng(Research) * * Electronics Consultant * * email: russell@webaxs.net * * Australia * *******************************************Article: 20186
I've just put up a HowTo page for running Xilinx place and route tools under Linux. http://www.polybus.com/xilinx_on_linux.htmlArticle: 20187
I had an old article in Personal Engineering magazine (January 1998) that covered this topic. See http://www.optimagic.com/acrobat/pein_0198.pdf. Some of the figures are a bit difficult to make out. -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- "Bonio Lopez" <bonio.lopezNOboSPAM@gmx.ch.invalid> wrote in message news:2a42f762.e1d74b29@usw-ex0101-003.remarq.com... > Hi friends, > i am trying to synthesize one external mC core with Sinplicity and > Leonardo. > I have got very strange results by synplisity. > The Leonardo make really good job, > but simpisity synthesize some memory cells (quite many of them) as > combinatorial > loops. > Have somebody any thinks about this phenomena. > Sorry, that i can't send you source code. > > > > * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * > The fastest and easiest way to search and participate in Usenet - Free! >Article: 20188
On Fri, 28 Jan 2000 17:41:52 GMT, Ray Andraka <randraka@ids.net> wrote: >I hadn't considered a VCO made as a ring oscillator. I'll have to noodle on that. Here's a description of a ring oscillator used as a VCO in a PLL. http://www.cypress.com/pub/appnotes/robo.pdf (see figure 29, on page 14) Regards, Allan.Article: 20189
The Programmable Logic Jump Station at http://www.optimagic.com might be a good place to start. It has links for practically all topics. You might check out the FAQ section as it has an overview on the various programmable logic architectures. It hasn't been updated for awhile but the basic concepts still apply. -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- "#XUE ZHONG#" <P144850500@ntu.edu.sg> wrote in message news:0CF260C495FED111A6610000F866308D09C8C10E@mail3.ntu.edu.sg... > Hi folks, > > In face, I am familiar with Lattice's ispPLD chip 1000, 2000, 3000 > series: > Such as 1016, 2032, etc. including there structures, and programming. > > How about the difference between FPGA and the same. Where can I find > (website) > the information about FPGA, and learn it quickly, I need to develop > circurts with FPGA > in the near future. > > Thanks. >Article: 20190
Dave Vanden Bout <devb@xess.com> wrote in message news:38945AC9.41B6AA23@xess.com... > As always, I will recommend our XSK-40 product which combines an XS40 FPGA Board with the Xilinx Student Edition for around $200. Does this come with programming software (for the XS40 board) that works under Windows NT or Linux yet? When I looked at it a couple of years ago, the provided software appeared a little on the amateurish side; hopefully a lot has changed over time. ---Joel KolstadArticle: 20191
B. Joshua Rosen wrote:
>
> I've just put up a HowTo page for running Xilinx place and route tools under Linux.
>
> http://www.polybus.com/xilinx_on_linux.html
Alleluyah!!!!!!!
I was thinking about trying this out to see if its possible
but you've beat me to it. This is fantastic news. I may finally
be able to dump WinNT at work like I already have at home.
Erik
--
+-------------------------------------------------+
Erik de Castro Lopo erikd@zip.com.au
+-------------------------------------------------+
"There are two ways of constructing a software design. One way is
to make it so simple that there are obviously no deficiencies
and the other is to make it so complicated that there are no
obvious deficiencies." -- C A R Hoare
Article: 20192Hi Everyone, Many thanks to all of you who replied to my original posting about downloading a Xilinx design from a Linux box: you've given me several strategies to try out. I'm going to try Larry Doolittle's Linux port of the XESS utility first. I note that this has to run as root in order to access the IO port: has anyone looked into adding calls to setuid() so that it uses the real user id to read the input files? Has anyone else used this with the VCC board or another Virtex device? Anything else I should know? Cheers, --Phil.Article: 20193
On Fri, 28 Jan 2000, Tim Tyler wrote: > : what is the ARM core? Is there any site or Book for this question? > > http://www.arm.com/ > > ARM Architecture Reference Manual - D. Jaggar; > ARM System Architecture - S.Furber; I can recommend the Steve Furber book - he was one of the Acorn team involved at the time of the development of the Acorn Risc Machine (later renamed to Advanced Risc Machine - ARM) > The ARM RISC Chip, A Programmer's Guide A. van Someron & C. Atack. > -- > Sprow.Article: 20194
This is a multi-part message in MIME format. --------------D05E331F891685464BA50A8E Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Joel Kolstad wrote: > Dave Vanden Bout <devb@xess.com> wrote in message > news:38945AC9.41B6AA23@xess.com... > > As always, I will recommend our XSK-40 product which combines an XS40 FPGA > Board with the Xilinx Student Edition for around $200. > > Does this come with programming software (for the XS40 board) that works > under Windows NT or Linux yet? When I looked at it a couple of years ago, > the provided software appeared a little on the amateurish side; hopefully a > lot has changed over time. > > ---Joel Kolstad Our software for testing, programming, and debugging the XS40 Board runs under Win95/98/NT in both a DOS window and using the GUI. You can read more about that at http://www.xess.com/gxstools-v3_0.pdf. We have made the underlying code for these tools publicly available so others can port them as they see fit. Larry Doolittle and others have made ports to Linux. We will have no official Linux port of our tools until Xilinx has an official Linux port of Foundation. --------------D05E331F891685464BA50A8E Content-Type: text/x-vcard; charset=us-ascii; name="devb.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dave Vanden Bout Content-Disposition: attachment; filename="devb.vcf" begin:vcard n:Vanden Bout;David tel;fax:(919) 387-1302 tel;work:(919) 387-0076 x-mozilla-html:FALSE url:http://www.xess.com org:XESS Corp. adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA version:2.1 email;internet:devb@xess.com title:FPGA Product Manager x-mozilla-cpt:;28560 fn:Dave Vanden Bout end:vcard --------------D05E331F891685464BA50A8E--Article: 20195
Ray Andraka <randraka@ids.net> wrote: > I hadn't considered a VCO made as a ring oscillator. Take a look at the Lucent 3T parts. Their clock synchronizer can be used in either DLL or PLL mode. It's implemented as a multi-tap voltage-controlled delay line. -- Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby Fermi National Accelerator Lab Phone: 630-840-3668 Batavia, IL 60510 Fax: 630-840-5406Article: 20196
Bummer. Thanks for the warning. I guess it's not too surprising since they made some major changes to the constraints file processing. pmueller <pbcmuellerNOpbSPAM@hotmail.com.invalid> wrote: > I have tried out the new Foundry 9.4 with 2 different designs for > a or3t30 (98% full) and a or3t80 (84% full) (both running at 62.5 > MHz). > > Well, plain-spoken it was a DESASTER!!! > > Compilation times increased, score was 10 times worse, Does the part meet your timing constraints? Did you use the same timing analyzer for both measurements? (IE: did you use the 9.35 analyzer to check the 9.4 compilation or the 9.4 analyzer to check the 9.35 compliation?) Lucent may have just changed the way they compute the score. Also note that some new paths-types were added to the analysis: For example, 9.35 does not check paths through an open latch (a serious flaw that I have been whining about for years.) 9.4 does (according to the release notes). It also is supposed to handle timing between multiple clock domains differently (better). > timing slack was 2 times worse..... (then with 9.35). Unfortunately, the software doesn't try to optimize timing slack. To get an optimal design, I usually rachet-up the clock speed until it no-longer routes. For example, I try to place a 62.5 MHz design using an 80 MHz constraint. Even if a few paths fail to meet that constraint, the whole design runs easily at 62.5. -- Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby Fermi National Accelerator Lab Phone: 630-840-3668 Batavia, IL 60510 Fax: 630-840-5406Article: 20197
Because EEPROM technology requires additional mask steps during manufacturing, EEPROM-based devices are more expensive to manufacture, not to mention more expensive to test. The incremental cost is probably insignificant on a small device but become intolerable as the die size increases. Also, generally SRAM is a leading-edge process. It's one of the first to be migrated to a new, more aggressive process technology. A manufacturing fab needs SRAM to be up and running before implementing more complex processes like EEPROM. The more aggressive fab process is one of the reasons that SRAM-based devices are generally faster and denser. The most direct evidence of this is to see what process is used by the largest and fastest devices like Xilinx Virtex and Altera Apex. Both Xilinx and Altera are racing down the process curve from 0.25u, to 0.18u, to 0.15u, to .... -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- "George" <g_roberts75@hotmail.com> wrote in message news:86nge5$sq2$1@news.qub.ac.uk... > Hi Folks, > > EEPROM based FPGAs are in-circuit re-programmable FPGAs, which are, unlike > SRAM based FPGAs, not volatile. Their disadvantage, I presume, is that they > are slower. Could you think about any other disadvantage? or advantage? > compared to SRAM based ones. > > Cheers. > >Article: 20198
Has anyone in this group worked with these devices, and if so, could they share their experiences? We used Gatefield FPGAs (GF200 and GF250) to prototype our last ASIC design, and were quite happy with the design flow and performance that these FPGAs offered. We have been planning to use the new Actel proAsic devices to prototype our next ASIC design, however it has been very difficult to obtain information from them about the availability of their higher density devices, let alone pricing. We understant the the 130 series is available, however we need the additional logic tiles found in the 180 series. Any opinions as to the viability of these FPGAs in the market, long term? I'm getting the impression that many of their higher density devices are vapour-ware until a market materializes for them, and perhaps the market just isn't there. The quantity we will use to prototype our ASIC is obviously very small, and they can't survive on small fry such as us. AdrianArticle: 20199
I thought the point to using a DLL was to get away from the analog circuit. I know the xilinx DLL is entirely digital, and I have played a little with making DLLs in the XC4000 series parts using the carry chain as a tapped delay. Theoretically speaking, I suppose one could make a ring oscillator with the same type of structure to make an entirely digital PLL (without the many-x clock normally associated with DPLLs). Practically, though, I don't see how it would work because the delays in the selection logic are in the ring, and would tend to swamp the tapped delay. To make the selection logic delay inconsequential, the adjustable part of the delay chain would have to be too long to get the frequencies out that we need in modern designs. Don Husby wrote: > Ray Andraka <randraka@ids.net> wrote: > > I hadn't considered a VCO made as a ring oscillator. > > Take a look at the Lucent 3T parts. Their clock synchronizer > can be used in either DLL or PLL mode. It's implemented as a > multi-tap voltage-controlled delay line. > > -- > Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby > Fermi National Accelerator Lab Phone: 630-840-3668 > Batavia, IL 60510 Fax: 630-840-5406 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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