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Klaus Falser <kfalser@durst.it> wrote: : You could use the smallest Xilinx XC9500 device. : Programming software is free and downloadable from there site (WebPack) : and programming is done through JTAG (6 pins ) form the parellel port : of a PC. The adapter should cost around 50$, but if you want to : build it itself there should be the schematics somewhere on Xilinx's : Web-sites. I will look into it. Someone else also suggested one of Lattice's small CPLD's. These may be better than the GAL. Thanks for the suggestions. -- Shawn D'Alimonte - sdalimon@ee.ryerson.ca "Faster processors are nice, but they are not truly revolutionary. And neither are colors." - Jim Collas, Amiga Inc.Article: 20051
On Thu, 30 Dec 1999 11:35:10 +0100, Genio Kronauer <g.kronauer@kronauer-digital.de> wrote: >Recently Xilinx has changed process for XC900 series from 0.6u to 0.5u, Die step often means you are getting a much faster part than you are used to. I suspect you are seeing noise related problems, probably caused by higher ground bounce of the faster 0.5u device. If this is so, the problem can be fixed by better power/ground distribution and decoupling. The faster part may also cause problems with setup and hold requirements to external devices from the 9500 device. It is a good idea to requalify your designs over your operating temperature and VCC range when a manufacturer changes the process on a device. See http://support.xilinx.com/techdocs/271.htm and http://www.xilinx.com/xcell/xl30/xl30_36.pdf I hope this helps you out. >see also http://www.xilinx.com/partinfo/notify/pcn9803.htm . >Since that, some 30% of chips of a certain design work, other designs >work >on 70% of chips, and some don?t work at all. >Has anybody the same problem? >Are those chips suffering from ESD? >Or do they have some problem with powersupply or do they latch up more >easily? >Do failiures affect 9572-15, or also other types? >Jedec's are not under suspect anymore: Failiures are seen also in >designs >without any asynchronous path at all. > >Any hints appreciated. >BR >Genio > >Article: 20052
Hi ! Its easy : Open the VHDL Windows. Go to Menu 'Project' Choose 'Create Macro' Maybe you have to systhesize the code first. Regards, -- Holger Kleinert Development / Support IBP Instruments GmbH Sutelstrasse 7a D-30659 Hannover, Germany http://www.ibpmt.com Fon : +49-511-651647 Fax : +49-511-652283 Steven Sanders <sanders@imec.be> schrieb in im Newsbeitrag: 388DA0C9.83D9D662@imec.be... > Hello, > > I`m a newbie to the Xilinx Foundation Series. I have 5 VHDL files > (describing 5 components) > and I want to link these in a top file, but graphical! How do I make > symbols out of my VHDL code? > > Thanx > > Steven. >Article: 20053
Peter Fenn wrote: > Please advise: > Can Atmel AT17c256 be used in place of Xilinx XC17s20 config PROM? > If we assume that all these SPROMs can spit out a serial bitstream, here are some subtle points: RESET polarity. You have to program this, and you should go for active Low RESET, so that you can drive this pin from INIT. Reset polarity programming is the most confusing aspect of SPROMs. Power-on delay. If the SPROM takes longer to power up than the FPGA, you are in trouble, unless you find ways to stall the FPGA. Peter Alfke, Xilinx ApplicationsArticle: 20054
While I have not done this, it should be very doable to prgram an FPGA on a Linux PC. Check out the PDF at: http://www.support.xilinx.com/apps/config.htm Take a look at the App Note "Configuring FPGAs Over a Processor Bus". It contains diagrams and code to program an FPGA from a PCs ISA bus. Another alternative would be to write to either the parallel or serial ports by modifying the example code. Another app note is XAPP058. This could be adapted also with some research. Have fun. -Rodger Phil Endecott <phil_endecott@spamcop.net> wrote in message news:388C7A42.BA29F505@spamcop.net... > Hi FPGA Experts, > > I have a Virtex prototyping board from VCC (www.vcc.com) which I > currently program from an NT PC running the Xilinx alliance tools. The > problem is that I run all of the other tools (VHDL simulation & > synthesis, place & route) on a Sun; this machine is locked away in a > machine room somewhere, and I have a Linux PC on my desk which I use as > an X-terminal. I'd like to be able to get rid of the NT PC and plug the > VCC board directly into my Linux box, but I can't find a way to download > the bit file. What I need is either a utility that will download a bit > file from Linux (I don't need anything like the hardware debugger), or > alternatively a way to make the Sun version of the alliance tools talk > to a serial port that's not on the local machine. Xilinx support tell > me that neither is possible. > > I can't believe that I'm the only person ever to try to do this. Does > anyone have any experience to share? If someone knows the protocol > needed to talk to an X-checker or MultiLINX cable I'm happy to write my > own tool. > > Thanks in advance, > > --Phil.Article: 20055
On Tue, 25 Jan 2000 01:57:53 GMT, bobperl@best_no_spam_thanks.com (Bob Perlman) wrote: > The plane-to-plane capacitance is >nice, being low-inductance, but there isn't much of it, particularly >if you have lots of stuff switching. CMOS-based designs can have >rather astonishing dI/dt requirements; I'd think a long time before >trying to build a board without high-frequency bypass caps. I'm not sure that it takes any thinking about. The last time I checked, a reasonably-sized board with one power and one ground plane had a total plane capacitance of, IIRC, a few 10's of nF. A given chip is only going to have access to the stored charge in its own local region, and so it has a local capacitance of maybe 100pF. Putting in some ballpark numbers shows that the most you can get out of this cap is maybe 30 or 40mA, over a 0.5ns interval, for a reasonable supply voltage drop of 5%. As you say, modern CMOS chips have *very* much greater transient current requirements than this. 30 or 40mA may be enough for one switching output, but that's about it. EvanArticle: 20056
Anyone managed this? I've tried modding the boot sector with a '95 boot disk and Debug, but Debug can't even see the C drive, let alone modify the boot sector. And does anyone know where the serial number is? Presumably the NTFS location is different from the FAT16 and FAT32 locations. By the way, this is (I think) legal. Thanks EvanArticle: 20057
rodger (brownsco@frii.com) wrote:
: While I have not done this, it should be very doable to
: prgram an FPGA on a Linux PC.
Of course it can be done.
Right now my toolchain for a Xilinx Spartan XCS10 is:
* Icarus Verilog on Linux http://www.geda.seul.org/tools/verilog/
* Xilinx Alliance on Solaris
* XStools http://www.xess.com/
ported to Linux twice, see
either ftp.microux.com/pub/pilotscope/xstools.tar.gz
or http://recycle.lbl.gov/~ldoolitt/fpga/
One of these days Alliance will run on Linux, and I can stop
mooching off of another group's Sun. Right now that step is
embedded within a Linux Makefile using ssh. Downloading 12 Kbytes
from Linux to the XCS10 takes 1.93 seconds.
: Take a look at the App Note "Configuring FPGAs Over a
: Processor Bus". It contains diagrams and code to program
: an FPGA from a PCs ISA bus.
Cute. But not relevant for an existing development kit.
: Another alternative would be to write to either the parallel or
: serial ports by modifying the example code.
The parallel port works trivially. Lots of people have made
it work for the XESS prototyping board listed above.
: > I have a Virtex prototyping board from VCC (www.vcc.com) which I
: > currently program from an NT PC running the Xilinx alliance tools. The
: > problem is that I run all of the other tools (VHDL simulation &
: > synthesis, place & route) on a Sun; this machine is locked away in a
: > machine room somewhere, and I have a Linux PC on my desk which I use as
: > an X-terminal. I'd like to be able to get rid of the NT PC and plug the
: > VCC board directly into my Linux box, but I can't find a way to download
: > the bit file. What I need is either a utility that will download a bit
: > file from Linux (I don't need anything like the hardware debugger), or
: > alternatively a way to make the Sun version of the alliance tools talk
: > to a serial port that's not on the local machine. Xilinx support tell
: > me that neither is possible.
Outrageous. Either they don't understand the question,
or they are putting short-term stockholder greed ahead
of your desire to get the job done.
: > I can't believe that I'm the only person ever to try to do this. Does
: > anyone have any experience to share? If someone knows the protocol
: > needed to talk to an X-checker or MultiLINX cable I'm happy to write my
: > own tool.
If this cable connects the programming pins of the Virtex to
the parallel port of the PC, like the XESS board does, you just
look at the Virtex manual.
- Larry Doolittle <LRDoolittle@lbl.gov>
Article: 20058Hello all, I've just obtained the 1.3 student edition and am running on NT. Whenever I try to implement a design using XACTstep, map always produces an exception error. Thanks for any ideas, ChuckArticle: 20059
Larry Doolittle <ldoolitt@recycle> wrote in message news:86l7q6$if71@overload.lbl.gov... > rodger (brownsco@frii.com) wrote: > : While I have not done this, it should be very doable to > : prgram an FPGA on a Linux PC. > > Of course it can be done. A small point... Jbits will run on Linux. You don't need any other tools. Steve Casselman, President Virtual Computer Corp.Article: 20060
CALL FOR PAPERS **************************************************************************** Reconfigurable Technology: FPGAs & Reconfigurable Processors for Computing and Applications To be held as part of: SPIE's Photonics East Symposium on Voice Video, and Data Communications, 5-8 November 2000, Boston Massachusetts **************************************************************************** The past decade has seen a dramatic increase in the use of reconfigurable logic devices in commerical applications. Among the most significant milestones in this field are the arrival of million plus gate logic devices and the introduction of a series of new reconfigurable processors. These devices are ideal for data-intensive, Internet, DSP,and other high performance embedded telecom and datacom applications. Many systems engineers are using reconfigurable technologies to overcome computation and product development bottlenecks. The advent of million plus gate counts and advanced manufacturing techniques have made these reconfigurable devices more economical and practical for computing systems. This conference, in it's fifth year, focuses on three areas of reconfigurable technology: 1) new devices and systems 2) tools and techniques 3) high-performance applications The conference will present papers that illustrate applications and techniques for using reconfigurable technology in both design and production cycles. Papers relating to the following areas are solicited: * field programmable devices * reconfigurable processors * programming tools and methodologies for reconfigurable devices & systems * applications and platforms utilizing reconfigurable technology for: - network & data intensive applications - hardware/software codesign - rapid product development - high-performance computing - image, signal, and communication processing - robotics - evolvable algorithms Conference Chairs: John Schewel, Virtual Computer Corp.; Peter M. Athanas, Virginia Polytechnic Institute & State Univ.; Chris Dick, Xilinx Inc.; John T. McHenry, National Security Agency IMPORTANT DATES ================= On-site Proceedings requires the following paper submission schedule. * Deadline for Abstract submission: March 27, 2000 * * Deadline for final Manuscripts: August 14, 2000 * SUBMISSION INSTRUCTIONS: ================= Accepted papers are required to make an oral presentation at the conference in Boston,MA. Internet http://www.spie.org/info/vv E-Mail pecalls@spie.org Fax 1(360)647-1445 Mail SPIE - The International Society for Optical Engineering PO Box 10 Bellingham, WA 98227 If you have any questions regarding the conference contact the Conference Chairman, John Schewel jas@vcc.com (+1 818-342-8294). ****************************************************************************Article: 20061
On Tue, 25 Jan 2000 01:57:53 GMT, bobperl@best_no_spam_thanks.com (Bob Perlman) wrote: |On 25 Jan 2000 00:47:04 GMT, krw@attglobal.net (Keith R. Williams) |wrote: | |<stuff snipped> |>On Virtex/VirtexE? That's not what Xilinx is saying. That's not |>my experience either. Our product is a BGA and we're having all |>sorts of problems supplying the power to the part (note that this |>is on testers with their inherent problems, so far). |>> |>> 460 is a LOT of caps! |> |>Not really. I have lots more space for them. ;-) In fact I'm |>using *many* 470uF SMT caps in parallel instead of PTH bulk |>capacitors. Parallel is an advantage. Putting them on the |>back-side is an advantage. I gotta buy the things in reels |>anyway so it doesn't matter much if I need one or use a hundred. |<more stuff snipped> | |One of the best how-many-and-what-kind-of-bypass-capacitors-do-I-need |articles I've seen is by some signal integrity engineers at Sun, |titled, "Power Distribution System Design Methodology and Capacitor |Selection for Modern CMOS Technology." You can find it online at: | |http://www.qsl.net/wb6tpu/si_documents/docs.html | |One comment about capacitor placement: if you have a 500ps risetime |(as more than a few modern devices do) and the bypass capacitor is |more than an inch or so away from the device's power pins, that cap |isn't helping source current for that edge, except to replenish plane |charge after the fact. Placement does matter, at least for the |smaller, high-frequency bypass caps (the larger, lower-frequency bulk |capacitors are another matter). The plane-to-plane capacitance is |nice, being low-inductance, but there isn't much of it, particularly |if you have lots of stuff switching. CMOS-based designs can have |rather astonishing dI/dt requirements; I'd think a long time before |trying to build a board without high-frequency bypass caps. | |Take care, |Bob Perlman | |----------------------------------------------------- |Bob Perlman |Cambrian Design Works |Digital Design, Signal Integrity |http://www.best.com/~bobperl/cdw.htm |Send e-mail replies to best<dot>com, username bobperl |----------------------------------------------------- Bob, thanks for the reference. The papers are interesting, but both ignore plane capacitance. A power-ground plane pair with a small dielectric gap (a few mills can be easily had) is in fact a very low impedance transmission line. Transients looking into the parallel planes (as I see with my TDR experiments) see low-Z transmission line in all radial directions. My testing indicates that the highest impedance a chip pin sees is the via that reaches down from the pin to the power or ground plane; the planes themselves (if the dielectric gap is small) are very stiff for fast transients. Of course, if you need X colombs of charge to keep your chip happy, you'd better have n*X farads available somewhere to supply it. I think my point is that, for properly designed multilayer boards, the planes themselves are an enormous asset in supplying low-impedance power for fast transients. My TDR tests indicate that additional bypass caps can be scattered about, and improve the apparent capacitance a pin sees, without having to be really close to every pin. I have never observed the multiple-resonances effects predicted by the Sun paper Spice models for paralleled caps; I suspect they didn't model the planes. As I get braver, I am using fewer bypass caps, spread farther apart, and am still measuring very clean Vcc and ground noise levels. As parts get smaller, and have *lots* of pins, one eventually will be faced with brickwalling the backside of the board with thousands of head-to-butt capacitors. This will eventually get silly, and our Manufacturing people will stop saying 'hello' in the hallways. John ----------------- "If anybody ever marries you, it will be for the pleasure of hearing you talk piffle," said Harriet, severely.Article: 20062
Free Spirit <Burn@D.man> wrote in message news:388cfa84.417978246@enews.newsguy.com... > The read and write are pretty easy, but I had to use a lot of states > to properly initialize the darn things. Hmm... no CPU interface around? Tossing a multiplexor in front of the registered CAS, RAS, WE and address line outputs and handing the SDRAM data sheet to the device driver guy can do wonderful things... :-) ---Joel KolstadArticle: 20063
Do you know how to link two pins of a virtex fpga like if it is a wire between this two pins ( in order to bypass a fpga... )Article: 20064
In article <388e1f97.4722839@news.dial.pipex.com>, eml@riverside- machines.com.NOSPAM writes >Anyone managed this? I've tried modding the boot sector with a '95 >boot disk and Debug, but Debug can't even see the C drive, let alone >modify the boot sector. And does anyone know where the serial number >is? Presumably the NTFS location is different from the FAT16 and FAT32 >locations. > >By the way, this is (I think) legal. > Depends on why you would want to do this... If you're trying to subvert a s/w licensing schema (say FLEXlm) then its not.Article: 20065
Yes, you can use it - they behave the same way as XC17S20. And they bring you the possibility of in system programming, too - you can switch them to serial programming mode and change the bitstream without removing the EEPROM from the board. This can be done without any extra logic, just modifying the Xilinx design. Tomas Dulik In article <86k3gn$gmo$1@nntp5.atl.mindspring.net>, "Peter Fenn" <PeteFenn@mindspring.com> wrote: > Please advise: > Can Atmel AT17c256 be used in place of Xilinx XC17s20 config PROM? > > Regards > Peter Fenn > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20066
Hello, does anybody have the Synplify 5.1.4 eval version ? I have the 5.2.2 and 5.3.1, but don't like them - they both stopped working after 20 days :-) Tom Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20067
dulik@my-deja.com wrote: > Yes, you can use it - they behave the same way as XC17S20. And they > bring you the possibility of in system programming, too - you can > switch them to serial programming mode and change the bitstream without > removing the EEPROM from the board. This can be done without any extra > logic, just modifying the Xilinx design. I used these parts a couple of years ago & they were fine EXCEPT for one problem. The first byte of config data was only loaded into the serialiser on power-up and not every time RESET was asserted. In fact it was much worse than this since even a power cycle didn't always load the first byte correctly. Checking with Atmel I found that this was a known problem since the first byte is cached at power on, a new version of the device was supposed to fix it but it never came out while I was using the parts. You might be better off with the Xilinx XC1800 series parts that are ISP via JTAG.Article: 20068
Steve Bird wrote: > > In article <388e1f97.4722839@news.dial.pipex.com>, eml@riverside- > machines.com.NOSPAM writes > >Anyone managed this? I've tried modding the boot sector with a '95 > >boot disk and Debug, but Debug can't even see the C drive, let alone > >modify the boot sector. And does anyone know where the serial number > >is? Presumably the NTFS location is different from the FAT16 and FAT32 > >locations. > > > >By the way, this is (I think) legal. > > > > Depends on why you would want to do this... If you're trying to subvert > a s/w licensing schema (say FLEXlm) then its not. But if you buy a new (faster) PC, shouldn't they allow you to use your old software? And with FLEXlm you have to fiddle with the serial number (i.e., if you have a student license which has no support). It's not exactly legal, but they can't really object to this, since I bought the software and I want to keep on using it(?) Jo -- =======================< mailto:jdp@elis.rug.ac.be >======================= "How things look different on the way down", Cries on the Wind -- Anathema ====================< http://www.elis.rug.ac.be/~jdp >=====================Article: 20069
On Tue, 25 Jan 2000 20:32:46 -0800, John Larkin <jjlarkin@highlandSnipSniptechnology.com> wrote: > My testing indicates that the highest impedance a chip >pin sees is the via that reaches down from the pin to the power or >ground plane; the planes themselves (if the dielectric gap is small) >are very stiff for fast transients. Of course, if you need X colombs >of charge to keep your chip happy, you'd better have n*X farads >available somewhere to supply it. > >I think my point is that, for properly designed multilayer boards, the >planes themselves are an enormous asset in supplying low-impedance >power for fast transients. My TDR tests indicate that additional >bypass caps can be scattered about, and improve the apparent >capacitance a pin sees, without having to be really close to every >pin. We're obviously talking about two different things here. If you're discussing transmission lines, then yes, the planes provide great return paths, and your edge rate and via-crossing results are very interesting and useful. What's normally meant by 'decoupling' is the ability to provide lots of instantaneous current to your chip, quickly, without relying on a remote power supply, and this is the first-order problem. The critical word here is quickly - this means that capacitor placements, and values, are *critical*. There's a vast amount of literature on this. I've heard, second-hand, of one person who attempted to build a digital board without decoupling caps; he claimed the planes were enough. The description I had of him didn't include the word 'brave'. > I have never observed the multiple-resonances effects predicted >by the Sun paper Spice models for paralleled caps; I suspect they >didn't model the planes. I'm never observed it either, but the theory is simple enough. A real capacitor is a series LCR. Put two next to each other, add any extra inductance at the pads, and you're in trouble. Specifically, the 2 LCRs in parallel form a resonant tank circuit. I'm not sure how the planes can make any significant difference to this, apart from adding another minimum at very high frequencies. I've got a graph in front of me (from an old Cypress Hotlink appnote) plotting combined reactance from a parallel 22nF//100nF combination. This assumes that each cap has an ESR of 30mohm, and an ESL of 5nH, which they believe is "achievable on real PCBs using 'good' layouts and surface-mounted capacitors" (IIRC, you can probably reduce this to about 1nH with very careful cap selection and an impractical layout). The plot shows a reactance peak of over 100ohm at about 105MHz, which is not good. EvanArticle: 20070
On 25 Jan 2000 22:24:06 GMT, ldoolitt@recycle (Larry Doolittle) wrote: >One of these days Alliance will run on Linux, and I can stop >mooching off of another group's Sun. Roll on. ModelSim's on Linux now, and this probably means that Spectrum will have another go at Linux before long. At that point I can find out whether the 'Recycle Bin' can cope with \windoze... EvanArticle: 20071
1) Use XILINX Foundation Accessories -> Foundation Express to compile your VHDL files to XNF 2) Use Foundation Schematic Editor -> Hierarchy -> Create Macro Symbol from Netlist to create schematic symbol, based on XNF-file Steven Sanders wrote in message <388DA0C9.83D9D662@imec.be>... >Hello, > >I`m a newbie to the Xilinx Foundation Series. I have 5 VHDL files >(describing 5 components) >and I want to link these in a top file, but graphical! How do I make >symbols out of my VHDL code? > >Thanx > >Steven. >Article: 20072
On Wed, 26 Jan 2000 11:07:01 GMT, eml@riverside-machines.com.NOSPAM wrote: |On Tue, 25 Jan 2000 20:32:46 -0800, John Larkin |<jjlarkin@highlandSnipSniptechnology.com> wrote: | |> My testing indicates that the highest impedance a chip |>pin sees is the via that reaches down from the pin to the power or |>ground plane; the planes themselves (if the dielectric gap is small) |>are very stiff for fast transients. Of course, if you need X colombs |>of charge to keep your chip happy, you'd better have n*X farads |>available somewhere to supply it. |> |>I think my point is that, for properly designed multilayer boards, the |>planes themselves are an enormous asset in supplying low-impedance |>power for fast transients. My TDR tests indicate that additional |>bypass caps can be scattered about, and improve the apparent |>capacitance a pin sees, without having to be really close to every |>pin. | |We're obviously talking about two different things here. If you're |discussing transmission lines, then yes, the planes provide great |return paths, and your edge rate and via-crossing results are very |interesting and useful. | |What's normally meant by 'decoupling' is the ability to provide lots |of instantaneous current to your chip, quickly, without relying on a |remote power supply, and this is the first-order problem. The critical |word here is quickly - this means that capacitor placements, and |values, are *critical*. There's a vast amount of literature on this. |I've heard, second-hand, of one person who attempted to build a |digital board without decoupling caps; he claimed the planes were |enough. The description I had of him didn't include the word 'brave'. | |> I have never observed the multiple-resonances effects predicted |>by the Sun paper Spice models for paralleled caps; I suspect they |>didn't model the planes. | |I'm never observed it either, but the theory is simple enough. A real |capacitor is a series LCR. Put two next to each other, add any extra |inductance at the pads, and you're in trouble. Specifically, the 2 |LCRs in parallel form a resonant tank circuit. I'm not sure how the |planes can make any significant difference to this, apart from adding |another minimum at very high frequencies. I've got a graph in front of |me (from an old Cypress Hotlink appnote) plotting combined reactance |from a parallel 22nF//100nF combination. This assumes that each cap |has an ESR of 30mohm, and an ESL of 5nH, which they believe is |"achievable on real PCBs using 'good' layouts and surface-mounted |capacitors" (IIRC, you can probably reduce this to about 1nH with very |careful cap selection and an impractical layout). The plot shows a |reactance peak of over 100ohm at about 105MHz, which is not good. | |Evan Evan, to paraphrase an old saying, Spice is not Life. John ----------------- "If anybody ever marries you, it will be for the pleasure of hearing you talk piffle," said Harriet, severely.Article: 20073
Jo Depreitere wrote: > Steve Bird wrote: > > > > In article <388e1f97.4722839@news.dial.pipex.com>, eml@riverside- > > machines.com.NOSPAM writes > > >Anyone managed this? I've tried modding the boot sector with a '95 > > >boot disk and Debug, but Debug can't even see the C drive, let alone > > >modify the boot sector. And does anyone know where the serial number > > >is? Presumably the NTFS location is different from the FAT16 and FAT32 > > >locations. > > > > > >By the way, this is (I think) legal. > > > > > > > Depends on why you would want to do this... If you're trying to subvert > > a s/w licensing schema (say FLEXlm) then its not. > > But if you buy a new (faster) PC, shouldn't they allow you to use your > old software? And with FLEXlm you have to fiddle with the serial number > (i.e., if you have a student license which has no support). It's not > exactly legal, but they can't really object to this, since I bought > the software and I want to keep on using it(?) > > Jo > > -- > =======================< mailto:jdp@elis.rug.ac.be >======================= > "How things look different on the way down", Cries on the Wind -- Anathema > ====================< http://www.elis.rug.ac.be/~jdp >===================== Allow me to regurgitate my experience about this matter. I too wanted to upgrade my PC to a faster machine. A PII at 266 Mhz is a snail against a 700 Mhz Athlon. So I called up the FPGA vendor whose package I wanted to move. I was informed that for them to cut a license for a new machine would involve obtaining another license from the original vendor and the charges would be the same, in other words, I had to purchase a new package at full price. SO off I went to the net and search engines and found several packages that would allow me to change the serial number on the disk. I have not upgraded to another PC yet and have not fully researched the license agreement to see if there was some restriction about moving the software from one machine to another. What I have done is used the disk editor to changed the serial number on another NT drive. I would like to hear from software vendors who license their products using the host id. What is their position on moving the software to another machine. So the short answer is YES, one can change the serial number on disk drive that is used under the NT operating system. regards Jerry EnglishArticle: 20074
I am rather new to VHDL and FPGA. I want to hook a XC4005 using Xilinx Foundation 1.5 tools and talk to the FPGA through a 68HC11. Currently, I am taking a course in VHLD at UCI. Master/Slave arangement... Thanks Don Golding
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