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rk wrote:
>
> hi,
>
> i wish to publish some schematics for people to view on the www. before
> i start on this project, i thought i'd solicit some suggestions.
> currently i have a viewlogic license but haven't had the greatest luck
> with doing much with that wrt sharing schematics; perhaps i need to
> fiddle with it more. i also have veribest but haven't really explored
> that at all so perhaps someone with some experience has some ideas or
> thoughts.
>
> i could do .hgl (hp graphics language) output but not sure how readable
> that would be. usually when i import an .hgl into word it makes a mess.
>
> likewise, printing to .pdf has been far from successful.
>
> so,
>
> what's a portable way to share schematics here, approaching 2000, in the
> so-called information age? :-)
For viewing/printing I would prefer .pdf, .jpg or .gif.
If I had to *do* something with the schematic
I would prefer an .edf or .vhd netlist.
-Mike Treseler
Article: 18501Is there any place I can download exemplar_1164 package. Or, can somebody email this to package to. Any help would be greatly appreciated -- Haneef D. Mohammed Symphony EDA haneef@symphonyeda.comArticle: 18502
Output them as postscript. People can use GhostView to view/print them. rk <stellare@NOSPAM.erols.com> wrote in article <38176FB4.3C287AC7@NOSPAM.erols.com>... > hi, > > i wish to publish some schematics for people to view on the www. before > i start on this project, i thought i'd solicit some suggestions. > currently i have a viewlogic license but haven't had the greatest luck > with doing much with that wrt sharing schematics; perhaps i need to > fiddle with it more. i also have veribest but haven't really explored > that at all so perhaps someone with some experience has some ideas or > thoughts. > > i could do .hgl (hp graphics language) output but not sure how readable > that would be. usually when i import an .hgl into word it makes a mess. > > likewise, printing to .pdf has been far from successful. > > so, > > what's a portable way to share schematics here, approaching 2000, in the > so-called information age? :-) > > suggestions? > > rk > > > >Article: 18503
rk wrote: > > hi, > > i wish to publish some schematics for people to view on the www. before > i start on this project, i thought i'd solicit some suggestions. > currently i have a viewlogic license but haven't had the greatest luck > with doing much with that wrt sharing schematics; perhaps i need to > fiddle with it more. i also have veribest but haven't really explored > that at all so perhaps someone with some experience has some ideas or > thoughts. > > i could do .hgl (hp graphics language) output but not sure how readable > that would be. usually when i import an .hgl into word it makes a mess. > > likewise, printing to .pdf has been far from successful. > > so, > > what's a portable way to share schematics here, approaching 2000, in the > so-called information age? :-) > > suggestions? > > rk I use PDF for this purpose. I have noticed that PDF files of my Orcad schematics are not perfect. For example the resistors are made of lines that are a little too long. But they are very readable and can be printed in any size. A coworker (in another location) uses a Design Works and produces good PDF files that I have no trouble reading. When you say you have been far from successful using PDF, what sort of problems do you have? I don't think HGL files would be very useful. I don't think many viewers can read them and they are not even easy to print unless you have one of a handful of printers. I don't use postscript because my attempts at using Ghostview have not been very successful. I don't remember what problems I have with it, but I seem to recall that it crashed and I was never able to view a file. Likely an installation error. But that is the sort of problem I have with most applications I try to run that come from the Unix/Mac world. Mixing PCs and other computers just don't seem to work. The only way I have of viewing my coworker's PC board layouts is directly from the gerber files since he can't produce a PC readable graphic file with his software on the Mac. He says the file format is older than what can be read on the PC. I can't remember if he was talking about a TIF or a PIC file. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 18504
Graham Seaman (seamang@westminster.ac.uk) wrote:
: If you want a working (but bare - no gui!) VHDL93 simulator for Linux
: (or any Unix, since its under LGPL and so comes with source) you could
: try Savant: http://www.ececs.uc.edu/~paw/savant/
: There are rpm and deb packages.
: There's a longer list of open source design tools at
: http://collector.hscs.wmin.ac.uk Unfortunately, plenty for data entry and
: simulation, nothing for synthesis (yet...)
Synthesis? How about Icarus Verilog. It's definitely a work-in-progress,
but it is progressing :-). And it works for me.
http://www.geda.seul.org/
- Larry Doolittle <LRDoolittle@lbl.gov>
Article: 18505
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Ilia Oussorov wrote:
> Hi friends.
>
> I use Virtex device and software Xilinx aliance2.1i and Leonardo.
> I have bidirectional buses in my design (see figure). The control logic
>
> of design never leave both T-buffers open. But if i try to implement the
>
> design, xilinx place and route takes a very
> long time. And than it says "timing constraints could not be met". I
> think that the tool assume infinite loop in design. If I do 2
> unidirectional buses the implementation takes a very short time. Is it
> possible to
> say to the tool to do not execute loops analyze?
> How can I solve this problem?
> I don't like to do 2 unidirectional buses from one bi-directional but I
> can't wait 2 hours until the design will be implemented.
> P.S. The design works after mentioned implementation also in hardware
> properly
>
> uc_dc(7 downto 0) <= uc_d(7 downto 0) when re = '1' else (others =>
> 'Z');
> uc_d(7 downto 0) <= uc_dc(7 downto 0) when we = '1' else (others =>
> 'Z');
>
> /-------<Tbuf------\
> / \
> <>-----/------Tbuf>------------\------<>-----
>
> Best regards,
Hi Ilia,
some years ago we had the same problem when synthesizing with Mentor's
Autologic II. We solved with two unidirectional busses, both with the same
name. After synthesis it was implemented as bidirectional bus.
Just try it !!!
Hope this helps.
Davor
--
----------------------------------------------
Davor Lukacic
mailto:Davor.Lukacic@bosch.com
----------------------------------------------
Robert Bosch GmbH Reutlingen, Dep. K8/EIC2
Development of Integrated Bipolar/MOS Asics
P.O. Box 1342, D-72703 Reutlingen
Tel: ++49-7121-35-4100
Fax: ++49-7121-35-2880
----------------------------------------------
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<html>
Ilia Oussorov wrote:
<blockquote TYPE=CITE>Hi friends.
<p>I use Virtex device and software Xilinx aliance2.1i and Leonardo.
<br>I have bidirectional buses in my design (see figure). The control
logic
<p>of design never leave both T-buffers open. But if i try to implement
the
<p>design, xilinx place and route takes a very
<br>long time. And than it says "timing constraints could not be met".
I
<br>think that the tool assume infinite loop in design. If I do 2
<br>unidirectional buses the implementation takes a very short time. Is
it
<br>possible to
<br>say to the tool to do not execute loops analyze?
<br>How can I solve this problem?
<br>I don't like to do 2 unidirectional buses from one bi-directional but
I
<br>can't wait 2 hours until the design will be implemented.
<br>P.S. The design works after mentioned implementation also
in hardware
<br>properly
<p> uc_dc(7 downto 0) <= uc_d(7 downto 0) when re = '1' else (others
=>
<br>'Z');
<br> uc_d(7 downto 0) <= uc_dc(7 downto 0) when we = '1' else
(others =>
<br>'Z');
<p> /-------<Tbuf------\
<br> /
\
<br><>-----/------Tbuf>------------\------<>-----
<p>Best regards,</blockquote>
Hi Ilia,
<p>some years ago we had the same problem when synthesizing with Mentor's
Autologic II. We solved with two unidirectional busses, both with the same
name. After synthesis it was implemented as bidirectional bus.
<br>Just try it !!!
<p>Hope this helps.
<p>Davor
<pre>--
----------------------------------------------
Davor Lukacic
<A HREF="mailto:Davor.Lukacic@bosch.com">mailto:Davor.Lukacic@bosch.com</A>
----------------------------------------------
Robert Bosch GmbH Reutlingen, Dep. K8/EIC2
Development of Integrated Bipolar/MOS Asics
P.O. Box 1342, D-72703 Reutlingen
Tel: ++49-7121-35-4100
Fax: ++49-7121-35-2880
----------------------------------------------</pre>
</html>
--------------593177EBB3B3734CF40EFE34--
Article: 18506Does anybody now how I can get the hold time requirement between an external pin and an internal Flip-Flop ? I want to make sure that my PCI logic meets the 0-hold-time requirement. For Virtex there are pin-to-pin values in the data sheet but they only apply to IOB FFs. As far as I can see the only way to check this is via a post-route simulation with a min delay SDF hacked to set the PCICLK delay to max. BTW: In the latest BitGen documentation it appears to be possible to put a delay on the GClks but your are told to do this only under instructions from Xilinx. Has anybody worked out how to use them ?Article: 18507
I now have a copy. thanx.... Haneef D. Mohammed <haneef@mindspring.com> wrote in message news:7v8394$ecd$1@nntp3.atl.mindspring.net... > Is there any place I can download exemplar_1164 package. > Or, can somebody email this to package to. > Any help would be greatly appreciated > > -- > > Haneef D. Mohammed > Symphony EDA > haneef@symphonyeda.com > >Article: 18508
Haneef D. Mohammed wrote: > > Is there any place I can download exemplar_1164 package. > Or, can somebody email this to package to. > Any help would be greatly appreciated > > -- > > Haneef D. Mohammed > Symphony EDA > haneef@symphonyeda.com It comes free when you buy Leonardo Spectrum. Other than that, I am sure it is copyrighted, and thus would be illegal for anyone to give to you. -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 18509
Rick Filipkiewicz wrote: > > Does anybody now how I can get the hold time requirement between an > external pin and an internal Flip-Flop ? > I want to make sure that my PCI logic meets the 0-hold-time requirement. > > For Virtex there are pin-to-pin values in the data sheet but they only > apply to IOB FFs. As far as I can see the only way to check this is via > a post-route simulation with a min delay SDF hacked to set the PCICLK > delay to max. > > BTW: In the latest BitGen documentation it appears to be possible to put > a delay on the GClks but your are told to do this only under > instructions from Xilinx. Has anybody worked out how to use them ? If I can ask the obvious question, why don't you use the IOB FF so that you know the hold time? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 18510
--------------91B780A42659A2B7E6A2C0EA Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Brian Boorman wrote: > Haneef D. Mohammed wrote: > > > > Is there any place I can download exemplar_1164 package. > > Or, can somebody email this to package to. > > Any help would be greatly appreciated > > > > -- > > > > Haneef D. Mohammed > > Symphony EDA > > haneef@symphonyeda.com > > It comes free when you buy Leonardo Spectrum. > > Other than that, I am sure it is copyrighted, and thus would be illegal > for anyone to give to you. > > -- > Brian C. Boorman > Harris RF Communications > Rochester, NY 14610 > XYZ.bboorman@harris.com > <Remove the XYZ. for valid address> take a look at his !!!! ;-))))))) any questions ? ------------------------------------------------------------------------ ----------------------------------------------------------------------- -- -- Copyright (c) 1992, 1993, 1994, Exemplar Logic, Inc. All rights reserved -- -- This file is owned by Exemplar Logic Inc. It can be used without -- restrictions as long as this header remains attached. -- -- Package : exemplar_1164 -- -- Version : 2.1.3 -- -- Purpose : Definition of package exemplar_1164. -- Functions, procedures and operators that provide often -- needed functionality for the IEEE 1164 standard -- STD_LOGIC, STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR -- types are defined in this package, for general use. -- Also attributes are defined that have pre-defined -- semantics in CORE. -- If the package exemplar_1164 is used in a VHDL description, -- this file provides the simulation models. -- -- ------------------------------------------------------------------------ ------------------------------------------------------------------------ --------------91B780A42659A2B7E6A2C0EA Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Brian Boorman wrote: <blockquote TYPE=CITE>Haneef D. Mohammed wrote: <br>> <br>> Is there any place I can download exemplar_1164 package. <br>> Or, can somebody email this to package to. <br>> Any help would be greatly appreciated <br>> <br>> -- <br>> <br>> Haneef D. Mohammed <br>> Symphony EDA <br>> haneef@symphonyeda.com <p>It comes free when you buy Leonardo Spectrum. <p>Other than that, I am sure it is copyrighted, and thus would be illegal <br>for anyone to give to you. <p>-- <br>Brian C. Boorman <br>Harris RF Communications <br>Rochester, NY 14610 <br>XYZ.bboorman@harris.com <br><Remove the XYZ. for valid address></blockquote> <p><br>take a look at his !!!! ;-))))))) any questions ? <br> <p>------------------------------------------------------------------------ <br>----------------------------------------------------------------------- <br>-- <br>-- Copyright (c) 1992, 1993, 1994, Exemplar Logic, Inc. All rights reserved <br>-- <br>-- This file is owned by Exemplar Logic Inc. It can be used without <br>-- restrictions as long as this header remains attached. <br>-- <br>-- Package : exemplar_1164 <br>-- <br>-- Version : 2.1.3 <br>-- <br>-- Purpose : Definition of package exemplar_1164. <br>-- Functions, procedures and operators that provide often <br>-- needed functionality for the IEEE 1164 standard <br>-- STD_LOGIC, STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR <br>-- types are defined in this package, for general use. <br>-- Also attributes are defined that have pre-defined <br>-- semantics in CORE. <br>-- If the package exemplar_1164 is used in a VHDL description, <br>-- this file provides the simulation models. <br>-- <br>-- <br>------------------------------------------------------------------------ <br>------------------------------------------------------------------------ <br> <br> <pre></pre> </html> --------------91B780A42659A2B7E6A2C0EA--Article: 18511
> I don't use postscript because my attempts at using Ghostview have not > been very successful. I don't remember what problems I have with it, but > I seem to recall that it crashed and I was never able to view a file. > Likely an installation error. But that is the sort of problem I have > with most applications I try to run that come from the Unix/Mac world. Just a note in 'defense' of GhostView...I've never had any problems with it, and find it a VASTLY useful (must have) utility...I run it under NT 4.0. I can't vouch for anything under W95. GhostView is available at: http://www.cs.wisc.edu/~ghost/gsview/ I also use a Windows version of EMacs, and it works flawlessly too...it is available at: http://www.cs.washington.edu/homes/voelker/ntemacs.html and the spell checker: http://mohawk.cat.rpi.edu/~tibbetts/ispell_toc.htmlArticle: 18512
Hi; I would like to generate a signal with 3/4 period high and 1/4 period low. The clock runs at 80MHz. I tried to use 270 degree shift output of DLLs but still no luck. Any idea how may I implement that? Regards; Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18513
Big architectural differences. Which is best depends on your application. For signal processing, Xilinx is a hands down winner. For other apps, the Altera is better. Look for my previous posts on this subject in deja-news for more details. Child K.L. Sun wrote: > Have you tried both of the chips/software from these two > companies? > What's the difference between them? > > Child -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18514
check IEEE and ACM conference proceedings - specifically look at FCCM, FPGA, RAW conferences. THere are periodically papers on fault tolerant FPGAs there. Andreas Kröpfl wrote: > HI > > This are Andreas Kropfl kroepfl@iti.tu-graz.ac.at and Dieter Leiler > leiler@sbox.tu-graz.ac.at. We are diplomand students at the technical > university of Graz and search for literature concerning FPGAs > > Perhaps someone can help us in one of the following points. > * MAIN PROBLEM : failure tollerance in reconfigurable FPGAs > * introducing material concerning the development of FPGA ( summaries about > the work on FPGAs ) > * state-of-the-art articles ... a.s.o. > > It would rather be interesting to get more literature via email (.doc, .ps, > ..) , some other email-adresses from people, who are working on the same > topic. Finally some homepages for better understanding can be a great help. > > Thank you for your help ! > Greatings from Graz > > ------------------------------------------------------------------------ > ------ > Dipl.-Ing. Andreas R. Kroepfl - research assistent > Institut f. Technische Informatik - TU Graz > Inffeldg. 16/1 > 8010 Graz > Austria > > Tel.Nr.: +43 +316 873 6411 > Fax.Nr.: +43 +316 873 6903 > E-Mail: kroepfl@i.am > Homepage: http://kroepfl.i.am > ------------------------------------------------------------------------ > ------ > > ------------------------------------------------------------------------ > ------ > Dieter Leiler - diploma student > Institut f. Technische Informatik - TU Graz > Inffeldg. 16/1 > 8010 Graz > Austria > > Tel.Nr.: +43 +316 873 6411 > Fax.Nr.: +43 +316 873 6903 > E-Mail: leiler@iti.tu-graz.ac.at > ------------------------------------------------------------------------ > ------ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18515
Rich, If you have WVO 7.5 and adobe acrobat exchange, you can print to the acrobat distiller to get the schematics in pdf format. rk wrote: > hi, > > i wish to publish some schematics for people to view on the www. before > i start on this project, i thought i'd solicit some suggestions. > currently i have a viewlogic license but haven't had the greatest luck > with doing much with that wrt sharing schematics; perhaps i need to > fiddle with it more. i also have veribest but haven't really explored > that at all so perhaps someone with some experience has some ideas or > thoughts. > > i could do .hgl (hp graphics language) output but not sure how readable > that would be. usually when i import an .hgl into word it makes a mess. > > likewise, printing to .pdf has been far from successful. > > so, > > what's a portable way to share schematics here, approaching 2000, in the > so-called information age? :-) > > suggestions? > > rk -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18516
One extra note regarding pdf. You need to print to the distiller, not to pdfwriter. The graphics are too complicated for pdfwriter. Using PDFwriter will make a mess of things-missing lines, wrong length lines, random scaling and things like that. I've had good success printing to pdf as long as I use the distiller as the printer. rk wrote: > hi, > > i wish to publish some schematics for people to view on the www. before > i start on this project, i thought i'd solicit some suggestions. > currently i have a viewlogic license but haven't had the greatest luck > with doing much with that wrt sharing schematics; perhaps i need to > fiddle with it more. i also have veribest but haven't really explored > that at all so perhaps someone with some experience has some ideas or > thoughts. > > i could do .hgl (hp graphics language) output but not sure how readable > that would be. usually when i import an .hgl into word it makes a mess. > > likewise, printing to .pdf has been far from successful. > > so, > > what's a portable way to share schematics here, approaching 2000, in the > so-called information age? :-) > > suggestions? > > rk -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18517
On 23 Oct 1999 01:33:22 GMT, "Austin Franklin" <austin@darkr00m.com>
wrote:
>OR better yet, why they don't have either an Adobe Acrobat (preferred) or
>PostScript printable and legible document for each package/die combination.
> It gets VERY tedious making these for the new Virtex chips....
don't forget that FPGA editor now has postscript output, although the
print option seems to be greyed out for the larger devices:
fpga editor -> file/new -> select part, with dummy design name -> turn
on text ('A' box) -> print.
next question: how is it possible to get legible output for a large
device? you need a *very* large printer. i've also tried file output,
and post-processing with ghostscript/gsview, but no luck so far.
evan
Article: 18518
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Alexander Krebs wrote:
> Hi,
>
> Does anybody know why Xilinx switched to not generating the object code
> for
> fast VSS simulation for all the simulation libraries? Until version 1.4
> the
> call of the VHDL compiler in their analyze.csh files looked like
>
> vhdlan -c -optimize -w ...
>
> Starting with version 1.5 it is
>
> vhdlan -i -w ...
>
> I changed their scripts back to the "-c" version because it should give
> us much
> shorter simulation times. It seems to work. Are there any drawbacks?
>
> Thanx for your help in advance!
>
> Alex.
>
> --
Hello Alex,
in (VSS) release note (version 1998.08) you can find the following
VHDL- Simulator : Compiled Mode
48202 Compiled Simulation needs twice as much time as
interpreted simulation
Maybe that was the reason.
Jörg
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Alexander Krebs wrote:
<blockquote TYPE=CITE>Hi,
<p>Does anybody know why Xilinx switched to not generating the object code
<br>for
<br>fast VSS simulation for all the simulation libraries? Until version
1.4
<br>the
<br>call of the VHDL compiler in their analyze.csh files looked like
<p>vhdlan -c -optimize -w ...
<p>Starting with version 1.5 it is
<p>vhdlan -i -w ...
<p>I changed their scripts back to the "-c" version because it should give
<br>us much
<br>shorter simulation times. It seems to work. Are there any drawbacks?
<p>Thanx for your help in advance!
<p>Alex.
<p>--</blockquote>
Hello Alex,
<br>in (VSS) release note (version 1998.08) you can find the following
<blockquote>VHDL- Simulator : Compiled Mode
<br>48202 Compiled Simulation needs twice as much time
as interpreted simulation</blockquote>
Maybe that was the reason.
<p>Jörg
<br> </html>
--------------277048289855562EB057FCFC--
Article: 18519:)Article: 18520
Rickman wrote:rnal Flip-Flop ? > If I can ask the obvious question, why don't you use the IOB FF so that > you know the hold time? > > -- > > Rick Collins > > rick.collins@XYarius.com > > I found that when designing a PCI interface I couldn't get it going at the full burst rate of 1 word/clock unless I could feed the PCI control inputs direct from the pins into the master/target state machines. So the inputs go to more than 1 register bit.. Maybe I wasn't doing it right but if I registered all the inputs in the IOBs the fastest I could go was 1 every 2 clocks without the state machines getting into a tangle of special cases.Article: 18521
I've had to wrtestle with this problem from time to time myself, and have not found anything that works better than either PCX or BMP format, so long as your intended audience uses Win9x, which provides handlers for those formats. Several schematic/PCB packages have HPGL viewers, i.e. allow importation of HPGL drawings, but I've not found a schematic capture package for Windows that satisfies my requirements, so I still use a 10-year old DOS-based one (OrCAD), which, by the way, doesn't import HPGL, but their PCB package does. It's not perfect, by any means, however, as text often gets muddled to where it can't be read. If you find a solution, please share it with me. thanx Dick On Wed, 27 Oct 1999 17:33:41 -0400, rk <stellare@NOSPAM.erols.com> wrote: >hi, > >i wish to publish some schematics for people to view on the www. before >i start on this project, i thought i'd solicit some suggestions. >currently i have a viewlogic license but haven't had the greatest luck >with doing much with that wrt sharing schematics; perhaps i need to >fiddle with it more. i also have veribest but haven't really explored >that at all so perhaps someone with some experience has some ideas or >thoughts. > >i could do .hgl (hp graphics language) output but not sure how readable >that would be. usually when i import an .hgl into word it makes a mess. > >likewise, printing to .pdf has been far from successful. > >so, > >what's a portable way to share schematics here, approaching 2000, in the >so-called information age? :-) > >suggestions? > >rk > > >Article: 18522
In article <38186192.C5198DD1@ids.net>, Ray Andraka <randraka@ids.net> wrote: >Big architectural differences. Which is best depends on your >application. For signal processing, Xilinx is a hands down winner. For >other apps, the Altera is better. Look for my previous posts on this >subject in deja-news for more details. OH! I dissagree! Xilinx is the hands down winner in far more applications than "just" signal processing. :-) Then again, you (or I) might say that all applications are "signal processing" of one type or another. Philip > >Child K.L. Sun wrote: > >> Have you tried both of the chips/software from these two >> companies? >> What's the difference between them? >> >> Child > > > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > >Article: 18523
Hey there, First you go here: http://www.gotoworld.com/getpaid/default.asp?rid=1026073826 download the browser, read the instructions and get paid just for browsing. You will see a little windows with ads changing at the top of the browser, but that's all to it. Start browsing now and it'll help you cover your Internet service provider expenses and make a few extra bucks. Thanks for your time, MMArticle: 18524
--------------AE71497BB4F3E69C6A10E0EF Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit hi, you may also wish to take a look at mapld '99 which covers this topic ... ... from session d: http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/ProgramSessions/Session_D.html Abstract: http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/lach.pdf Abstract: http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/lach.ps John Lach UCLA Electrical Engineering Department D3: "Runtime Logic and Interconnect Fault Recovery on Diverse FPGA Architectures" Abstract: http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/doumar.pdf Abstract: http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/doumar.ps Abderrahim Doumar Graduate School of Science and Technology Chiba University D4: "Fault Tolerant FPGAs by Shifting the Configuration Data" hope this helps, rk ==================================================== Ray Andraka wrote: > check IEEE and ACM conference proceedings - specifically look at FCCM, FPGA, > RAW conferences. THere are periodically papers on fault tolerant FPGAs there. > > Andreas Kröpfl wrote: > > > HI > > > > This are Andreas Kropfl kroepfl@iti.tu-graz.ac.at and Dieter Leiler > > leiler@sbox.tu-graz.ac.at. We are diplomand students at the technical > > university of Graz and search for literature concerning FPGAs > > > > Perhaps someone can help us in one of the following points. > > * MAIN PROBLEM : failure tollerance in reconfigurable FPGAs > > * introducing material concerning the development of FPGA ( summaries about > > the work on FPGAs ) > > * state-of-the-art articles ... a.s.o. > > > > It would rather be interesting to get more literature via email (.doc, .ps, > > ..) , some other email-adresses from people, who are working on the same > > topic. Finally some homepages for better understanding can be a great help. > > > > Thank you for your help ! > > Greatings from Graz > > > > ------------------------------------------------------------------------ > > ------ > > Dipl.-Ing. Andreas R. Kroepfl - research assistent > > Institut f. Technische Informatik - TU Graz > > Inffeldg. 16/1 > > 8010 Graz > > Austria > > > > Tel.Nr.: +43 +316 873 6411 > > Fax.Nr.: +43 +316 873 6903 > > E-Mail: kroepfl@i.am > > Homepage: http://kroepfl.i.am > > ------------------------------------------------------------------------ > > ------ > > > > ------------------------------------------------------------------------ > > ------ > > Dieter Leiler - diploma student > > Institut f. Technische Informatik - TU Graz > > Inffeldg. 16/1 > > 8010 Graz > > Austria > > > > Tel.Nr.: +43 +316 873 6411 > > Fax.Nr.: +43 +316 873 6903 > > E-Mail: leiler@iti.tu-graz.ac.at > > ------------------------------------------------------------------------ > > ------ > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka --------------AE71497BB4F3E69C6A10E0EF Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> hi, <P>you may also wish to take a look at mapld '99 which covers this topic ... <P>... from session d:<A HREF="http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/ProgramSessions/Session_D.html"></A> <P><A HREF="http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/ProgramSessions/Session_D.html">http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/ProgramSessions/Session_D.html</A> <P>Abstract: <A HREF="http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/lach.pdf">http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/lach.pdf</A> <BR>Abstract: <A HREF="http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/lach.ps">http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/lach.ps</A> <BR>John Lach <BR>UCLA Electrical Engineering Department <BR>D3: "Runtime Logic and Interconnect Fault Recovery on Diverse FPGA Architectures" <P>Abstract: <A HREF="http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/doumar.pdf">http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/doumar.pdf</A> <BR>Abstract: <A HREF="http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/doumar.ps">http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Abstracts/doumar.ps</A> <BR>Abderrahim Doumar <BR>Graduate School of Science and Technology <BR>Chiba University <BR>D4: "Fault Tolerant FPGAs by Shifting the Configuration Data" <P>hope this helps, <P>rk <P>==================================================== <P>Ray Andraka wrote: <BLOCKQUOTE TYPE=CITE>check IEEE and ACM conference proceedings - specifically look at FCCM, FPGA, <BR>RAW conferences. THere are periodically papers on fault tolerant FPGAs there. <P>Andreas Kröpfl wrote: <P>> HI <BR>> <BR>> This are Andreas Kropfl kroepfl@iti.tu-graz.ac.at and Dieter Leiler <BR>> leiler@sbox.tu-graz.ac.at. We are diplomand students at the technical <BR>> university of Graz and search for literature concerning FPGAs <BR>> <BR>> Perhaps someone can help us in one of the following points. <BR>> * MAIN PROBLEM : failure tollerance in reconfigurable FPGAs <BR>> * introducing material concerning the development of FPGA ( summaries about <BR>> the work on FPGAs ) <BR>> * state-of-the-art articles ... a.s.o. <BR>> <BR>> It would rather be interesting to get more literature via email (.doc, .ps, <BR>> ..) , some other email-adresses from people, who are working on the same <BR>> topic. Finally some homepages for better understanding can be a great help. <BR>> <BR>> Thank you for your help ! <BR>> Greatings from Graz <BR>> <BR>> ------------------------------------------------------------------------ <BR>> ------ <BR>> Dipl.-Ing. Andreas R. Kroepfl - research assistent <BR>> Institut f. Technische Informatik - TU Graz <BR>> Inffeldg. 16/1 <BR>> 8010 Graz <BR>> Austria <BR>> <BR>> Tel.Nr.: +43 +316 873 6411 <BR>> Fax.Nr.: +43 +316 873 6903 <BR>> E-Mail: kroepfl@i.am <BR>> Homepage: <A HREF="http://kroepfl.i.am">http://kroepfl.i.am</A> <BR>> ------------------------------------------------------------------------ <BR>> ------ <BR>> <BR>> ------------------------------------------------------------------------ <BR>> ------ <BR>> Dieter Leiler - diploma student <BR>> Institut f. Technische Informatik - TU Graz <BR>> Inffeldg. 16/1 <BR>> 8010 Graz <BR>> Austria <BR>> <BR>> Tel.Nr.: +43 +316 873 6411 <BR>> Fax.Nr.: +43 +316 873 6903 <BR>> E-Mail: leiler@iti.tu-graz.ac.at <BR>> ------------------------------------------------------------------------ <BR>> ------ <P>-- <BR>-Ray Andraka, P.E. <BR>President, the Andraka Consulting Group, Inc. <BR>401/884-7930 Fax 401/884-7950 <BR>email randraka@ids.net <BR><A HREF="http://users.ids.net/~randraka">http://users.ids.net/~randraka</A></BLOCKQUOTE> </HTML> --------------AE71497BB4F3E69C6A10E0EF--
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