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Kostas wrote: > I've tried to solve an issue some > time ago, and the synopsys attitude > was, that since xilinx oem-bundles > their product with their tools, > they don't want to know anything > about these user requests. Interesting contrast with Synplicity who, as reported here a couple of months ago, were courteous and responsive in dealing with a Synplify licence problem in my **FREE** Actel software. Are "market leader" and "arrogant" on the same page in _your_ thesaurus? Jonathan BromleyArticle: 18076
Ray Andraka <randraka@ids.net> wrote in message > What is the availability? I've got a current customer that could use higher > density than the XCV1000, but he needs it today. XCV300E and XCV1000E should be available NOW in some packages, with XCV2000E and XCV600E to follow VERY soon. I suggest you contact your distributor for more detailed information. For those interested in learning more about Virtex-E, I suggest the following reading: Press release at: http://www.xilinx.com/prs_rls/vtxe.htm Virtex-E FAQ at: http://www.xilinx.com/prs_rls/vtxefaq.htm Technical Backgrounder at: http://www.xilinx.com/prs_rls/vtxebkgdr.htm More product info at: http://www.xilinx.com/products/virtex.htm Virtex-E datasheet: http://www.xilinx.com/partinfo/databook.htm#virtex New appnotes at: http://www.xilinx.com/apps/virtexapp.htm One of the application notes discusses one of the most exciting features (and until now - the best kept secret) about the Virtex-E: The support for 622Mbps LVDS. Also make sure you read about the SelectLink feature which offers extremely high Virtex-to-Virtex data rates, the DLLs (of which there are now 8) which eases system design greatly, more I/O standards, support for 200MHz ZBT RAM and SDRAM, more memory, and lots of more... Regards, Rune BaeverrudArticle: 18077
Jonathan Bromley wrote: > Kostas wrote: > > > I've tried to solve an issue some > > time ago, and the synopsys attitude > > was, that since xilinx oem-bundles > > their product with their tools, > > they don't want to know anything > > about these user requests. > > Interesting contrast with Synplicity who, as reported > here a couple of months ago, were courteous and > responsive in dealing with a Synplify licence > problem in my **FREE** Actel software. > > Are "market leader" and "arrogant" on the > same page in _your_ thesaurus? > > Jonathan Bromley I too had this problem since I wanted, among other things, more documenation on the Tcl scripting in FPGA-E 3.1 since the on line help for this is appallingly thin. The stuff I needed was on Synopsys' site but I couldn't download without a user ID & passwd I too was told that OEM customers have no access to to Solve-NET and should ``contact their distributor''. The Xilinx FAE managed to get most of the stuff but I still haven't got any info on the synthesis control Tcl commands. As a result we made the excellent decision to buy Synplify in spite of FPGA Express being FREE with Foundation. So far, in spite of my unusual ability to generate bugs in all known forms of s/w, I have found only 1 in Synplify which they admitted without the usual attempt to blame the user.Article: 18078
Rune Baeverrud wrote: > - Based on the 0.18 µm, 6LM process vs. a 0.25 µm 5LM process for Virtex > - Over 3x density increase (from 1 million to 3.2 million system gates) > - 1.3x speed grade performance > - Over 1.5x number of user I/Os (from 512 to 804) > - Over 1.5x I/O performance (from 200 MHz to over 311 MHz) > - 6.5x the internal block memory (from 128 Kbits to 832 Kbits) > - 2x the number of DLLs (from 4DLLs to 8 DLLs) > - Available with more advanced fine pitch packaging (FG860, FG900, and > FG1156) support bringing the max I/O count up to 804 > - Support three differential I/O standards: LVDS, Bus LVDS, and LVPECL (from > supporting 17 I/O standards to 20 I/O standards) > - Capable of delivering 622 Megabits per second (Mbps) differential I/O > performance > > There are press releases, datasheets and new application notes available at: > > http://www.xilinx.com > > Enjoy! > > Best Regards, > Rune Baeverrud Yeah so why doesn't M2.1i support them without a special plea to your distributor.Article: 18079
ðÒÏÄÁÍ ÍÉËÒÏÓÈÅÍÙ ÆÉÒÍÙ ALTERA EPM9320LI84-20 - 20$ EPM9320RC208-15 - 25$ Ï ÐÒÅÄÌÏÖÅÎÉÑÈ ÓÏÏÂÝÁÔØ ÎÁ e-mail: oleg@uniirt.com.uaArticle: 18080
Thank you all, Can you please advise for another manufacturer other then atmel. Keren Dave Vanden Bout <devb@xess.com> wrote in message news:37EED72B.3AA6322A@xess.com... > Try one of the Atmel 17C*** eeproms if they are big enough to hold your bitstream. > > Keren wrote: > > > Hello, > > > > I am looking for a substitut component for the XC17*** PROM by Xilinx. > > * Flash Memory or EEMemory > > * ISP Programing thrugh JTag. > > > > Thank you > > > > Keren >Article: 18081
TESTArticle: 18082
TESTArticle: 18083
Hello, I have been teaching myself about FPGAs using Xilinx Foundation Series 1.5. I would like to get a textbook on VHDL to learn with also. Is there any consensus as to which is better to learn, Verilog or VHSIC HDL ? I have heard that they are both widely used, but verilog is easier. Also, dose anyone know where I can get a used text on this subject in the St. Pete area of Florida ? Thanks in advance. -NickArticle: 18084
In article <37EF17A6.3F177E43@crl.co.uk>, Stephen King <sking@crl.co.uk> wrote: > I am interested to know if any one has used the LVDS IO on the 20KE? If > so what are your experiences with it and where can I get hold of > detailed timing and electrical specifications? (They have yet to be > included in the 20K data sheet.) I can't offer Altera specific information, but LVDS is a standard and you can get all you need to know about it either from National Semiconductor or Texas Instruments web sites; (do a search on LVDS). > My interest is in the possibility of using the LVDS IO for direct input > from a 500 MSPS ADC with LVDS output. I'm curious to know who makes this. Jacob Hirbawi Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18085
Has anyone tried the Lucent FPGA with integrated PCI hard core? They call it an FPSC, and apparently, they've hard-wired a PCI core into their FPGA parts, so you only need to develop the application part of the device (in the FPGA section). I found this part at: http://www.lucent.com/micro/fpga/fpsc.html I'm considering this part for a project I'm starting, and would like to hear from anybody who has used it. -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.eduArticle: 18086
Make a $6 investment into $6,000 in a month! INTEGRITY CAN
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back, I was browsing through newsgroups, just like you are now, and
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$6.00! So I thought," Yeah, right, this must be a scam", but like most
of us, I was curious, so I kept reading. Anyway, it said that you send
$1.00 to each of the 6 names and address stated in the article. You
then place your own name and address in the bottom of the list at
#6, and post the article in at least 200 newsgroups. (There are
thousands) No catch, that was it. So after thinking it over, and
talking to a few people first, I thought about trying it. I figured what
have I got to lose except 6 stamps and $6.00, right? Like most of us
I was a little skeptical and a little worried about the legal aspects of it
all. So I checked it out with the U.S. Post Office (1-800-725-2161)
and they confirmed that it is indeed legal! Then I invested the
measly $6.00. Well GUESS WHAT!!...within 7 days, I started getting
money in the mail! I was shocked! I figured it would end soon, but
the money just kept coming in. In my first week, I made about
$25.00. By the end of the second week I had made a total of over
$1,000.00! In the third week I had over $10,000.00 and it's still
growing. This is now my fourth week and I have made a total of just
over $42,000.00 and it's still coming in rapidly. It's certainly worth
$6.00, and 6 stamps, I have spent more than that on the lottery!!
Let me tell you how this works and most importantly, why it
works....also, make sure you print a copy of this article NOW, so you
can get the information off of it as you need it. STEP 1): Get 6
separate pieces of paper and write the following on each piece of
paper "PLEASE PUT ME ON YOUR MAILING LISTS". THIS HELPS
TO ENSURE THAT YOU WILL BE GETTING MORE RESPONSES BY
PEOPLE THAT ARE DOING THE SAME THING AS YOU. Now get 6
US $1.00 bills and place ONE inside EACH of the 6 pieces of paper
so the bill will not be seen through the envelope to prevent thievery.
Next, place one paper in each of the 6 envelopes and seal them.
You should now have 6 sealed envelopes, each with a piece of
paper stating the above phrase, your name and address, and a
$1.00 bill. What you are doing is creating a service by this. THIS IS
ABSOLUTELY LEGAL! Mail the 6 envelopes to the following
addresses:
1) Marcus Douglas, 12520 McKinnon Dr., Laurinburg, NC 28352
2) Jeremy Smith, P.O. Box 32, Pegram, TN 37143
3) Edith Bukenya, 6814 East Main street, Eau Claire, MI 49111
4) Jenny Chow, P.O. Box 901, Lodi, CA 95241
5) Allen Pearson, 403 W. Pearl Ave. Stockton, CA 95207
6) Dominic Maida P.O. Box 216 Sumner, Wa. 98390
STEP 2) Now take the #1 name off the list that you see above, move
the other names up (6 becomes 5, 5 becomes 4, etc...) and add
YOUR NAME as number 6 on the list. STEP 3): Change anything
you need to, but try to keep this article as close to the original as
possible! Now, post your amended article to at least 200
newsgroups. (I think there are close to 24,000 groups) All you need
is 200, but remember, the more you post, the more money you
make! ---DIRECTIONS-----HOW TO POST TO
NEWSGROUPS------------ STEP 1): You do not need to re-type this
entire letter to do your own posting. Simply put your cursor at the
beginning of this letter and drag your cursor to the bottom of this
letter, and select 'copy' from the 'edit' menu. This will copy the entire
letter into the computers memory. STEP 2): Open a new(or blank)
'WordPad' or 'Notepad' file and place your cursor at the top of the
blank page. From the 'edit' menu select 'paste'. This will paste a
copy of the letter into your word processor so that you can add your
name to the list. STEP 3): Save your new notepad file as a .txt file. If
you want to do your postings in different sittings, you'll always have
this file to go back to. STEP 4): Use Netscape or Internet explorer
and try searching for various newsgroups (on-line forums, message
boards, chat sites, discussions). STEP 5): Visit these message
boards and post this article as a new message by highlighting the
text of this letter and selecting paste from the edit menu. Fill in the
Subject, this will be the header that everyone sees as they scroll
through the list of postings in a particular group, click the post
message button. You're done with your first one!
Congratulations...THAT'S IT! All you have to do is jump to different
news groups and post away, after you get the hang of it, it will take
about 30 seconds for each newsgroup! **REMEMBER, THE MORE
NEWSGROUPS YOU POST IN, THE MORE MONEY YOU** WILL
MAKE!! BUT YOU HAVE TO POST A MINIMUM OF 200** That's it!
You will begin reciving money from around the world within days!
You may eventually want to rent a P.O.Box due to the large amount
of mail you will receive. If you wish to stay anonymous, you can
invent a name to use, as long as the postman will deliver it. **JUST
MAKE SURE ALL THE ADDRESSES ARE CORRECT.** Now the
WHY part: Out of 200 postings, say I receive only 5 replies (a very
low example). So then I made $5.00 with my name at #6 on the
letter. Now, each of the 5 persons who just sent me $1.00 make the
MINIMUM 200 postings, each with my name at #5 and only 5
persons respond to each of the original 5, that is another $25.00 for
me, now those 25 each make 200 MINIMUM posts with my name at
#4 and only 5 replies each, I will bring in an additional $125.00!
Now, those 125 persons turn around and post the MINIMUM 200 with
my name at #3 and only receive 5 replies each, I will make an
additional $625.00! OK, now here is the fun part, each of those 625
persons post a MINIMUM 200 letters with my name at #2 and they
each only receive 5 replies, that just made me $3,125.00!!! Those
3,125 persons will all deliver this message to 200 newsgroups with
my name at #1 and if still 5 persons per 200 newsgroups react I will
receive $15,625,00! With a original investment of only $6.00!
AMAZING! When your name is no longer on the list, you just take
the latest posting in the newsgroups, and send out another $6.00 to
names on the list, putting your name at number 6 again. And start
posting again. The thing to remember is, do you realize that
thousands of people all over the world are joining the internet and
reading these articles everyday, JUST LIKE YOU are now!! So can
you afford $6.00 and see if it really works?? I think so... People have
said, "what if the plan is played out and no one sends you the
money? So what! What are the chances of that happening when
there are tons of new honest users and new honest people who are
joining the internet and newsgroups everyday and are willing to give
it a try? Estimates are at 20,000 to 50,000 new users, every day,
with thousands of those joining the actual internet. Think about this!
If you gamble your money away in a casino or a race track, or
maybe just the lottery...WHY? Because we all want more
$$$!RIGHT? So we risk our money! Playing it against the odds!
NEED MONEY? Well if you have any logic and $6 You will! You think
this is a gamble? Maybe! But its not odds your up against; INSTEAD
YOUR OWN INTEGRITY! You NEED MONEY? Play FAIRLY and
HONESTLY, WITH FULL INTEGRITY! And you will be making some
SERIOUS CASH!!! $$ GO FOR IT $$
Article: 18087Grrrr. Bloody hell. All I want is the flipping user manual and attribute passing manual. (Which I suspect that synposys does not do on a par with synplify but how the hell am I supposed to find out unless I can get hold off the manual? Any synopsys employees hello?) Does anyone have either of these two documents? Otherwise I guess I'll just have to go switch to synplify. Cheers -- --------------------------------------------------------------------------------------------- David Braendler http://gene.bsee.swin.edu.au/daveb/index.htm Centre for Intelligent Systems Swinburne University of Technology --------------------------------------------------------------------------------------------Article: 18088
Someone said to me that FPGA´s are poor performers. Is this right? Could someone give me a speed comparison, for example between a modern PC-CPU and an fast Xilinx FPGA? thanxArticle: 18089
Stephan Diemer wrote: > > Someone said to me that FPGA´s are poor performers. Is this right? Could > someone give me a speed comparison, for example between a modern PC-CPU > and an fast Xilinx FPGA? > thanx In http://www.sussex.ac.uk/~tapu9/list_publ.html have a look in the paper: "A VHDL implementation of an on-board ACF application targeting FPGAs". In the second page of the long abstract (mapld99.pdf) there is a table showing a performance comparison between an FPGA and a microcontroller. For this application the FPGA implementation is faster than the microcontroller one, but for other cases it will depend on the application. Eduardo.Article: 18090
Stephan Diemer <s.diemer@gmx.de> wrote in message news:37F1E779.32CA1EDA@gmx.de... > Someone said to me that FPGA´s are poor performers. Is this right? Could > someone give me a speed comparison, for example between a modern PC-CPU > and an fast Xilinx FPGA? > thanx For one thing, 'performance' is a broad term. It can refer to: speed, density, temperature range, radiation hardening, power consumption, time-to-market, cost and a host of other issues. In terms of part speeds, they are poor performers when compared to ASIC or GaAs parts. They are very good performers when compared to discrete logic parts. In terms of time-to-market and development costs, they are very good performers. -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.eduArticle: 18091
Poor performers relative to what? For many regular tasks (ones that are repeated for many samples) as you usually find in DSP applications, you can see performance gains over a CPU of anywhere from 10x to 1000x depending on the application and the implementation. FPGAs allow you to obtain low level parallelism (doing many basic operations at once) that is not possible with a microprocessor. For example, if you need to sum a bunch of data points, the processor has to do one addition at a time, where the FPGA can do them all at once using an adder tree. I routinely do DSP designs in FPGAs with data sample rates over 100 MS/sec. Applications include radar and wireless communications. Operations done in the FPGA include demodulation, filtering, radar signal processing etc. Even the fastest CPUs would only be capable of doing one or two instructions per sample, which is totally inadequate for the complex functions above. Stephan Diemer wrote: > Someone said to me that FPGA´s are poor performers. Is this right? Could > someone give me a speed comparison, for example between a modern PC-CPU > and an fast Xilinx FPGA? > thanx -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18092
XC18*** by Xilinx is beeing released right now. Catalin Baetoniu Keren wrote: > Hello, > > I am looking for a substitut component for the XC17*** PROM by Xilinx. > * Flash Memory or EEMemory > * ISP Programing thrugh JTag. > > Thank you > > KerenArticle: 18093
If you're not afraid to build something, you can gather up the ISP documents for all the parts you intend to program, then design a circuit which meets all the contstraints and build it yourself. That's probably the least costly way to manage this problem. Dick On Wed, 22 Sep 1999 11:34:11 -0700, "John Becich" <johnbecich@csi.com> wrote: >I have seen the pdf file on how to build an inexpensive in-circuit >programming link to the parallel port of a PC. > >Suppose I would like to have an inexpensive way to program chips that is not >an in-circuit method. Perhaps something that connects to the parallel port >of the same PC that I am using to generate source and object code for these >chips...I burn the chips, and stick them into sockets on my breadboard....Of >course I must be careful about static electricity. > >Any suggestions would be appreciated. Can I get something for a couple >hundred bucks? > >I prefer Altera and Lattice chips. > >Thanks, >John > >Article: 18094
Hello, I am trying to find out how to program a Xilinx Spartan XCS40XL with an Atmel serial EEPROM rather than using the Xilinx serial PROMs. The goal is to be able to easily reprogram the FPGA. Can anyone give me some direction on which Atmel part to use and how to hook it up to the FPGA? I am using the Master programming mode. Any help would be greatly appreciated. Thanks. Paul M.Article: 18095
"John Becich" <johnbecich@csi.com> wrote: >I have composed a large source file using Altera's version 9.3 of Max+Plus. >It is a ".tdf" file. > >I have used a few megafunctions in this file, by "including" the related >".inc" file for each megafunction I desired. > >I had to create my own FIFO circuit, because the megafunctions provided by >Altera were inappropriate. I use graphic schematic entry, and saved the >file as a ".gdf" file. I wanted to compile that file and simulate it by >itself, but the compiler protested all the illegal inputs, outputs, etc. > >I would be satisfied just to put this circuit in my larger design and just >simulate the whole thing. I can't figure out how to get a .gdf file into my >.tdf file. > >Can you tell me how to do this? > >Thanks, >John > Generate an .inc file (File / Generate Default inc file) for the GDF and use it like the other Megafunctions. -- richard_damon@iname.com (Redirector to my current best Mailbox) rdamon@beltronicsInspection.com (Work Adddress) Richad_Damon@msn.com (Just for Fun)Article: 18096
--------------29CC0582E5CA2B014105EDF0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit If you are a synthesis user and aren't tuned into the (VHDL) Synthesis Interoperability Working Group (SIWG) then send any email to Majordomo@vhdl.org with the words "subscribe siwg" in the body to join the reflector. The working group also maintains the VHDL Synthesis Interoperability Working Group homepage. There is a discussion brewing there about the 1076.6 standard. To catch up look at the SWIG E-Mail Archive (Start with IEEE standard for VHDL RTL Synthesis for the beginning of the recent discussion). Whether you believe the standard is good or bad your contribution is important now for the future of the Level II version of this standard. Also, you should become a member of the IEEE Standards Association so that you can ballot (vote) on future standards. Join the Design Automation SubCommittee (DASC) to participate directly in the standards development process. If you (like me) balloted a negative vote on 1076.6 please email me. Thanks. -- Tim Davis Aspen Logic EM: TimDavis@AspenLogic.com WB: www.aspenlogic.com/~timdavis PH: +1 (303) 426-0800 FX: +1 (303) 426-1023 --------------29CC0582E5CA2B014105EDF0 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <body text="#000080" bgcolor="#FFFFFF" link="#0000FF" vlink="#800080" alink="#FF0000"> If you are a synthesis user and aren't tuned into the (VHDL) Synthesis Interoperability <br>Working Group (SIWG) then send any email to Majordomo@vhdl.org with the <br>words "subscribe siwg" in the body to join the reflector. The working group also <br>maintains the <a href="http://www.vhdl.org/siwg/">VHDL Synthesis Interoperability Working Group</a> homepage. <p>There is a discussion brewing there about the 1076.6 standard. To catch up look <br>at the SWIG <a href="http://www.vhdl.org/siwg/hm/index.html">E-Mail Archive</a> (Start with <a href="http://www.vhdl.org/siwg/hm/0245.html">IEEE standard for VHDL RTL Synthesis</a> <br>for the beginning of the recent discussion). <p>Whether you believe the standard is good or bad your contribution is <br>important now for the future of the Level II version of this standard. <br>Also, you should become a member of the IEEE Standards Association so <br>that you can ballot (vote) on future standards. Join the Design Automation <br>SubCommittee (DASC) to participate directly in the standards development <br>process. <p>If you (like me) balloted a negative vote on 1076.6 please email me. <p>Thanks. <p>-- <p>Tim Davis <br>Aspen Logic <p>EM: TimDavis@AspenLogic.com <br>WB: www.aspenlogic.com/~timdavis <br>PH: +1 (303) 426-0800 <br>FX: +1 (303) 426-1023 <br> <br> </body> </html> --------------29CC0582E5CA2B014105EDF0--Article: 18097
You'll have to check how large the configuration is for your FPGA. If less than 1 megabit, I'd recommend the AT17LV010. It's a small PLCC which is easy to use with a socket. I can't recall the name of the document, but Atmel has application notes for making the correct connections between the FPGA and configuration device. Regards, Jamie Paul Mondello wrote in message <37f223f1.0@newsfeed.vitts.com>... >Hello, > >I am trying to find out how to program a Xilinx Spartan XCS40XL with an >Atmel serial EEPROM rather than using the Xilinx serial PROMs. The goal is >to be able to easily reprogram the FPGA. > >Can anyone give me some direction on which Atmel part to use and how to hook >it up to the FPGA? I am using the Master programming mode. > >Any help would be greatly appreciated. Thanks. > >Paul M. > >Article: 18098
Pardon me if this is an obvious question. I don't need an explicit reset
pin since all flip-flops are reset on initialization anyway. How do I get
foundation express to use GSR without having to waste a pin for it? If I
remove reset from the top level port list, it complains. If I set it to
zero, it complains. If I instiantiate the STARTUP module, but don't drive
reset it complains. If I remove the reset net all together, it complains
and flip flops may not be reset to the correct level (if negative ones are
inferred). Do you always have to waste a pin for a redundant reset line?
module toplevel(clk,reset,in,out);
input clk, reset, in;
output out;
reg out;
always @(posedge clk or posedge reset)
if(reset) out=0;
else out=in;
endmodule
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 18099Depends. If your doing FPGAs, then I recommend VHDL over Verilog. The reason for this, is although Verilog is easier to learn, it is not well suited for the occasional low level stuff that comes up in FPGAs. With VHDL, you can at least take a stab at specifying placement in the code and can get the control over implementation when needed. If youre doing ASICs in the US, then you'll probably want to use verilog, as that seems to be the standard. In Europe, ASIC work is more VHDL. Nick wrote: > Hello, > I have been teaching myself about FPGAs using Xilinx Foundation Series > 1.5. I would like to get a textbook on VHDL to learn with also. Is there > any consensus as to which is better to learn, Verilog or VHSIC HDL ? > I have heard that they are both widely used, but verilog is easier. > Also, dose anyone know where I can get a used text on this subject in > the St. Pete area of Florida ? > Thanks in advance. > -Nick -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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