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XESS makes (is making) a board with the Virtex: http://www.xess.com/prod014.htmlArticle: 17926
For both soft and hard PCI cores in an ORCA FPGA Check out http://www.lucent.com/micro/fpga/csc.html Regards, Mike. Robert Sefton wrote in message <37DE8BFA.75C6574C@cosinecom.com>... >Has anyone successfully ported a PCI core to the Lucent Orca 3T family? >If so, who was the core vendor? Also, how fast did you run it and what, >if any, major problems did you encounter? > >Thanks, > >-- > >-------------------------- >-- >-- Robert Sefton >-- Senior Design Engineer >-- >-- CoSine Communications >-- 1200 Bridge Parkway >-- Redwood City, CA 94065 >-- >-- Direct: 650.637.2441 >-- Main: 650.637.4777 >-- Fax: 650.637.2412 >-- >--------------------------Article: 17927
The Programmable Logic Jump Station at http://www.optimagic.com/index.shtml provides links to most topics related to FPGAs, their applications, and various support software and services. -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Lupu Cristian <sea12@ee.utt.ro> wrote in message news:37D93DC6.10432AF@ee.utt.ro... > Hi there! > > I'm new to FPGA and I'll be glad to receive any tutorial or > descriptive material from any gold-hearted group user :o) > Many thanks in advance. > > Chris. >Article: 17928
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Article: 17929On Thu, 16 Sep 1999 16:10:54 -0400, Arthur Dardia <ahdiii@webspan.net> wrote: >I was recently given 5 of these my a friend. What do I need to learn and get to >program these? All I have are the chips. I'd like to build a DES cracker out >of the five chips for a science project that shows how the government is holding >back our crytography technology by keeping the strength of exportable crypto >limited. Is it possible to put all 5 of these processors in parallel and have >them crunch away? How would I program them, and in what language? Where can I >learn? Any tutorails or books I could get? My friend used to work at Xilinx >and National Semiconductor. He said that he'd try to get me some more stuff if >I need it, such as the programming software. I have stacks of books from Xilinx >on their chips, but I don't understand a word in them. Please give me resources >and/or help. > > Thanks, > Art Dardia These are not processors, but, rather, should be viewed as a bucket of parts. Interconnecting the available resources is accomplished by programming an external EPROM or EEPROM from which the device automatically self-loads a configuration. Building this configuration is accomplished by means of software provided by the device manufacturer, for less than $100 but only until Sept 30. After that, the price, listed as $495 in the Digi-Key catalog, goes back up. These are substantial devices capable of the task you suggest, provided, of course, that you know how to do it, and provided that you are knowledgable in its implementation. If you send off for the software, be sure to obtain the device data book as well. It is normally provided free of charge. DickArticle: 17930
What complete software development tools are available as freeware either from vendors or third parties for purposes of develping CPLD/FPGA devices? I've obtained quite a number of free or nearly free tool sets only to find that they lack some key part which one must obtain from a third party, without which the development task cannot be completed. Typically, the missing part is either a schematic entry or HDL tool or a "real" simulator, though other components are often left out. The missing pieces all partially disable the development task. The level of this limitation ranges from significantly hobbling the tool, to making it TOTALLY useless. What I'd like to see is a list of tools, all of which are sufficient in and of themselves to complete the design/development task yet represent a VERY small investment so I can essentially evaluate not only the devices they support but the tool suite as well. As a "hired-gun" I'm not willing to speculate/invest in numerous software tools incapable of completing the entire job, and ultimately leading to a finger-pointing session wherein the various involved suppliers simply answer, " that's not ours . . . we can't help you there" when a problem arises. Any recommendations? DickArticle: 17931
Hi ,
some questions from a beginner.
- did I have enough controll with VHDL to implement High Speed Designs
(DSP)
or should I use e.g Schematic entry ?
- the FPGA Vendors provide complete core solutions like Filter,
Correlator, Transformer...
Now, what is the challenge for me if I have ready to use components
?
- which FPGA is "better" suited for DSP : Xilinx - Atmel
Greetinx, Cemal
Article: 17932
There is actually a new category of devices that integrate both a
microcontroller and programmable logic.
One such set of devices is the Triscend E5 Configurable System-on-Chip
(CSoC) family. These devices include:
* An 8051/52-compatible 8032 "Turbo" microcontroller
- About 2.5 times faster than the original 8051 operating at the same
clock frequency
- 40 MHz performance
- All the standard 8052 peripherals plus a watchdog-timer, two-channel
DMA controller, integrated debugger, wait-state control
* A large block of programmable logic (ranging from 5,000 to 40,000 gates)
- Logic cell based on Look-Up Table (LUT) and flip-flop (512 to 3,200
cells on a single device)
- SRAM-based
- Integrated connectivity to the system bus (address, data, chip select,
DMA control, wait-state, breakpoint)
* A high-performance internal system bus
- Connects the programmable logic to the rest of the system
- Integrated address decoding for easy, single-cycle interfaces
- Access to DMA controllers, wait-state control, breakpoint control
- Up to 40 MHz guaranteed performance
* A large bank of byte-wide system RAM (from 16K bytes to 64K bytes)
- Single-cycle access
- Available to processor and DMA
- Data or code storage
Why an integrated device? Well, there are some things that a
microcontroller does better and there are others better suited to
programmable logic. Here are a few examples.
MICROCONTROLLERS ARE BETTER because ...
* They re-use a common piece of logic for all functions. The CPU executes
the function sequentially using the same silicon resulting in lowest costs
for moderate-performance applications.
* They are easy to program and to modify. Leverage existing processor
design tools and infrastructure. In the case of the Triscend devices,
they're binary compatible with the 8051/52 and consequently can use the same
assemblers, compilers, source files, etc.
* They are better at complex control functions. It's conceptually easier to
program and maintain a function in 'C' on a processor with a known timing
behavior than to code it as a giant state machine in VHDL or Verilog and map
it to logic device with variable timing performance.
PROGRAMMABLE LOGIC IS BETTER because ...
* You can build just about any digital logic function that you want. Is the
processor short a dozen timers, a few UARTs, need a few more PWMs, or more
interrupts? No problem, you can build these in programmable logic. In the
case of Triscend, the FastChip development system includes some
commonly-used "soft" modules that you can drag-and-drop into the
programmable logic.
* Programmable logic is better at real-time response. A processor might
take a few microseconds to milliseconds to respond to a _single_ event.
Programmable logic can respond to _multiple_ events in nanoseconds to
microseconds.
* Programmable logic is better at bit manipulation. Need to swap a few
bits? Just change the wiring between the bits.
* Programmable logic is better at any function that can exploit parallelism.
Assume you have two functions. On a processor, you must execute these
functions sequentially, re-using the same CPU. On programmable logic, you
can build two copies of the logic to implement the desired function and
operate them in parallel. Programmable logic can implement digital signal
processing (DSP) functions orders of magnitude faster than most DSP
processors.
Trade-offs:
Microcontroller: Additional functionality costs you additional time
(cost is constant, or buy a faster processor)
Programmable logic: Additional functionality costs you additional
silicon (time can be constant)
The COMBINATION OF A MICROCONTROLLER AND PROGRAMMABLE LOGIC, integrated on a
single device is better because ...
* The microcontroller signals (address, data, control) are distributed to
the programmable logic, within the same package.
- Saves I/O pins (about 18-20 pin for most 8032-type designs)
- Reduces power consumption and decreases noise (EMI)
* The integrated device is generally less expensive than multiple discrete
devices assembled on a PC board.
* Higher integration with resulting lower manufacturing costs and higher
reliability
* A single integrated debugging environment for hardware and software.
* You can offload performance-critical functions from the microcontroller to
the programmable logic. You can offload the complex control functions to
the microcontroller. You can optimize the design and get the best of both
worlds.
For additional information, please visit the Triscend (www.triscend.com)
website, especially the Online Learning Center
(http://www.triscend.com/learning/IndexSelfPaced.html). There is also some
information available from the last few Embedded Systems Conferences
(www.embedded.com). Their site doesn't seem to be working at the moment so
I'll post some additional links later.
--
Steven K. Knapp
Triscend Corporation
301 N. Whisman Rd.
Mountain View, CA 94043 USA
Tel: 650-968-8668 x-166, FAX: 650-934-9393
sknapp@triscend.com, Web: www.triscend.com
<vortekdoug@my-deja.com> wrote in message
news:7rj41c$nvo$1@nnrp1.deja.com...
> In article <37BE90C5.D41BA8EF@tinet.fut.es>,
> Daniel Figuerola Estrada <pfa@tinet.fut.es>
> wrote:
> > I am making a project in wich I compare
> advantages and disadvantages in
> > using microcontrollers and FPGA in the design of
> a digital system.
> >
> > Has anyone worked with those two technologies
> and could give his opinion
> > of them?
> >
> >
> --------------------------------------------------
> ----------------------
> > ////////////////////////////////\
> ("`-''-/").___..--''"`-.__
> > // Marcel Figuerola Estrada // `6_ 6 )
> `-. ( ).`-.__.`)
> > // pfa@tinet.fut.es // (_Y_.)'
> ._ ) `._ `.``-..-'
> > // Valls - Catalunya - Europe //
> _..`--'_..-_/ /--'_.' ,'
> > \//////////////////////////////// (il),-''
> (li),' ((!.-'
> >
> --------------------------------------------------
> ----------------------
> >
> I have to agree with Jashua (Msg 9).
> You will never get a microcontroller that is the
> perfect fit. I always need one more counter or
> PWM.
> The last system I did uses a 80C32 and a Xilinx
> 5202. The 5202 has decode logic, PWM controls, an
> SPI port, and an application specific frequncy
> measurement circuit.
> The FPGA can do things like the frequency counter
> easily. The micro just reads it when interupted.
> There is almost no software overhead.
> The flexibility is great. I redid the SPI port in
> two days when anouther engineer put an oddball
> Burr Brown A/D onto the serial bus. We did not
> have to redo boards, or change any parts.
> Here is the kicker: 80C32 => $1.60, XC5202 =>
> $7.50. That is hard to beat for totally custom
> hardware.
>
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.
Article: 17933I think this book may help: The Designer's Guide to VHDL is both a comprehensive manual for the language and an authoritative reference on its use in hardware design at all levels, from system level down to gate level. Using the IEEE standard for VHDL, the author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Requiring only a minimal background in programming, this is an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD. http://www.amazon.com/exec/obidos/ASIN/1558602704/iversonsoftwarecA On Tue, 14 Sep 1999 20:44:23 GMT, leejp@my-deja.com wrote: >For years now, I have programmed simple PALs using the free PALASM >package from AMD (now Vantis). While PALASM is still adequate for much >of the designs that I do (mostly 26V12, 22V10 and 16V8 designs), I >will be doing some bigger devices in the near future (small MACH devices >and such) and wish to start learning VHDL since it is more "industry >standard". > >So I'm looking for a free (or low cost) VHDL package with a reasonable >learning curve that I can use to program simple PALs and small FPGA's. > >Additionally, is there a book or manual that addresses such >applications? Most VHDL stuff I've seen tend to concentrate heavily on >the software side. > >Thanks, > > >Sent via Deja.com http://www.deja.com/ >Share what you know. Learn what you don't. Kind Regards, Jeff Iverson -- Iverson Software Co. 612-571-5013 6281 NE 6th St. j5rson@iversonsoftware.com Minneapolis MN 55432 http://www.iversonsoftware.com/Article: 17934
I was impressed with the speed improvement I got when going from the M1.5i tools to the 2.1i release. I had 4000 series implementation passes that were typically in the 20+ hour range drop into the 6 to 12 hour range. Better device performance results with less floorplanning as well. - SteveArticle: 17935
All credit to xilinx on 2.1i with service pack 1. I have definitely seen a massive improvement in the tools (over 1.5i). Still some way to go but they are getting there. A. Steve McDowell <srmcd@marrakesh.mv.com> wrote in message news:37e27bfa@News.Destek.net... > I was impressed with the speed improvement I got when going from the M1.5i > tools to the 2.1i release. I had 4000 series implementation passes that were > typically in the 20+ hour range drop into the 6 to 12 hour range. Better > device performance results with less floorplanning as well. > > - Steve > > > >Article: 17936
From what I've heard, not only is the runtime faster, but device performance is also better. However, I was wondering how much to expect? Now I know this depends on the design itself, but this is my situation, I have a design that runs at 135 Mhz using 1.5i. (I am expecting to receive 2.1i a week from now) There is also no floorplanning done (I am using Virtex, which the Floorplanner says it will support in 2.1) Given that I will use extensive floorplanning, and also, using 2.1i, is it feasable that this design can run at 200 Mhz?Article: 17937
test -**** Posted from RemarQ, http://www.remarq.com/?a ****- Search and Read Usenet Discussions in your Browser - FREE -Article: 17938
Mark Summerfield <m.summerfield@ieee.org> wrote: > by Wakerly now covers VHDL and includes the Xilinx student edition > software. I haven't seen a copy of this book myself yet, but the > previous edition is a very good book, so I'd expect that the new edition > is worth checking out. Wow you like this book? Ugh, we used it for our digital logic class (senior level) and I thought it was *horrible* A really good general purpose digital logic book it put out by M. Morris Mano, forgot the exact name but it's an *excellent* book. I know that OrCad had this VHDL starter kit thingy with a small section by Paul Mench(sp?); I found that useful for introductory stuff. You may find free tools in the UNIX/Linux world, but I don't know of anything that does FPGAs + VHDL. I think there is a schematic capture package, free, called ChipMunk, perhaps it might be of some help. Good luck, while slightly off topic hope it was helpful. Vasant. remove no_spam to e-mailArticle: 17939
Vasant Ram wrote: > Mark Summerfield <m.summerfield@ieee.org> wrote: > > by Wakerly now covers VHDL and includes the Xilinx student edition > > software. I haven't seen a copy of this book myself yet, but the > > previous edition is a very good book, so I'd expect that the new edition > > is worth checking out. > > Wow you like this book? Ugh, we used it for our digital logic class > (senior level) and I thought it was *horrible* i had a wakerly book on uP's a long time ago that was good; don't know about his digital logic book. > A really good general > purpose digital logic book it put out by M. Morris Mano, forgot the exact > name but it's an *excellent* book. had that book over 20 years ago, very good. my friend bought the new edition, said it too was good (and obviously more up to date, he got tired of reading my history books). > I know that OrCad had this VHDL starter > kit thingy with a small section by Paul Mench(sp?); I found that useful > for introductory stuff. You may find free tools in the UNIX/Linux world, > but I don't know of anything that does FPGAs + VHDL. I think there is a > schematic capture package, free, called ChipMunk, perhaps it might be of > some help. actel has vhdl + sim + schematic + fpga free (for a while). other packages are around $99 or so. http://www.optimagic.com/ has stuff on free and low cost s/w. rkArticle: 17940
Hi I use Synplify version 5.21. Version 5.21 cannot find counters as the previous version v5.08a does. Ver.5.21 finds 1 counter while v5.08a finds 5 counters in my same design. This is valid for the target Xilinx Spartan 30 device, and I wonder if v521 cause Design Manager not to use carry logic for the 'missing' counters. Maybe it is better to use older version of Synplify in such a condition Does anyone observed such a situation?Thank you for your time, OzgurArticle: 17941
Isn't the current "full" release of Synplify Version 5.1.5a ? 5.21 appears to be their interim "emergency-release" to support FLEX20K. Which is a bit pointless as you are targeting Spartan. Cheers Stuart On Sat, 18 Sep 1999 12:46:31 +0300, Ozgur Kayalar <ozgurk@netas.com.tr> wrote: > >Hi >I use Synplify version 5.21. >Version 5.21 cannot find counters as the previous version v5.08a does. >Ver.5.21 finds 1 counter while v5.08a finds 5 counters in my same >design. >This is valid for the target Xilinx Spartan 30 device, and I wonder if >v521 cause Design Manager not to use carry logic for the 'missing' >counters. >Maybe it is better to use older version of Synplify in such a condition >Does anyone observed such a situation?Thank you for your time, >Ozgur > An employee of Saros Technology: Model Technology, Exemplar Logic, TransEDA, Renoir. www.saros.co.ukArticle: 17942
Steve McDowell wrote: > > I was impressed with the speed improvement I got when going from the M1.5i > tools to the 2.1i release. I had 4000 series implementation passes that were > typically in the 20+ hour range drop into the 6 to 12 hour range. Better > device performance results with less floorplanning as well. > > - Steve anybody noticed any significiant improvement (CPU time and P&R quality) for the 4000 devices which have been designed by HDL codes? As far as I have understood, schematic-based design entry causes faster and better P&R results, since you have the floorplanner in the hand. On the other side, HDL-based design entry is difficult to floorplan. I want to know if there is a significiant improvement for HDL-based designs. Utku -- I feel better than James Brown.Article: 17943
Depends on how you do your HDL designs. If you code carefully you can get performance to meet that with schematics, but it might take a substantial amount of "pushing on a rope" to get the tools to produce what you want. Keeping the design hierarchical and labeling the components goes a long way toward making the graphical floorplanner usable for HDL designs. You can also embed placement in the HDL code using synplicity or exemplar, but it requires structural code to the primitive level, is time consuming, is generally not portable between synthesis tools, requires building your own library of some of the primitives, and can't be simulated easily until after mapping (and then the simulation is slow because it is working on LUTs and FF's instead of VHDL code). I've done several VDHL designs with extensive floorplanning...it can be done, but it is more work than doing it in schematics. Utku Ozcan wrote: > Steve McDowell wrote: > > > > I was impressed with the speed improvement I got when going from the M1.5i > > tools to the 2.1i release. I had 4000 series implementation passes that were > > typically in the 20+ hour range drop into the 6 to 12 hour range. Better > > device performance results with less floorplanning as well. > > > > - Steve > > anybody noticed any significiant improvement (CPU time and P&R quality) > for the 4000 devices which have been designed by HDL codes? As far as > I have understood, schematic-based design entry causes faster and better > P&R results, since you have the floorplanner in the hand. On the other > side, HDL-based design entry is difficult to floorplan. I want to know > if there is a significiant improvement for HDL-based designs. > > Utku > > -- > I feel better than James Brown. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17944
Programming FPGAs is not like programming microprocessors. It really is building a digital design out of logic primitives. To be successful, you really should have a strong background in digital logic design, especially with synchronous design techniques. Richard Erlacher wrote: > On Thu, 16 Sep 1999 16:10:54 -0400, Arthur Dardia <ahdiii@webspan.net> > wrote: > > >I was recently given 5 of these my a friend. What do I need to learn and get to > >program these? All I have are the chips. I'd like to build a DES cracker out > >of the five chips for a science project that shows how the government is holding > >back our crytography technology by keeping the strength of exportable crypto > >limited. Is it possible to put all 5 of these processors in parallel and have > >them crunch away? How would I program them, and in what language? Where can I > >learn? Any tutorails or books I could get? My friend used to work at Xilinx > >and National Semiconductor. He said that he'd try to get me some more stuff if > >I need it, such as the programming software. I have stacks of books from Xilinx > >on their chips, but I don't understand a word in them. Please give me resources > >and/or help. > > > > Thanks, > > Art Dardia > > These are not processors, but, rather, should be viewed as a bucket of > parts. Interconnecting the available resources is accomplished by > programming an external EPROM or EEPROM from which the device > automatically self-loads a configuration. > > Building this configuration is accomplished by means of software > provided by the device manufacturer, for less than $100 but only until > Sept 30. After that, the price, listed as $495 in the Digi-Key > catalog, goes back up. > > These are substantial devices capable of the task you suggest, > provided, of course, that you know how to do it, and provided that you > are knowledgable in its implementation. If you send off for the > software, be sure to obtain the device data book as well. It is > normally provided free of charge. > > Dick -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17945
Cemal Coemert wrote: > Hi , > some questions from a beginner. > > - did I have enough controll with VHDL to implement High Speed Designs > (DSP) > or should I use e.g Schematic entry ? VHDL does have the hooks to successfully pull off high speed DSP designs, but it can involve a substantial amount of "pushing on a rope" to get the tools to produce exactly what you want, especially when you are doing floorplanning. If you are starting out with FPGAs I recommend starting with schematics until you are very comfortable with the FPGA architecture and what circuit structures make for high speeds. VHDL intentionally hides the architectural details from the designer, so it is very easy to turn out designs that fall short of the mark because they fight the FPGA architecture rahter than play with it. For high speed designs, you will want to floorplan the design as well as tailor your design to the FPGA architecture. > > > - the FPGA Vendors provide complete core solutions like Filter, > Correlator, Transformer... > Now, what is the challenge for me if I have ready to use components > ? Most of the time, these cores either don't do exactly what you want or are not optimized to your needs. Many of the available cores are ports from ASIC cores that have not really been optimized to the FPGA architecture so they are bigger and slower than a design done from the bottom up for a particular FPGA family. Also, in DSP, there is usually more than one way to skin the cat. Often this involves modifying a function to perhaps do two steps at once. The CORES are generally "closed" so you are stuck with what you get. Hardware DSP design is more than just glueing blocks together. I've found that most of the time, the algorithm given to me to implement is one that came from a software solution. More than likely, the port from software to hardware is not a one-to-one. The relative costs of resources in each realm is different so the best solution is also different. A good hardware DSP designer has to be prepared to dig into the algorithm to understand the motivation for the approach presented, and then come up with alternate approaches to solving the problem. > - which FPGA is "better" suited for DSP : Xilinx - Atmel > DSP designs generally contain alot of arithmetic, so you want a device with a capable carry chain. That puts Atmel chips at a considerable disadvantage for most serious DSP applications (bit serial designs are an exception since the carry chain isn't needed there). The carry chain allows you to make very fast arithmetic elements without resorting to area intensive speedups for the carry inherent in artihmetic.A more viable alternative to Xilinx for DSP applications are the Altera 10K and Apex families, as these parts do have carry chains. I do prefer Xilinx 4K and Virtex over the Altera devices for DSP for several reasons however: first, the Altera carry logic reduces the LE cell to a three input function, one of which is for the carry input. THat means that arithmetic functions are limited to two inputs if the logic is to stay in a single level (desirable for speed)...accumulators with load or clear, adder-subtractors etc need to use two levels of logic in Altera 10K, also the clock enable uses one of the LUT inputs, so clock-enabled arithmetic has only one input in Altera 10K. APEX improves the situation slightly by adding dedicated clock enable and synchronous load/clear controls to the cell. DSP designs also typically require many delay queues - filtering for example depends on delaying the signal. The xilinx 4K and virtex chips allow you to use the CLB as a delay queue or shift register so you can delay a bit up to 16 clocks in one LUT (half a 4K CLB or half a virtex slice), leading to area efficient delays. Altera does not have this capability, so delay queues have to be constructed from the registers in the LE's (logic elements), which will quickly eat up the logic resource for even modest word-wide delay queues. Also, altera's I/) cell can only be registered in one direction at a time, so interfaces to high speed external memory or other bidirectional devices is handicapped and can have timing that is sensitive to the place an route. Given the choice, I'll take the Xilinx over Altera for DSP applications. Altera is still quite capable (and I've done a number of those designs), but just not as capable as the Xilinx architecture. Most of the other players don't have carry chains, which for me is a non-starter in DSP apps. > Greetinx, Cemal -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17946
There's a small chance, but without floorplanning and also paying attention to the design implementation I doubt you'll get there. The tools are better, but they are not miracle cures. The virtex floorplanner does work in 2.1 (I was using it yesterday). James Yeh wrote: > From what I've heard, not only is the runtime faster, but device > performance is also better. However, I was wondering how much to > expect? > > Now I know this depends on the design itself, but this is my situation, > I have a design that runs at 135 Mhz using 1.5i. (I am expecting to > receive 2.1i a week from now) > > There is also no floorplanning done (I am using Virtex, which the > Floorplanner says it will support in 2.1) > > Given that I will use extensive floorplanning, and also, using 2.1i, is > it feasable that this design can run at 200 Mhz? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17947
With FPGAs, and assuming devices with "zero" static Icc, by far the most important factor in the dynamic Icc level is how much clock gating is being done. If you use the global clock nets then you will be wasting maybe 90% of your power just charging and discharging those. However clock gating is a dodgy practice in FPGA designs, and different vendors' devices can work better or worse. I know about this, having done some ASIC prototyping in FPGAs, and the ASIC had to be very low power. The sort of figures I had were 20mA with global clock nets, 4mA with lots of gating (and a very layout-sensitive design which would be a real hazard if used in production), 1mA with the real ASIC. >Which manufacturers are presently claiming to be the lowest power? I know >Quicklogic and Actel (and others) go back and forth about who is fastest. >But who is the lowest power (given identical clock rates, func, etc.)? > >I know Phillips/Xilinx Coolrunner is low power, but those are mainly for >gate intensive designs. My application is flip-flop intensive. > >Thanks in advance, >Keith Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 17948
I have designs which use a lot of loadable arithmetic, of the type :
if load = '1' then
sum <= a;
else
sum <= a + b;
end if;
I've just run one of these designs which was implemented in a 4000-xla-09
device (slowest available) through synthesis and p&r targeted to a
Virtex -4 device (slowest available), and was suprised to find that it
consumed 20 % more resources, and only ran about 10 % faster.
I've tracked most of this poor performance down to the loadable arithmetic,
which in the XLA devices consumed roughly 1 LUT per
bit, but in Virtex consume 2. This is because the arithmetic is being split
into a carry chain column and a seperate column for the loadable registers.
Looking at the structure of a Virtex slice (I'm very new to Virtex's), I
can't see any way to implement loadable arithmetic as efficiently as in
the XLA devices. Can anyone offer any insights into this ?. I'm hoping that
i've missed something, as the 20 % LUT overhead wipes out any cost benefits
of moving to Virtex, and the slow speed puts a damper on any plans to run at
the advertised clock rates.
I can't find any examples of a better implementation in Coregen (which
doesn't seems to support Virtex arithmetic). Should I wait for VirtexE ?.
--
Edward Moore
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