Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"B. Joshua Rosen" wrote: > Are you sure that Synopsis didn't throw out half of your design. In my > experience when one synthesis tool gets results that are twice as good > as another it's because of a bug that causes the tool to throw out logic > that it shouldn't. I've never seen this happen in Verilog, but I've seen > happen several times with VHDL. I assume that you mean Synplify (from Synplicity) and not FPGA Express (from Synopsis). These names are easily confused... Yes, I'm sure. Actually, this design is what started me looking at Synliplify. I first tried the design with FPGA Express/Synopsis and the logic was several times larger than what I thought it should be. After a lot of searching, I tracked it down to a small ROM that I use for the DES S-Boxes. I could synthesize this ROM by itself with both tools and see a large difference. Synplify/Synplicity took exactly the amount of logic required. And of course I did a timing simulation on the end results to verify that everything was working... David Kessner davidk@free-ip.comArticle: 17826
David Kessner wrote in message <37D674FC.6D631CB4@free-ip.com>... >After a lot of searching, I tracked it down to a small ROM that >I use for the DES S-Boxes. I could synthesize this ROM by >itself with both tools and see a large difference. Synplify/Synplicity >took exactly the amount of logic required. right, synplify can infer xilinx rams and roms; fpga express is brain-dead in that regard. I requested an eval license from synplify a couple of weeks ago and even spoke to a sales-droid on the phone but as yet i haven't gotten the license. so i can't run that test. -- a my shift key is not working. sorry. ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu The Republican Party: "We've upped our standards. Now, up yours!"Article: 17827
I received the following report from my Norton 2000 Virus checker. Has anyone else seen this? Date: 9/3/99, Time: 22:16:24, SYSTEM on GYPSYLOU The file virtex_arch.ppt in compressed file C:\bin\fndtn\userware\training\virtex_arch.zip was infected with the XM.Laroux.AF virus. The file was repaired. Date: 9/3/99, Time: 22:16:24, SYSTEM on GYPSYLOU Virus scanning completed. Items scanned: C:-E: Master boot records: Scanned: 1 Infected: 0 Repaired: 0 Boot records: Scanned: 3 Infected: 0 Repaired: 0 Files: Scanned: 100365 Infected: 1 Repaired: 1 Quar'ed: 0 Deleted: 0Article: 17828
Check this out: http://www.xilinx.com/techdocs/5658.htm Whenever you have a problem like this, always visit http://support.xilinx.com to search for solutions/workarounds. Cheers! Bennet wannarat wrote: > Hello > I have problem when I download to CPLD > It's have error with JTAG program. "not found xc9572_ver2.bsd" > I can't load to CPLD how can I solve this problem > Regard > Wannarat Suntiamorntut > ksuwanna@kmitl.ac.thArticle: 17829
On Wed, 01 Sep 1999 21:48:30 -0700, Wayne Miller <wayne@aerial-imaging.com> wrote: >Anyone have any experience (good or bad) with FPGAs from QuickLogic? > I've used them extensively, starting with their first generation and going up to the current parts. I've done maybe 25 different designs using QuickLogic parts. The upside? The devices are fast, a particular advantage for me because my preferred design flow is verilog, with all the inefficiency that entails. My last design ran at over 100 MHz without resorting to any schematic capture or manual intervention, and it was reasonably complex. Their tools are superior to many other vendors. They provide schematic capture, verilog/vhdl synthesis (Synplify), a good text editor (codewright), and fast and efficient place and route tools. Their support is also excellent - I've had much better results with their support than any of their larger competitors. The downside? Their devices are smaller in terms of gate count than the latest offerings from Xilinx or Altera, and a lot of folks are put off by their one-time programmability. However, with careful design and simulation that's really not too much of a drawback, IMHO. Check out their Web site - you can get an eval copy of the tools that's good for 3 days, I think. That might be enough time to try one of your designs in their devices and see how you like them. Nick SteffenArticle: 17830
David Kessner <davidk@free-ip.com> wrote in message news:37D3CDFA.7FC48550@free-ip.com... > As someone else pointed out, I've found at least one application > that Synopsis FPGA Express totally died on. Same thing here. FPGA Express (even 3.2) seems to have serious problems with wide decoding. It would take about an hour to synthesize a register interface with a hundred or so adresses. At first I thought the problem was 12 inches in front of the monitor, but then somebody told me he had the exact same problem! Then I tried Synplify, which crunched the entire 100k gates design in 5 minutes...Article: 17831
You may try with Actel's SX devices. One of my friend designed ATM phone with 155Mhz speed, which could easily with -1 speed grade of SX and Actel now offer the fastes -3 speed grade. Phil Hays wrote: > thiru1457@my-deja.com wrote: > > > I intend to implement a logic in FPGA (roughly > > 12K logic gates complexity), running at 200 MHz. > > > > Is it possible to implement the above design, > > with the current FPGA technology?. > > It is impossible to estimate practicality or effort needed without any > more information. > > The size is no problem. > > The speed might be a problem. The path from flip flop, through any > routing and/or logic, to setup into the next flip flop needs to be 5 ns > or less for all paths (with a few exceptions) for a design running at > 200 MHz. To route a signal a significant distance may well take several > ns. To get a design to work at such speeds there can be at most only a > few levels of logic between each flip flop, and not much routing, or > perhaps a longer route (or a route with large fanout), and a single > 4in-LUT (four input look up table). > > The layout of the design also matters because longer routes take more > time. If the design is regular and needs to communicate only to a few > of the nearest neighbor logic cells then it might be made to run very > fast. If communication needs to be very general, it might be very hard > to make run fast. If the design is regular and rectangular it might be > made to run very fast. Very irregular logic is very difficult to place. > Some non rectangular logic is hard to place, and some is fairly easy. > > If your design is already structured into simple logic between pipeline > stages that can be easily floorplanned into a regular rectangular > structure, a design like this might be done in 2 to 6 person weeks by an > experienced FPGA designer. > > It also might take a few person years of effort to fit the design into > the next generation of FGPAs, defined for this statement as twice as > fast as the current generation. > > It's also very possible that your design can't be done with existing > FPGAs at all, even assuming a factor of two speedup for the next > generation, regardless of effort, regardless of experience. > > The questions you need to ask are: > 1) can the design be pipelined "enough"? (How much time will this > take?) > 2) what is the "shape" of the parts of design? How can they be > floorplanned to minimize route lengths and delays? > > Best of luck. > > -- > Phil Hays > "Irritatingly, science claims to set limits on what > we can do, even in principle." Carl SaganArticle: 17832
Hi Winkzer, You need XILINX app. note 151, avaliable at their website. Good luck, David. Winzker wrote: > If you want to change the RAM contents with minimal CAD effort > you could try to change (i.e. patch) the bit-file for configuration. > There is an application note from Xilinx, describing their data format. > (Sorry, I don't know the number.) > > It looks complicated at first, but once you have understood the format, > you (or your computer) have easy access to every single bit in the RAMs. > > I admit, that I have not tried to fumble with these bits. > Has anybody out there done so? > Has anybody out there done so with success? > > Regards, Marco > > --- > Marco Winzker > Liesegang electronics Gmbh, Hannover, Germany > Only speaking for myselfArticle: 17833
Hello To permit Leonardo to recognize a function has a (d/s)pram, the depth of the ram shall not be more than the depth of 2 LUTs (if 2 LUTs inside one macrocell), which is 32 => 5 address bits. (as you did it with coregen). Good luck. Michel Le Mer Gerpi sa http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi. htm Andreas Johnsson <emwjjj@emw.ericsson.se> a écrit dans le message : 37D62353.3BAC963B@emw.ericsson.se... > I've tried to make a generic Dual Port RAM for Xilinx XC4000 in VHDL for > use with Leoanardo with no success. I started making a Single Port RAM > in this way: > > LIBRARY ieee ; > USE ieee.std_logic_1164.all; > USE ieee.numeric_std.all; > > ENTITY GEN_RAM IS > ERIC( > g_width : integer := 16; > g_depth : integer := 64 > ); > PORT( > addr : in integer range g_depth-1 downto 0 ; > cp : in std_logic ; > di : in unsigned (g_width-1 downto 0) ; > we : in std_logic ; > do : out unsigned (g_width-1 downto 0) > ); > END GEN_RAM ; > > architecture gen_ram_architecture of GEN_RAM is > type mem_type is array (g_depth-1 downto 0) of unsigned(g_width-1 > downto 0); > signal mem : mem_type; > begin > process(cp) > begin > if rising_edge(cp) then > if we='1' then mem(addr) <= di; end if; > end if; > end process; > do<=mem(addr); > end gen_ram_architecture; > > This worked just fine and I got RAM blocks generated by Leoanardo. But > then I changed the design to make it Dual Port in this way: > > LIBRARY ieee ; > USE ieee.std_logic_1164.all; > USE ieee.numeric_std.all; > > ENTITY GEN_DPRAM IS > GENERIC( > g_width : integer := 16; > g_depth : integer := 64 > ); > PORT( > cpw : in std_logic ; > di : in unsigned (g_width-1 downto 0) ; > raddr : in integer range g_depth-1 downto 0 ; > waddr : in integer range g_depth-1 downto 0 ; > we : in std_logic ; > do : out unsigned (g_width-1 downto 0) > ); > END GEN_DPRAM ; > > architecture gen_dpram_architecture of GEN_DPRAM is > type mem_type is array (g_depth-1 downto 0) of unsigned(g_width-1 > downto 0); > signal mem : mem_type; > begin > process(cpw, raddr) > begin > if rising_edge(cpw) then > if we='1' then mem(waddr) <= di; end if; > end if; > end process; > do<=mem(raddr); > end gen_dpram_architecture; > > This code compiled fine, but only generated a huge amount of > combinatorial logic and flip-flopps and no DPRAM blocks. What did i do > wrong! > > /AndreasArticle: 17834
I am working with a group at Caltech developing a PCI board set using the
PC-MIP daughter cards for I/O. We have one PC-MIP with a Spartan FPGA
for the bus interface and an XCV300 for processing. There are two digital
camera interfaces, ZBT RAM and a 170MHz RAMDAC. There is a passive PCI
carrier card that holds two PC-MIPs and the low voltage power supplies.
Another active carrier (two XCV1000s and lots of RAM) is under development.
Right now I am looking for either academic or commercial people who would
be interested in using the board set. As a fair warning, we are still
developing interfaces and drivers for the board so I am not ready to talk
to end users.
More information about PC-MIP can be found at:
http://www.greenspring.com/
Thanks,
--
Steve Nordhauser
Embedded Systems Manager Phone: (518) 283-7500
InterScience, Inc. Fax: (518) 283-7502
105 Jordan Road email: nords@intersci.com
Troy, NY 12180 web: http://www.intersci.com
"Any sufficiently advanced technology is
indistinguishable from magic."
- Arthur C. Clarke
Daryl Bradley wrote:
>
> have a look at www.xess.com
>
> THey have a virtex board coming soon with memory on it
> Haven't looked at the specs but maybe suitable?
> Sukandar Kartadinata wrote in message <37C4E4CA.DFC1D45C@zkm.de>...
> >well, almost.
> >but I need that 32bit access
> >
> >Daryl Bradley wrote:
> >
> >> Take a look at www.vcc.com
> >>
> >> The virtual workbench has 16meg on it in1Mb x 16 bits SDRAM (maybe ok for
> >> you?)
> >>
> >> >I'm looking for a Virtex development board that has (supports) at least
> >> >16MBytes (or rather 4Mwords with 32bits word width, or 2Mx64bits) of
> >> >fast SDRAM.
> >> >Even better would be a board with two memory interfaces.
> >
> >
> >
Article: 17835Bennet An <bennet.an@xilinx.com> wrote in message news:37D6EE06.CDC6C0C1@xilinx.com... > Check this out: > > http://www.xilinx.com/techdocs/5658.htm > > Whenever you have a problem like this, always visit > http://support.xilinx.com > to search for solutions/workarounds. > > Cheers! > > Bennet > > wannarat wrote: > > > Hello > > I have problem when I download to CPLD > > It's have error with JTAG program. "not found xc9572_ver2.bsd" > > I can't load to CPLD how can I solve this problem > > Regard > > Wannarat Suntiamorntut > > ksuwanna@kmitl.ac.th > > >Article: 17836
Chad Bearden <ebeard@compuserve.com> wrote: : I received the following report from my Norton 2000 Virus checker. Has : anyone else seen this? : Date: 9/3/99, Time: 22:16:24, SYSTEM on GYPSYLOU : The file virtex_arch.ppt in compressed file : C:\bin\fndtn\userware\training\virtex_arch.zip was infected with the : XM.Laroux.AF virus. : The file was repaired. : Date: 9/3/99, Time: 22:16:24, SYSTEM on GYPSYLOU : Virus scanning completed. : Items scanned: C:-E: [snip] : Files: : Scanned: 100365 : Infected: 1 : Repaired: 1 : Quar'ed: 0 : Deleted: 0 *Most* virus-checking programs can exhibit false positives. /If/ this is one of those the file may have been modified incorrectly. Perhaps examine the file virtex_arch.ppt in compressed file C:\bin\fndtn\userware\training\virtex_arch.zip to see if this could be important. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com LSD melts in your mind, not in your hand.Article: 17837
OK, Would someone please break US export law and send me the FreeDES design files that I can't download from the link below, because I'm British. That reminds me, I must renew my subscription to International Terrorist Weekly... Cheers... mark@woodstec.freeserve.co.uk Phil Hays <spampostmaster@sprynet.com> wrote in message news:37CF5C53.4501B839@sprynet.com... > I now have an evaluation copy of Exemplar's LS. I've done a little with > the cores offered by the FreeIP page: > > http://www.free-ip.com/ > > I downloaded the FreeDES and Free6502 source files, and had a look at > them. I have several comments: > > 1) I can't yet get Leonardo Spectrum to do "Extended Optimization > Effort" on the FreeDES design, as this computer has only 64 MB of > memory, and LS seems to need about twice that. The memory is on order, > I'll get it next week. Not that it really matters much, but Synplify > (sum of several processes) seems to top out at 26 MB. Memory is fairly > cheap compared to the tools, I would forgive a tool for needing more > memory if it just did a better job. But so far, the size of resulting > output from LS is inbetween the results of Synplify and FPGA Express. I > will post results when I can have the tool do all optimizations for > size. I also want to look at speed. > > 2) The Free6502 core is an interesting design, as I think it could be > made to run at a rather higher clock rate. To do this, I'm going to > make some suggestions for change in a step by step fashion. I suppose I > might just propose a final design, but perhaps the step by step fashion > will allow for a better discussion as to why I want to make these > changes to speed up this design. These changes may require microcode > changes: I'm not going to do that. These changes will require running a > regression test to insure that the processor is still doing all > instructions correctly: I would run such a regression test if it was > automatic, but will not otherwise. > > The longest path starts at the microcode address , goes through the ALU > and into the flags logic. This path involves most of the design. As it > is such a large amount of logic, and as it is the critical path, let us > start by adding a pipeline register. > > The first change I propose is to add a pipeline register between the > output of the Microcode ROM and the rest of the design. This will > reqire adding an extra state to the "state" statemachine that we might > call "decode", may require changes to the step counter and may require > microcode changes, both of which I did not do. State "decode" will > always follow after "fetch". This might add a clock to every > instruction, however any but will increase the clock rate from the > original 28.5 MHz to something over 45 Mhz (I did xilinx par using a > slower -4 part and hit 45 Mhz). > > > In the file free6502.vhd: > > type STATES is (RESET1, RESET2, FETCH, DECODE, START_IRQ, START_NMI, > RUN); > ^add > -- The main state machine > process (clk, reset, nmi_event, irq_reg, i_flag, done) > begin > if reset='1' then > state <= RESET1; > elsif clk'event and clk='1' then > case state is > when RESET1 => state <= RESET2; > when RESET2 => state <= RUN; > when FETCH => state <= DECODE; -- change > when DECODE=> state <= RUN; -- change > > -- The microcode step counter > process (clk, reset, state) > begin > if reset='1' then > step<="000"; > elsif clk'event and clk='1' then > case state is > when RESET1 => step <= "000"; > when RESET2 => step <= "000"; > when FETCH => step <= "000"; > when START_IRQ => step <= "000"; > when START_NMI => step <= "000"; > when DECODE => step <= step + 1; -- change > > In the file MICROCODE.VHD: > > architecture mc_rom_arch of mc_rom is > signal addr :std_logic_vector (10 downto 0); > signal DONE_c : MCT_DONE; > signal ADDR_OP_c : MCT_ADDR_OP; > signal DIN_LE_c : MCT_DIN_LE; > signal RD_EN_c : MCT_RD_EN; > signal DOUT_OP_c : MCT_DOUT_OP; > signal DINT1_OP_c: MCT_DINT1_OP; > signal DINT2_OP_c: MCT_DINT2_OP; > signal DINT3_OP_c: MCT_DINT3_OP; > signal PC_OP_c : MCT_PC_OP; > signal SP_OP_c : MCT_SP_OP; > signal ALU1_c : MCT_ALU1; > signal ALU2_c : MCT_ALU2; > signal ALU_OP_c : MCT_ALU_OP; > signal A_LE_c : MCT_A_LE; > signal X_LE_c : MCT_X_LE; > signal Y_LE_c : MCT_Y_LE; > signal FLAG_OP_c : MCT_FLAG_OP; > begin > -- > addr <= opcode & step; > -- > Process(clk) begin > if rising_edge(clk) then > DONE <= DONE_c; > ADDR_OP <= ADDR_OP_c; > DIN_LE <= DIN_LE_c; > RD_EN <= RD_EN_c; > DOUT_OP <= DOUT_OP_c; > DINT1_OP <= DINT1_OP_c; > DINT2_OP <= DINT2_OP_c; > DINT3_OP <= DINT3_OP_c; > PC_OP <= PC_OP_c; > SP_OP <= SP_OP_c; > ALU1 <= ALU1_c; > ALU2 <= ALU2_c; > ALU_OP <= ALU_OP_c; > A_LE <= A_LE_c; > X_LE <= X_LE_c; > Y_LE <= Y_LE_c; > FLAG_OP <= FLAG_OP_c; > end if; > end process; > > U00: DONE_rom port map (addr, DONE_c); > U01: ADDR_OP_rom port map (addr, ADDR_OP_c); > U02: DIN_LE_rom port map (addr, DIN_LE_c); > U03: RD_EN_rom port map (addr, RD_EN_c); > U04: DOUT_OP_rom port map (addr, DOUT_OP_c); > U05: DINT1_OP_rom port map (addr, DINT1_OP_c); > U06: DINT2_OP_rom port map (addr, DINT2_OP_c); > U07: DINT3_OP_rom port map (addr, DINT3_OP_c); > U08: PC_OP_rom port map (addr, PC_OP_c); > U09: SP_OP_rom port map (addr, SP_OP_c); > U10: ALU1_rom port map (addr, ALU1_c); > U11: ALU2_rom port map (addr, ALU2_c); > U12: ALU_OP_rom port map (addr, ALU_OP_c); > U13: A_LE_rom port map (addr, A_LE_c); > U14: X_LE_rom port map (addr, X_LE_c); > U15: Y_LE_rom port map (addr, Y_LE_c); > U16: FLAG_OP_rom port map (addr, FLAG_OP_c); > end mc_rom_arch; > > > -- > Phil Hays > "Irritatingly, science claims to set limits on what > we can do, even in principle." Carl SaganArticle: 17838
Hi there!
I'm new to FPGA and I'll be glad to receive any tutorial or
descriptive material from any gold-hearted group user :o)
Many thanks in advance.
Chris.
Article: 17839Assuming that you had access the designs .ADB file, the best that you might hope for is to export a technology specific netlist that could serve as the baseline for regression based testing and/or incorporating new modifications. You can export a netlist from Actel Designer by selecting File -> Export from the main menu bar... from the Export dialog box choose "Netlist File" for File Type, choose "VHDL", "VERILOG", or "EDIF" for Format (depending on preference).Article: 17840
Chad Bearden wrote: > I received the following report from my Norton 2000 Virus checker. Has > anyone else seen this? This issue has been documented and is currently being addressed. Check out: http://support.xilinx.com/techdocs/7428.htm Regards, rohit > Date: 9/3/99, Time: 22:16:24, SYSTEM on GYPSYLOU > The file virtex_arch.ppt in compressed file > C:\bin\fndtn\userware\training\virtex_arch.zip was infected with the > XM.Laroux.AF virus. > The file was repaired. > > Date: 9/3/99, Time: 22:16:24, SYSTEM on GYPSYLOU > Virus scanning completed. > Items scanned: C:-E: > Master boot records: > Scanned: 1 > Infected: 0 > Repaired: 0 > Boot records: > Scanned: 3 > Infected: 0 > Repaired: 0 > Files: > Scanned: 100365 > Infected: 1 > Repaired: 1 > Quar'ed: 0 > Deleted: 0Article: 17841
Nicolas Bier wrote: > > David Kessner <davidk@free-ip.com> wrote in message > news:37D3CDFA.7FC48550@free-ip.com... > > As someone else pointed out, I've found at least one application > > that Synopsis FPGA Express totally died on. > > Same thing here. FPGA Express (even 3.2) seems to have serious problems with > wide decoding. It would take about an hour to synthesize a register > interface with a hundred or so adresses. At first I thought the problem was > 12 inches in front of the monitor, but then somebody told me he had the > exact same problem! > > Then I tried Synplify, which crunched the entire 100k gates design in 5 > minutes... one more comment: I have not used FPGA Express intensively but I always use Synplify (5.22). The synthesizer seems to be very fast and easy to use. There are many synthesis algorithm parameters the designer can use, such as directives, attributes, global clock frequency, FSM options. I have had enough time to perform parametric synthesis via Tcl codes, and I have tested two XC40150XV FPGA's (30,000 lines of Verilog code) under the allowable parameter region of the tool, like fanout, FSM style and global clock frequency. My observation is that the synthesizer performance does not change when I play with the parameters. The internal algorithms must be more flexible and more sensitivite to the parameters. Utku -- I feel better than James Brown.Article: 17842
Hi Folks, I am in search of some information regarding the local routing resources provided in the Virtex Architecture. I am specifically referring to the connection pattern in the Local Interconnection Matrix (LIM). I know that the output multiplexer(OMUX) is fully populated (i.e any of the 13 CLB outputs can drive any of the eight output pins) but the input multiplexer(IMUX) is not (i.e. every CLB input pin CANNOT connect to every input signal of the IMUX). I was wondering if anyone had some information regarding the pattern in which the inputs to the IMUX are connected to the inputs of the CLB. I know of the pattern that is used in XC5200 but havent been able to find the information for Virtex. Please email or post any information or pointers u may have regarding the connection pattern of the IMUX in Virtex. Thanks in advance, Vijay -- Architecture and Real-time Lab 310 Knowles Engg. Bldg. UMass, Amherst, MA 01003 email: vlakamra@ecs.umass.eduArticle: 17843
I am implementing a design in VHDL using xilinx Foundation software, (Synopsys FPGA express). I have a largish design with several levels, and I wish to have the overall module be the same each time it is instantiated in hardware ( to save on design compilation) . I know that it is possible to use EPIC to create hard macros, but that seems like a major effort. EPIC strikes me as a particularly unfriendly bit of software. Synplicity tools seems able to include attribute of RLOC - according to the application notes in the latest XCELL journal - but I'm not using Synplicity. I found an reference to an attribute called RELATIVE_LOCATION using FPGA express, but there is very little help to go on there. ( There is no actual entry for RELATIVE_LOCATION) Has someone used this feature before in one of their designs and know how to proceed?? Also I came across mention that FPGA express supports attributes in version 3.1 ( the version I have) but will provide more support for this in version 3.2. Can anyone shed some light on what the extra support will be and when version 3.2 will be released??? Cheers -- --------------------------------------------------------------------------------------------- David Braendler http://gene.bsee.swin.edu.au/daveb/index.htm Centre for Intelligent Systems Swinburne University of Technology --------------------------------------------------------------------------------------------Article: 17844
My point of view: Altera have (had) a better development system, but xilinx chips are cheaper. Altera doesn't provide internal 3-state signals, and emulates them with logic (a lot of logic !). eng. Davide Rizzo Yannis Mitsos wrote: > I would like to know which are the major differences between the PLD's > of the above companies. I have worked with ALTERA FLEX series. > > Thanks > > YannisArticle: 17845
Hi All, I am a Foundation Express 1.5i user. I had recently some problems with my Operating System (Windows 95), I was obliged to reinstall it again along with all the software I had on machine (including Foundation software). Now, I have a problem with Foundation software. When I implement my project, the translation phase goes fine, but as soon as the mapping phase starts, I get the following error: ******** This program has performed an illegal operation and will be shut down. If the problem persists, contact the program vendor. ******** The program terminates abnormally. What should I do? Cheers,Article: 17846
I think the original question was regarding the CPLDs rather than the FPGAs. I'm not as familiar with the CPLD side of things (My business has been pretty much exclusively FPGA designs since 1994), so I'll defer to those who use them more regularly. FOr the FPGA side of things there are distinct differences between Altera and Xilinx, both in the silicon and the tools, that will usually tip the scales one way or the other. Which way the scale tips depends heavily on the design. The Xilinx advantages: 1) Ability to use CLB as small RAMs or for delay queues - In DSP applications, there is a frequent need for signal delays. Such delays are expensive in Altera because they need to use an LE for each clock cycle of delay for each bit (ie an 8 bit bus needs to use 64 LEs for an 8 clock delay). Xilinx CLB RAM lets you do that in 6 4K CLBs or 2 virtex CLBs. 2) Xilinx has a very capable arithmetic carry chain. Altera's carry chain splits the 4 LUT inthe LE into a pair of 3 LUTs with one input dedicated to carry. That means any arithmetic function with more than two inputs (an accumulator with clear or and adder/subtractor for example) requires two levels of logic and the interconnect between the levels must use the relatively slow row routing. The xilinx carry chain structure has a 4 LUT available so you can do 3 input arithmetic in one level of logic. For heavily arithmetic designs, such as those typically found in signal processing, the xilinx carry architecture is clearly superior. In the 10K, using a clock enable also uses one of the LUT inputs, so registered arithmetic functions using the clock enable are limited to one input. 3) The Xilinx IOB allows you to register bidirectional I/O in both directions in the I/O cell (the tristate control has to be registered in the core in 4K except the 4K-XLA), which permits higher I/O speeds and less sensitivity to placement. The Altera IOB has only one register, so either the input or the output of a bidirectional I/O can't be registered at the IOB. That makes the I/O timing sensitive to placement and limits performance of high speed bidirectional interfaces unless you use two pins. 4) Xilinx has a strong local interconnect which can yeild high clock rates if the designer is willing to take the steps to do the necessary floorplanning. This can also be a disadvantage as well since high performance Xilinx designs demand floorplanning. Xilinx is the better choice for data path designs, especially ones that have delay queues, lots of arithmetic or high speed bidirectional I/O (such as memory). Altera advantages: 1) virtually all the interconnect is essentially global. This makes timing relatively independent of placement, therefore placement is not usually an issue for performance. Floorplanning an Altera is generally not required. 2) Interconnect within a LAB is very fast. For state machines and wider combinatorial logic functions this fast local interconnect makes for very fast designs. 3) Tools are easier to use. There are very few "expert" controls to fiddle with to get a high performance design working. 4) The routing structure and no requirement for floorplanning makes it easier for synthesis to generate a design that meets timing requirements. The downside here is that there is not all that much the user can do to push the performance beyond what is obtained with a design structured for the array architecture. For state machines, random logic and decodes Altera is generally a better choice than Xilinx on technical merits. Altera is also more "synthesis friendly" than xilinx, especially in these designs. Davide Rizzo wrote: > My point of view: > Altera have (had) a better development system, but xilinx chips are > cheaper. > Altera doesn't provide internal 3-state signals, and emulates them with > logic (a lot of logic !). > eng. Davide Rizzo > > Yannis Mitsos wrote: > > > I would like to know which are the major differences between the PLD's > > of the above companies. I have worked with ALTERA FLEX series. > > > > Thanks > > > > Yannis -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17847
You are right about macros generated under EPIC. Add to your comments that a design using those macros is a pain in the tail for simulation - you are pretty much stuck simulating the mapped design or later, which makes the simulation dreadfully slow. I haven't tried directing placement under FPGA express in almost a year now, so there may be improvements. When I last tried it it didn't accept user attributes (which you need to use to put RLOCs in the netlist) and it optimized FMAPs out of the design. I understand you can now put user attributes in FPGA express code, so you may be able to coax the tools into passing RLOCs to the netlist. I've heard that the latest version still optimizes FMAPs out, so you still won't be able to place or map LUTs. To put placement in your VHDL, you will need to describe your design structurally at the primitive level. Not a job for the faint at heart. You will probably need to create a package containing black boxes for the xilinx primitives. The carry chain can be painful because the carry in at the first bit may not be connected which will make the tools yell at you. You also have to preserve the hierarchy in elaboration, because the flattened design will screw up the RLOCs. FWIW, I haven't had much luck with synplicity's xRLOC attribute either, but I have been able to do placement with synplicity using my own RLOC attribute and primitives. You might look at http://www.riverside-machines.com/pub2/xilinx/vhdl_rpm/top.htm for good info on floorplanning under VHDL. david braendler wrote: > I am implementing a design in VHDL using xilinx Foundation software, > (Synopsys FPGA express). I have a largish design with several levels, > and I wish to have the overall module be the same each time it is > instantiated in hardware ( to save on design compilation) . > > I know that it is possible to use EPIC to create hard macros, but that > seems like a major effort. EPIC strikes me as a particularly unfriendly > bit of software. Synplicity tools seems able to include attribute of > RLOC - according to the application notes in the latest XCELL journal - > but I'm not using Synplicity. > > I found an reference to an attribute called RELATIVE_LOCATION using FPGA > express, but there is very little help to go on there. ( There is no > actual entry for RELATIVE_LOCATION) Has someone used this feature before > in one of their designs and know how to proceed?? > > Also I came across mention that FPGA express supports attributes in > version 3.1 ( the version I have) but will provide more support for this > in version 3.2. Can anyone shed some light on what the extra support > will be and when version 3.2 will be released??? > > Cheers > > -- > --------------------------------------------------------------------------------------------- > David Braendler http://gene.bsee.swin.edu.au/daveb/index.htm > Centre for Intelligent Systems > Swinburne University of Technology > -------------------------------------------------------------------------------------------- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17848
In article <37BE90C5.D41BA8EF@tinet.fut.es>,
Daniel Figuerola Estrada <pfa@tinet.fut.es>
wrote:
> I am making a project in wich I compare
advantages and disadvantages in
> using microcontrollers and FPGA in the design of
a digital system.
>
> Has anyone worked with those two technologies
and could give his opinion
> of them?
>
>
--------------------------------------------------
----------------------
> ////////////////////////////////\
("`-''-/").___..--''"`-.__
> // Marcel Figuerola Estrada // `6_ 6 )
`-. ( ).`-.__.`)
> // pfa@tinet.fut.es // (_Y_.)'
._ ) `._ `.``-..-'
> // Valls - Catalunya - Europe //
_..`--'_..-_/ /--'_.' ,'
> \//////////////////////////////// (il),-''
(li),' ((!.-'
>
--------------------------------------------------
----------------------
>
I have to agree with Jashua (Msg 9).
You will never get a microcontroller that is the
perfect fit. I always need one more counter or
PWM.
The last system I did uses a 80C32 and a Xilinx
5202. The 5202 has decode logic, PWM controls, an
SPI port, and an application specific frequncy
measurement circuit.
The FPGA can do things like the frequency counter
easily. The micro just reads it when interupted.
There is almost no software overhead.
The flexibility is great. I redid the SPI port in
two days when anouther engineer put an oddball
Burr Brown A/D onto the serial bus. We did not
have to redo boards, or change any parts.
Here is the kicker: 80C32 => $1.60, XC5202 =>
$7.50. That is hard to beat for totally custom
hardware.
Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17849david braendler wrote in message <37DCD79C.E4D05FA2@swin.edu.au>... >Also I came across mention that FPGA express supports attributes in >version 3.1 ( the version I have) but will provide more support for this >in version 3.2. Can anyone shed some light on what the extra support >will be and when version 3.2 will be released??? I'm not sure how much support there is for rlocs in 3.2 but FPGA Express 3.2 shipped with foundation 2.1i which has been out for a couple of weeks now. best a -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z